X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=sim%2Ffrv%2Fprofile.h;h=cae20c4b580ce5c0ca2025fa49071738a8693e18;hb=2662c237a9219b0863535b8b99be383add2cf0b9;hp=80cf58350237f9e89a34e126ea891f5aaad95171;hpb=b34f6357d032f4b39f9c7adb1995956d04339461;p=binutils-gdb.git diff --git a/sim/frv/profile.h b/sim/frv/profile.h index 80cf5835023..cae20c4b580 100644 --- a/sim/frv/profile.h +++ b/sim/frv/profile.h @@ -1,26 +1,27 @@ /* Profiling definitions for the FRV simulator - Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright (C) 1998-2021 Free Software Foundation, Inc. Contributed by Red Hat. This file is part of the GNU Simulators. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ #ifndef PROFILE_H #define PROFILE_H +#include "frv-desc.h" + /* This struct defines the state of profiling. All fields are of general use to all machines. */ typedef struct @@ -39,15 +40,19 @@ typedef struct int fr_busy[64]; /* Cycles until FR is available. */ int acc_busy[64]; /* Cycles until FR is available. */ int ccr_busy[8]; /* Cycles until ICC/FCC is available. */ + int spr_busy[4096]; /* Cycles until spr is available. */ int idiv_busy[2]; /* Cycles until integer division unit is available. */ int fdiv_busy[2]; /* Cycles until float division unit is available. */ int fsqrt_busy[2]; /* Cycles until square root unit is available. */ + int float_busy[4]; /* Cycles until floating point unit is available. */ + int media_busy[4]; /* Cycles until media unit is available. */ int branch_penalty; /* Cycles until branch is complete. */ int gr_latency[64]; /* Cycles until target GR is available. */ int fr_latency[64]; /* Cycles until target FR is available. */ int acc_latency[64]; /* Cycles until target FR is available. */ int ccr_latency[8]; /* Cycles until target ICC/FCC is available. */ + int spr_latency[4096]; /* Cycles until target spr is available. */ /* Some registers are busy for a shorter number of cycles than normal depending on how they are used next. the xxx_busy_adjust arrays keep track @@ -68,6 +73,8 @@ typedef struct int branch_hint; /* hint field from branch insn. */ USI branch_address; /* Address of predicted branch. */ USI insn_fetch_address;/* Address of sequential insns fetched. */ + int mclracc_acc; /* ACC number of register cleared by mclracc. */ + int mclracc_A; /* A field of mclracc. */ /* We need to know when the first branch of a vliw insn is taken, so that we don't consider the remaining branches in the vliw insn. */ @@ -84,6 +91,19 @@ typedef struct #define DUAL_REG(reg) ((reg) >= 0 && (reg) < 63 ? (reg) + 1 : -1) #define DUAL_DOUBLE(reg) ((reg) >= 0 && (reg) < 61 ? (reg) + 2 : -1) +/* Return the GNER register associated with the given GR register. + There is no GNER associated with gr0. */ +#define GNER_FOR_GR(gr) ((gr) > 63 ? -1 : \ + (gr) > 31 ? H_SPR_GNER0 : \ + (gr) > 0 ? H_SPR_GNER1 : \ + -1) +/* Return the GNER register associated with the given GR register. + There is no GNER associated with gr0. */ +#define FNER_FOR_FR(fr) ((fr) > 63 ? -1 : \ + (fr) > 31 ? H_SPR_FNER0 : \ + (fr) > 0 ? H_SPR_FNER1 : \ + -1) + /* Top up the latency of the given GR by the given number of cycles. */ void update_GR_latency (SIM_CPU *, INT, int); void update_GRdouble_latency (SIM_CPU *, INT, int); @@ -94,37 +114,51 @@ void update_FR_latency (SIM_CPU *, INT, int); void update_FRdouble_latency (SIM_CPU *, INT, int); void update_FR_latency_for_load (SIM_CPU *, INT, int); void update_FRdouble_latency_for_load (SIM_CPU *, INT, int); +void update_FR_ptime (SIM_CPU *, INT, int); +void update_FRdouble_ptime (SIM_CPU *, INT, int); void decrease_ACC_busy (SIM_CPU *, INT, int); void decrease_FR_busy (SIM_CPU *, INT, int); void decrease_GR_busy (SIM_CPU *, INT, int); void increase_FR_busy (SIM_CPU *, INT, int); +void increase_ACC_busy (SIM_CPU *, INT, int); void update_ACC_latency (SIM_CPU *, INT, int); void update_CCR_latency (SIM_CPU *, INT, int); +void update_SPR_latency (SIM_CPU *, INT, int); void update_idiv_resource_latency (SIM_CPU *, INT, int); void update_fdiv_resource_latency (SIM_CPU *, INT, int); void update_fsqrt_resource_latency (SIM_CPU *, INT, int); +void update_float_resource_latency (SIM_CPU *, INT, int); +void update_media_resource_latency (SIM_CPU *, INT, int); void update_branch_penalty (SIM_CPU *, int); void update_ACC_ptime (SIM_CPU *, INT, int); +void update_SPR_ptime (SIM_CPU *, INT, int); void vliw_wait_for_GR (SIM_CPU *, INT); void vliw_wait_for_GRdouble (SIM_CPU *, INT); void vliw_wait_for_FR (SIM_CPU *, INT); void vliw_wait_for_FRdouble (SIM_CPU *, INT); void vliw_wait_for_CCR (SIM_CPU *, INT); void vliw_wait_for_ACC (SIM_CPU *, INT); +void vliw_wait_for_SPR (SIM_CPU *, INT); void vliw_wait_for_idiv_resource (SIM_CPU *, INT); void vliw_wait_for_fdiv_resource (SIM_CPU *, INT); void vliw_wait_for_fsqrt_resource (SIM_CPU *, INT); +void vliw_wait_for_float_resource (SIM_CPU *, INT); +void vliw_wait_for_media_resource (SIM_CPU *, INT); void load_wait_for_GR (SIM_CPU *, INT); void load_wait_for_FR (SIM_CPU *, INT); void load_wait_for_GRdouble (SIM_CPU *, INT); void load_wait_for_FRdouble (SIM_CPU *, INT); void enforce_full_fr_latency (SIM_CPU *, INT); +void enforce_full_acc_latency (SIM_CPU *, INT); int post_wait_for_FR (SIM_CPU *, INT); int post_wait_for_FRdouble (SIM_CPU *, INT); int post_wait_for_ACC (SIM_CPU *, INT); int post_wait_for_CCR (SIM_CPU *, INT); +int post_wait_for_SPR (SIM_CPU *, INT); int post_wait_for_fdiv (SIM_CPU *, INT); int post_wait_for_fsqrt (SIM_CPU *, INT); +int post_wait_for_float (SIM_CPU *, INT); +int post_wait_for_media (SIM_CPU *, INT); void trace_vliw_wait_cycles (SIM_CPU *); void handle_resource_wait (SIM_CPU *);