X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=sim%2Fmips%2Fcp1.h;h=5622b9384d9dd7c09939983fe7fd005e4206d770;hb=8a24927bc8dbf6beac2000593b21235c3796dc35;hp=3284445236551ee2c39c7f1d9947edc0b5daf0a8;hpb=b811d2c2920ddcb1adcd438da38e90912b31f45f;p=binutils-gdb.git

diff --git a/sim/mips/cp1.h b/sim/mips/cp1.h
index 32844452365..5622b9384d9 100644
--- a/sim/mips/cp1.h
+++ b/sim/mips/cp1.h
@@ -1,6 +1,6 @@
 /*> cp1.h <*/
 /* MIPS Simulator FPU (CoProcessor 1) definitions.
-   Copyright (C) 1997-2020 Free Software Foundation, Inc.
+   Copyright (C) 1997-2022 Free Software Foundation, Inc.
    Derived from sim-main.h contributed by Cygnus Solutions,
    modified substantially by Ed Satterthwaite of Broadcom Corporation
    (SiByte).
@@ -23,7 +23,7 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 #ifndef CP1_H
 #define CP1_H
 
-/* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR) 
+/* See sim-main.h for allocation of registers FCR0 and FCR31 (FCSR)
    in CPU state (struct sim_cpu), and for FPU functions.  */
 
 #define fcsr_FCC_mask      (0xFE800000)
@@ -40,6 +40,12 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 #define fcsr_RM_mask       (0x00000003)
 #define fcsr_RM_shift      (0)
 
+/* FCSR bits for IEEE754-2008 compliance.  */
+#define fcsr_NAN2008_mask       (0x00040000)
+#define fcsr_NAN2008_shift      (18)
+#define fcsr_ABS2008_mask       (0x00080000)
+#define fcsr_ABS2008_shift      (19)
+
 #define fenr_FS            (0x00000004)
 
 /* Macros to update and retrieve the FCSR condition-code bits.  This