X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=sim%2Fmips%2Fmips.igen;h=dfad422761558b2d11d03ef0368325200ae9615e;hb=8a24927bc8dbf6beac2000593b21235c3796dc35;hp=9f99912fb8568d2e78f2727668b484291a1f82c5;hpb=b16d63dac6655da82bd934b1a10e053776bffcb3;p=binutils-gdb.git diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 9f99912fb85..dfad4227615 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -46,8 +46,10 @@ :model:::mipsV:mipsisaV: :model:::mips32:mipsisa32: :model:::mips32r2:mipsisa32r2: +:model:::mips32r6:mipsisa32r6: :model:::mips64:mipsisa64: :model:::mips64r2:mipsisa64r2: +:model:::mips64r6:mipsisa64r6: // Vendor ISAs: // @@ -71,6 +73,12 @@ :model:::mips16e:mips16e: // m16e.igen :model:::mips3d:mips3d: // mips3d.igen :model:::mdmx:mdmx: // mdmx.igen +:model:::dsp:dsp: // dsp.igen +:model:::dsp2:dsp2: // dsp2.igen +:model:::smartmips:smartmips: // smartmips.igen +:model:::micromips32:micromips64: // micromips.igen +:model:::micromips64:micromips64: // micromips.igen +:model:::micromipsdsp:micromipsdsp: // micromipsdsp.igen // Vendor Extensions // @@ -88,7 +96,7 @@ // Pseudo instructions known by interp.c // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK -000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD +000000,5.*,5.*,5.*,5.OP,111001:SPECIAL:32::RSVD "rsvd " { SignalException (ReservedInstruction, instruction_0); @@ -96,7 +104,28 @@ -// Helper: +// Helpers: +// +// Check if given instruction is CTI, if so signal +// +:function:::void:signal_if_cti:instruction_word instr +{ + uint32_t maj = (instr & 0xfc000000) >> 26; + uint32_t special = instr & 0x3f; + if ((maj & 0x3e) == 0x06 /* Branch/Jump */ + || ((maj & 0x38) == 0 && !((maj & 0x6) == 0)) + || maj == 0x18 + || (maj & 0x37) == 0x32 + || (maj & 0x37) == 0x36 + || ((maj == 0) && (special == 0x9)) + /* DERET/ERET/WAIT */ + || ((maj == 0x10) && (instr & 0x02000000) + && (special == 0x1f || special == 0x18 || special == 0x20))) + { + SignalException (ReservedInstruction, instr); + } +} + // // Simulate a 32 bit delayslot instruction // @@ -109,12 +138,34 @@ CIA = CIA + 4; /* NOTE not mips16 */ STATE |= simDELAYSLOT; delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ + signal_if_cti (SD_, delay_insn); ENGINE_ISSUE_PREFIX_HOOK(); idecode_issue (CPU_, delay_insn, (CIA)); STATE &= ~simDELAYSLOT; return target; } +// +// Simulate a 32 bit forbidden slot instruction +// + +:function:::address_word:forbiddenslot32: +*mips32r6: +*mips64r6: +{ + instruction_word delay_insn; + sim_events_slip (SD, 1); + DSPC = CIA; + CIA = CIA + 4; + STATE |= simFORBIDDENSLOT; + delay_insn = IMEM32 (CIA); + signal_if_cti (SD_, delay_insn); + ENGINE_ISSUE_PREFIX_HOOK (); + idecode_issue (CPU_, delay_insn, (CIA)); + STATE &= ~simFORBIDDENSLOT; + return CIA + 4; +} + :function:::address_word:nullify_next_insn32: { sim_events_slip (SD, 1); @@ -136,9 +187,11 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *vr4100: *vr5000: *r3900: +*micromips32: { return base + offset; } @@ -146,6 +199,8 @@ :function:::address_word:loadstore_ea:address_word base, address_word offset *mips64: *mips64r2: +*micromips64: +*mips64r6: { #if 0 /* XXX FIXME: enable this only after some additional testing. */ /* If in user mode and UX is not set, use 32-bit compatibility effective @@ -153,7 +208,7 @@ Programmers Volume III, Revision 0.95, section 4.9. */ if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX)) == (ksu_user << status_KSU_shift)) - return (address_word)((signed32)base + (signed32)offset); + return (address_word)((int32_t)base + (int32_t)offset); #endif return base + offset; } @@ -174,29 +229,22 @@ *vr4100: *vr5000: *r3900: -{ - /* For historical simulator compatibility (until documentation is - found that makes these operations unpredictable on some of these - architectures), this check never returns true. */ - return 0; -} - -:function:::int:not_word_value:unsigned_word value *mips32: *mips32r2: -{ - /* On MIPS32, since registers are 32-bits, there's no check to be done. */ - return 0; -} - -:function:::int:not_word_value:unsigned_word value +*mips32r6: *mips64: *mips64r2: +*micromips32: +*micromips64: +*mips64r6: { - return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0)); +#if WITH_TARGET_WORD_BITSIZE == 64 + return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); +#else + return 0; +#endif } - // Helper: // // Handle UNPREDICTABLE operation behaviour. The goal here is to prevent @@ -220,8 +268,12 @@ :function:::void:unpredictable: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*micromips32: +*micromips64: +*mips64r6: { unpredictable_action (CPU, CIA); } @@ -262,7 +314,7 @@ // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo // to check for restrictions (2) and (3) above. // -:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new +:function:::int:check_mf_cycles:hilo_history *history, int64_t time, const char *new { if (history->mf.timestamp + 3 > time) { @@ -288,7 +340,7 @@ *vr4100: *vr5000: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); int ok = check_mf_cycles (SD_, history, time, "MT"); history->mt.timestamp = time; history->mt.cia = CIA; @@ -299,7 +351,7 @@ *mipsIV: *mipsV: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD) || check_mf_cycles (SD_, history, time, "MT")); history->mt.timestamp = time; @@ -310,11 +362,15 @@ :function:::int:check_mt_hilo:hilo_history *history *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *r3900: +*micromips32: +*micromips64: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); history->mt.timestamp = time; history->mt.cia = CIA; return 1; @@ -334,13 +390,17 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: +*micromips32: +*micromips64: { - signed64 time = sim_events_time (SD); + int64_t time = sim_events_time (SD); int ok = 1; if (peer != NULL && peer->mt.timestamp > history->op.timestamp @@ -366,151 +426,1398 @@ -// check_mult_hilo: -// -// Check for restriction (3) above (for ISAs/processors that have it) -// for MULT ops, and record timestamps for restriction (1) above. -// -:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo -*mipsI: -*mipsII: -*mipsIII: -*vr4100: -*vr5000: +// check_mult_hilo: +// +// Check for restriction (3) above (for ISAs/processors that have it) +// for MULT ops, and record timestamps for restriction (1) above. +// +:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo +*mipsI: +*mipsII: +*mipsIII: +*vr4100: +*vr5000: +{ + int64_t time = sim_events_time (SD); + int ok = (check_mf_cycles (SD_, hi, time, "OP") + && check_mf_cycles (SD_, lo, time, "OP")); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return ok; +} + +:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo +*mipsIV: +*mipsV: +{ + int64_t time = sim_events_time (SD); + int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD) + || (check_mf_cycles (SD_, hi, time, "OP") + && check_mf_cycles (SD_, lo, time, "OP"))); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return ok; +} + +:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo +*mips32: +*mips32r2: +*mips32r6: +*mips64: +*mips64r2: +*mips64r6: +*r3900: +*micromips32: +*micromips64: +{ + /* FIXME: could record the fact that a stall occured if we want */ + int64_t time = sim_events_time (SD); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return 1; +} + + +// check_div_hilo: +// +// Check for restriction (3) above (for ISAs/processors that have it) +// for DIV ops, and record timestamps for restriction (1) above. +// +:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo +*mipsI: +*mipsII: +*mipsIII: +*vr4100: +*vr5000: +*r3900: +{ + int64_t time = sim_events_time (SD); + int ok = (check_mf_cycles (SD_, hi, time, "OP") + && check_mf_cycles (SD_, lo, time, "OP")); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return ok; +} + +:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo +*mipsIV: +*mipsV: +{ + int64_t time = sim_events_time (SD); + int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD) + || (check_mf_cycles (SD_, hi, time, "OP") + && check_mf_cycles (SD_, lo, time, "OP"))); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return ok; +} + +:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo +*mips32: +*mips32r2: +*mips32r6: +*mips64: +*mips64r2: +*micromips32: +*micromips64: +*mips64r6: +{ + int64_t time = sim_events_time (SD); + hi->op.timestamp = time; + lo->op.timestamp = time; + hi->op.cia = CIA; + lo->op.cia = CIA; + return 1; +} + + +// Helper: +// +// Check that the 64-bit instruction can currently be used, and signal +// a ReservedInstruction exception if not. +// + +:function:::void:check_u64:instruction_word insn +*mipsIII: +*mipsIV: +*mipsV: +*vr4100: +*vr5000: +*vr5400: +*vr5500: +*r3900: +{ + // The check should be similar to mips64 for any with PX/UX bit equivalents. +} + +:function:::void:check_u64:instruction_word insn +*mips16e: +*mips64: +*mips64r2: +*mips32: +*mips32r2: +*mips32r6: +*micromips64: +*micromips32: +*mips64r6: +{ +#if 0 /* XXX FIXME: enable this only after some additional testing. */ + if (UserMode && (SR & (status_UX|status_PX)) == 0) + SignalException (ReservedInstruction, insn); +#endif +} + + + +// +// MIPS Architecture: +// +// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2) +// + + +:function:::void:do_add:int rs, int rt, int rd +{ + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + { + ALU32_BEGIN (GPR[rs]); + ALU32_ADD (GPR[rt]); + ALU32_END (GPR[rd]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_addi:int rs, int rt, uint16_t immediate +{ + if (NotWordValue (GPR[rs])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); + { + ALU32_BEGIN (GPR[rs]); + ALU32_ADD (EXTEND16 (immediate)); + ALU32_END (GPR[rt]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[rt]); +} + +:function:::void:do_andi:int rs, int rt, unsigned int immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], immediate); + GPR[rt] = GPR[rs] & immediate; + TRACE_ALU_RESULT (GPR[rt]); +} + +:function:::void:do_dadd:int rd, int rs, int rt +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + { + ALU64_BEGIN (GPR[rs]); + ALU64_ADD (GPR[rt]); + ALU64_END (GPR[rd]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_daddi:int rt, int rs, int immediate +{ + TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); + { + ALU64_BEGIN (GPR[rs]); + ALU64_ADD (EXTEND16 (immediate)); + ALU64_END (GPR[rt]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[rt]); +} + +:function:::void:do_dsll32:int rd, int rt, int shift +{ + int s = 32 + shift; + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = GPR[rt] << s; + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_dsra32:int rd, int rt, int shift +{ + int s = 32 + shift; + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = ((int64_t) GPR[rt]) >> s; + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_dsrl32:int rd, int rt, int shift +{ + int s = 32 + shift; + TRACE_ALU_INPUT2 (GPR[rt], s); + GPR[rd] = (uint64_t) GPR[rt] >> s; + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_dsub:int rd, int rs, int rt +{ + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + { + ALU64_BEGIN (GPR[rs]); + ALU64_SUB (GPR[rt]); + ALU64_END (GPR[rd]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_break:address_word instruction_0 +{ + /* Check for some break instruction which are reserved for use by the + simulator. */ + unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK; + if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) || + break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) + { + sim_engine_halt (SD, CPU, NULL, cia, + sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); + } + else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) || + break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) + { + if (STATE & simDELAYSLOT) + PC = cia - 4; /* reference the branch instruction */ + else + PC = cia; + SignalException (BreakPoint, instruction_0); + } + + else + { + /* If we get this far, we're not an instruction reserved by the sim. Raise + the exception. */ + SignalException (BreakPoint, instruction_0); + } +} + +:function:::void:do_break16:address_word instruction_0 +{ + if (STATE & simDELAYSLOT) + PC = cia - 2; /* reference the branch instruction */ + else + PC = cia; + SignalException (BreakPoint, instruction_0); +} + +:function:::void:do_clo:int rd, int rs +{ + uint32_t temp = GPR[rs]; + uint32_t i, mask; + if (NotWordValue (GPR[rs])) + Unpredictable (); + TRACE_ALU_INPUT1 (GPR[rs]); + for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i) + { + if ((temp & mask) == 0) + break; + mask >>= 1; + } + GPR[rd] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_clz:int rd, int rs +{ + uint32_t temp = GPR[rs]; + uint32_t i, mask; + if (NotWordValue (GPR[rs])) + Unpredictable (); + TRACE_ALU_INPUT1 (GPR[rs]); + for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i) + { + if ((temp & mask) != 0) + break; + mask >>= 1; + } + GPR[rd] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_dclo:int rd, int rs +{ + uint64_t temp = GPR[rs]; + uint32_t i; + uint64_t mask; + TRACE_ALU_INPUT1 (GPR[rs]); + for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i) + { + if ((temp & mask) == 0) + break; + mask >>= 1; + } + GPR[rd] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_dclz:int rd, int rs +{ + uint64_t temp = GPR[rs]; + uint32_t i; + uint64_t mask; + TRACE_ALU_INPUT1 (GPR[rs]); + for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i) + { + if ((temp & mask) != 0) + break; + mask >>= 1; + } + GPR[rd] = EXTEND32 (i); + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_lb:int rt, int offset, int base +{ + GPR[rt] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[base], + EXTEND16 (offset))); +} + +:function:::void:do_lh:int rt, int offset, int base +{ + GPR[rt] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[base], + EXTEND16 (offset))); +} + +:function:::void:do_lwr:int rt, int offset, int base +{ + GPR[rt] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[base], + EXTEND16 (offset), GPR[rt])); +} + +:function:::void:do_lwl:int rt, int offset, int base +{ + GPR[rt] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[base], + EXTEND16 (offset), GPR[rt])); +} + +:function:::void:do_lwc:int num, int rt, int offset, int base +{ + COP_LW (num, rt, do_load (SD_, AccessLength_WORD, GPR[base], + EXTEND16 (offset))); +} + +:function:::void:do_lw:int rt, int offset, int base +{ + GPR[rt] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[base], + EXTEND16 (offset))); +} + +:function:::void:do_lwu:int rt, int offset, int base, address_word instruction_0 +{ + check_u64 (SD_, instruction_0); + GPR[rt] = do_load (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset)); +} + +:function:::void:do_lhu:int rt, int offset, int base +{ + GPR[rt] = do_load (SD_, AccessLength_HALFWORD, GPR[base], EXTEND16 (offset)); +} + +:function:::void:do_ldc:int num, int rt, int offset, int base +{ + COP_LD (num, rt, do_load (SD_, AccessLength_DOUBLEWORD, GPR[base], + EXTEND16 (offset))); +} + +:function:::void:do_lbu:int rt, int offset, int base +{ + GPR[rt] = do_load (SD_, AccessLength_BYTE, GPR[base], EXTEND16 (offset)); +} + +:function:::void:do_ll:int rt, int insn_offset, int basereg +{ + address_word base = GPR[basereg]; + address_word offset = EXTEND16 (insn_offset); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr = vaddr; + if ((vaddr & 3) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, + sim_core_unaligned_signal); + } + else + { + uint64_t memval = 0; + uint64_t memval1 = 0; + uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + unsigned int shift = 2; + unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); + unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); + LoadMemory (&memval, &memval1, AccessLength_WORD, paddr, vaddr, + isDATA, isREAL); + byte = ((vaddr & mask) ^ (bigend << shift)); + GPR[rt] = EXTEND32 (memval >> (8 * byte)); + LLBIT = 1; + } + } +} + +:function:::void:do_lld:int rt, int roffset, int rbase +{ + address_word base = GPR[rbase]; + address_word offset = EXTEND16 (roffset); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr = vaddr; + + if ((vaddr & 7) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, + sim_core_unaligned_signal); + } + else + { + uint64_t memval = 0; + uint64_t memval1 = 0; + LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr, + isDATA, isREAL); + GPR[rt] = memval; + LLBIT = 1; + } + } +} + +:function:::void:do_lui:int rt, int immediate +{ + TRACE_ALU_INPUT1 (immediate); + GPR[rt] = EXTEND32 (immediate << 16); + TRACE_ALU_RESULT (GPR[rt]); +} + +:function:::void:do_madd:int rs, int rt +{ + int64_t temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); +} + +:function:::void:do_dsp_madd:int ac, int rs, int rt +{ + int64_t temp; + if (ac == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) + + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); + DSPLO(ac) = EXTEND32 (temp); + DSPHI(ac) = EXTEND32 (VH4_8 (temp)); + if (ac == 0) + TRACE_ALU_RESULT2 (HI, LO); +} + +:function:::void:do_maddu:int rs, int rt +{ + uint64_t temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); + ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); +} + +:function:::void:do_dsp_maddu:int ac, int rs, int rt +{ + uint64_t temp; + if (ac == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) + + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); + if (ac == 0) + ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ + DSPLO(ac) = EXTEND32 (temp); + DSPHI(ac) = EXTEND32 (VH4_8 (temp)); + if (ac == 0) + TRACE_ALU_RESULT2 (HI, LO); +} + +:function:::void:do_dsp_mfhi:int ac, int rd +{ + if (ac == 0) + do_mfhi (SD_, rd); + else + GPR[rd] = DSPHI(ac); +} + +:function:::void:do_dsp_mflo:int ac, int rd +{ + if (ac == 0) + do_mflo (SD_, rd); + else + GPR[rd] = DSPLO(ac); +} + +:function:::void:do_movn:int rd, int rs, int rt +{ + if (GPR[rt] != 0) + { + GPR[rd] = GPR[rs]; + TRACE_ALU_RESULT (GPR[rd]); + } +} + +:function:::void:do_movz:int rd, int rs, int rt +{ + if (GPR[rt] == 0) + { + GPR[rd] = GPR[rs]; + TRACE_ALU_RESULT (GPR[rd]); + } +} + +:function:::void:do_msub:int rs, int rt +{ + int64_t temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); +} + +:function:::void:do_dsp_msub:int ac, int rs, int rt +{ + int64_t temp; + if (ac == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) + - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); + DSPLO(ac) = EXTEND32 (temp); + DSPHI(ac) = EXTEND32 (VH4_8 (temp)); + if (ac == 0) + TRACE_ALU_RESULT2 (HI, LO); +} + +:function:::void:do_msubu:int rs, int rt +{ + uint64_t temp; + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) + - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); + LO = EXTEND32 (temp); + HI = EXTEND32 (VH4_8 (temp)); + TRACE_ALU_RESULT2 (HI, LO); +} + +:function:::void:do_dsp_msubu:int ac, int rs, int rt +{ + uint64_t temp; + if (ac == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) + - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); + DSPLO(ac) = EXTEND32 (temp); + DSPHI(ac) = EXTEND32 (VH4_8 (temp)); + if (ac == 0) + TRACE_ALU_RESULT2 (HI, LO); +} + +:function:::void:do_mthi:int rs +{ + check_mt_hilo (SD_, HIHISTORY); + HI = GPR[rs]; +} + +:function:::void:do_dsp_mthi:int ac, int rs +{ + if (ac == 0) + check_mt_hilo (SD_, HIHISTORY); + DSPHI(ac) = GPR[rs]; +} + +:function:::void:do_mtlo:int rs +{ + check_mt_hilo (SD_, LOHISTORY); + LO = GPR[rs]; +} + +:function:::void:do_dsp_mtlo:int ac, int rs +{ + if (ac == 0) + check_mt_hilo (SD_, LOHISTORY); + DSPLO(ac) = GPR[rs]; +} + +:function:::void:do_mul:int rd, int rs, int rt +{ + int64_t prod; + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + prod = (((int64_t)(int32_t) GPR[rs]) + * ((int64_t)(int32_t) GPR[rt])); + GPR[rd] = EXTEND32 (VL4_8 (prod)); + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_dsp_mult:int ac, int rs, int rt +{ + int64_t prod; + if (ac == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + prod = ((int64_t)(int32_t) GPR[rs]) + * ((int64_t)(int32_t) GPR[rt]); + DSPLO(ac) = EXTEND32 (VL4_8 (prod)); + DSPHI(ac) = EXTEND32 (VH4_8 (prod)); + if (ac == 0) + { + ACX = 0; /* SmartMIPS */ + TRACE_ALU_RESULT2 (HI, LO); + } +} + +:function:::void:do_dsp_multu:int ac, int rs, int rt +{ + uint64_t prod; + if (ac == 0) + check_mult_hilo (SD_, HIHISTORY, LOHISTORY); + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + prod = ((uint64_t)(uint32_t) GPR[rs]) + * ((uint64_t)(uint32_t) GPR[rt]); + DSPLO(ac) = EXTEND32 (VL4_8 (prod)); + DSPHI(ac) = EXTEND32 (VH4_8 (prod)); + if (ac == 0) + TRACE_ALU_RESULT2 (HI, LO); +} + +:function:::void:do_pref:int hint, int insn_offset, int insn_base +{ + address_word base = GPR[insn_base]; + address_word offset = EXTEND16 (insn_offset); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr = vaddr; + /* Prefetch (paddr, vaddr, isDATA, hint); */ + } +} + +:function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0, int store_ll_bit +{ + uint32_t instruction = instruction_0; + address_word base = GPR[basereg]; + address_word offset = EXTEND16 (offsetarg); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr = vaddr; + + if ((vaddr & 3) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, + sim_core_unaligned_signal); + } + else + { + uint64_t memval = 0; + uint64_t memval1 = 0; + uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = + (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); + address_word bigendiancpu = + (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + byte = ((vaddr & mask) ^ bigendiancpu); + memval = ((uint64_t) GPR[rt] << (8 * byte)); + if (LLBIT) + StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, + isREAL); + if (store_ll_bit) + GPR[rt] = LLBIT; + } + } +} + +:function:::void:do_scd:int rt, int roffset, int rbase, int store_ll_bit +{ + address_word base = GPR[rbase]; + address_word offset = EXTEND16 (roffset); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr = vaddr; + + if ((vaddr & 7) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, + sim_core_unaligned_signal); + } + else + { + uint64_t memval = 0; + uint64_t memval1 = 0; + memval = GPR[rt]; + if (LLBIT) + StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr, + isREAL); + if (store_ll_bit) + GPR[rt] = LLBIT; + } + } +} + +:function:::void:do_sub:int rs, int rt, int rd +{ + if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) + Unpredictable (); + TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); + { + ALU32_BEGIN (GPR[rs]); + ALU32_SUB (GPR[rt]); + ALU32_END (GPR[rd]); /* This checks for overflow. */ + } + TRACE_ALU_RESULT (GPR[rd]); +} + +:function:::void:do_sw:int rt, int offset, int base +{ + do_store (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset), GPR[rt]); +} + +:function:::void:do_teq:int rs, int rt, address_word instruction_0 +{ + if ((signed_word) GPR[rs] == (signed_word) GPR[rt]) + SignalException (Trap, instruction_0); +} + +:function:::void:do_teqi:int rs, int immediate, address_word instruction_0 +{ + if ((signed_word) GPR[rs] == (signed_word) EXTEND16 (immediate)) + SignalException (Trap, instruction_0); +} + +:function:::void:do_tge:int rs, int rt, address_word instruction_0 +{ + if ((signed_word) GPR[rs] >= (signed_word) GPR[rt]) + SignalException (Trap, instruction_0); +} + +:function:::void:do_tgei:int rs, int immediate, address_word instruction_0 +{ + if ((signed_word) GPR[rs] >= (signed_word) EXTEND16 (immediate)) + SignalException (Trap, instruction_0); +} + +:function:::void:do_tgeiu:int rs, int immediate, address_word instruction_0 +{ + if ((unsigned_word) GPR[rs] >= (unsigned_word) EXTEND16 (immediate)) + SignalException (Trap, instruction_0); +} + +:function:::void:do_tgeu:int rs ,int rt, address_word instruction_0 +{ + if ((unsigned_word) GPR[rs] >= (unsigned_word) GPR[rt]) + SignalException (Trap, instruction_0); +} + +:function:::void:do_tlt:int rs, int rt, address_word instruction_0 +{ + if ((signed_word) GPR[rs] < (signed_word) GPR[rt]) + SignalException (Trap, instruction_0); +} + +:function:::void:do_tlti:int rs, int immediate, address_word instruction_0 +{ + if ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)) + SignalException (Trap, instruction_0); +} + +:function:::void:do_tltiu:int rs, int immediate, address_word instruction_0 +{ + if ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)) + SignalException (Trap, instruction_0); +} + +:function:::void:do_tltu:int rs, int rt, address_word instruction_0 +{ + if ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]) + SignalException (Trap, instruction_0); +} + +:function:::void:do_tne:int rs, int rt, address_word instruction_0 +{ + if ((signed_word) GPR[rs] != (signed_word) GPR[rt]) + SignalException (Trap, instruction_0); +} + +:function:::void:do_tnei:int rs, int immediate, address_word instruction_0 +{ + if ((signed_word) GPR[rs] != (signed_word) EXTEND16 (immediate)) + SignalException (Trap, instruction_0); +} + +:function:::void:do_abs_fmt:int fmt, int fd, int fs, address_word instruction_0 +{ + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (fd, fmt, AbsoluteValue (ValueFPR (fs, fmt), fmt)); +} + +:function:::void:do_add_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 +{ + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (fd, fmt, Add (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); +} + +:function:::void:do_alnv_ps:int fd, int fs, int ft, int rs, address_word instruction_0 +{ + uint64_t fsx; + uint64_t ftx; + uint64_t fdx; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + fsx = ValueFPR (fs, fmt_ps); + if ((GPR[rs] & 0x3) != 0) + Unpredictable (); + if ((GPR[rs] & 0x4) == 0) + fdx = fsx; + else + { + ftx = ValueFPR (ft, fmt_ps); + if (BigEndianCPU) + fdx = PackPS (PSLower (fsx), PSUpper (ftx)); + else + fdx = PackPS (PSLower (ftx), PSUpper (fsx)); + } + StoreFPR (fd, fmt_ps, fdx); +} + +:function:::void:do_c_cond_fmt:int cond, int fmt, int cc, int fs, int ft, address_word instruction_0 +{ + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + Compare (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt, cond, cc); + TRACE_ALU_RESULT (ValueFCR (31)); +} + +:function:::void:do_ceil_fmt:int type, int fmt, int fd, int fs, address_word instruction_0 +{ + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (fd, type, Convert (FP_RM_TOPINF, ValueFPR (fs, fmt), fmt, + type)); +} + +:function:::void:do_cfc1:int rt, int fs +{ + check_fpu (SD_); + if (fs == 0 || fs == 25 || fs == 26 || fs == 28 || fs == 31) + { + unsigned_word fcr = ValueFCR (fs); + TRACE_ALU_INPUT1 (fcr); + GPR[rt] = fcr; + } + /* else NOP */ + TRACE_ALU_RESULT (GPR[rt]); +} + +:function:::void:do_ctc1:int rt, int fs +{ + check_fpu (SD_); + TRACE_ALU_INPUT1 (GPR[rt]); + if (fs == 25 || fs == 26 || fs == 28 || fs == 31) + StoreFCR (fs, GPR[rt]); + /* else NOP */ +} + +:function:::void:do_cvt_d_fmt:int fmt, int fd, int fs, address_word instruction_0 +{ + check_fpu (SD_); + if ((fmt == fmt_double) | 0) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (fd, fmt_double, Convert (GETRM (), ValueFPR (fs, fmt), fmt, + fmt_double)); +} + +:function:::void:do_cvt_l_fmt:int fmt, int fd, int fs, address_word instruction_0 +{ + check_fpu (SD_); + if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word))) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (fd, fmt_long, Convert (GETRM (), ValueFPR (fs, fmt), fmt, + fmt_long)); +} + +:function:::void:do_cvt_ps_s:int fd, int fs, int ft, address_word instruction_0 +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (fd, fmt_ps, PackPS (ValueFPR (fs, fmt_single), + ValueFPR (ft, fmt_single))); +} + +:function:::void:do_cvt_s_fmt:int fmt, int fd, int fs, address_word instruction_0 +{ + check_fpu (SD_); + if ((fmt == fmt_single) | 0) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (fd, fmt_single, Convert (GETRM (), ValueFPR (fs, fmt), fmt, + fmt_single)); +} + +:function:::void:do_cvt_s_pl:int fd, int fs, address_word instruction_0 +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (fd, fmt_single, PSLower (ValueFPR (fs, fmt_ps))); +} + +:function:::void:do_cvt_s_pu:int fd, int fs, address_word instruction_0 +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (fd, fmt_single, PSUpper (ValueFPR (fs, fmt_ps))); +} + +:function:::void:do_cvt_w_fmt:int fmt, int fd, int fs, address_word instruction_0 +{ + check_fpu (SD_); + if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word))) + SignalException (ReservedInstruction, instruction_0); + StoreFPR (fd, fmt_word, Convert (GETRM (), ValueFPR (fs, fmt), fmt, + fmt_word)); +} + +:function:::void:do_div_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 +{ + check_fpu (SD_); + StoreFPR (fd, fmt, Divide (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); +} + +:function:::void:do_dmfc1b:int rt, int fs +*mipsIV: +*mipsV: +*mips64: +*mips64r2: +*mips64r6: +*vr4100: +*vr5000: +*r3900: +*micromips64: +{ + if (SizeFGR () == 64) + GPR[rt] = FGR[fs]; + else if ((fs & 0x1) == 0) + GPR[rt] = SET64HI (FGR[fs+1]) | FGR[fs]; + else + GPR[rt] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; + TRACE_ALU_RESULT (GPR[rt]); +} + +:function:::void:do_dmtc1b:int rt, int fs +{ + if (SizeFGR () == 64) + StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]); + else if ((fs & 0x1) == 0) + StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]); + else + Unpredictable (); +} + +:function:::void:do_floor_fmt:int type, int fmt, int fd, int fs +{ + check_fpu (SD_); + StoreFPR (fd, type, Convert (FP_RM_TOMINF, ValueFPR (fs, fmt), fmt, + type)); +} + +:function:::void:do_luxc1_32:int fd, int rindex, int rbase +*mips32r2: +*micromips32: +{ + address_word base = GPR[rbase]; + address_word index = GPR[rindex]; + address_word vaddr = base + index; + check_fpu (SD_); + if (SizeFGR () != 64) + Unpredictable (); + /* Arrange for the bottom 3 bits of (base + index) to be 0. */ + if ((vaddr & 0x7) != 0) + index -= (vaddr & 0x7); + COP_LD (1, fd, do_load_double (SD_, base, index)); +} + +:function:::void:do_luxc1_64:int fd, int rindex, int rbase +{ + address_word base = GPR[rbase]; + address_word index = GPR[rindex]; + address_word vaddr = base + index; + if (SizeFGR () != 64) + Unpredictable (); + /* Arrange for the bottom 3 bits of (base + index) to be 0. */ + if ((vaddr & 0x7) != 0) + index -= (vaddr & 0x7); + COP_LD (1, fd, do_load (SD_, AccessLength_DOUBLEWORD, base, index)); + +} + +:function:::void:do_lwc1:int ft, int offset, int base +{ + check_fpu (SD_); + COP_LW (1, ft, do_load (SD_, AccessLength_WORD, GPR[base], + EXTEND16 (offset))); +} + +:function:::void:do_lwxc1:int fd, int index, int base, address_word instruction_0 +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + COP_LW (1, fd, do_load (SD_, AccessLength_WORD, GPR[base], GPR[index])); +} + +:function:::void:do_madd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (fd, fmt, MultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt), + ValueFPR (fr, fmt), fmt)); +} + +:function:::void:do_mfc1b:int rt, int fs +{ + check_fpu (SD_); + GPR[rt] = EXTEND32 (FGR[fs]); + TRACE_ALU_RESULT (GPR[rt]); +} + +:function:::void:do_mov_fmt:int fmt, int fd, int fs, address_word instruction_0 +{ + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (fd, fmt, ValueFPR (fs, fmt)); +} + +:function:::void:do_movtf:int tf, int rd, int rs, int cc +{ + check_fpu (SD_); + if (GETFCC(cc) == tf) + GPR[rd] = GPR[rs]; +} + +:function:::void:do_movtf_fmt:int tf, int fmt, int fd, int fs, int cc +{ + check_fpu (SD_); + if (fmt != fmt_ps) + { + if (GETFCC(cc) == tf) + StoreFPR (fd, fmt, ValueFPR (fs, fmt)); + else + StoreFPR (fd, fmt, ValueFPR (fd, fmt)); /* set fmt */ + } + else + { + uint64_t fdx; + fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd, + fmt_ps)), + PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd, + fmt_ps))); + StoreFPR (fd, fmt_ps, fdx); + } +} + +:function:::void:do_movn_fmt:int fmt, int fd, int fs, int rt +{ + check_fpu (SD_); + if (GPR[rt] != 0) + StoreFPR (fd, fmt, ValueFPR (fs, fmt)); + else + StoreFPR (fd, fmt, ValueFPR (fd, fmt)); +} + +:function:::void:do_movz_fmt:int fmt, int fd, int fs, int rt +{ + check_fpu (SD_); + if (GPR[rt] == 0) + StoreFPR (fd, fmt, ValueFPR (fs, fmt)); + else + StoreFPR (fd, fmt, ValueFPR (fd, fmt)); +} + +:function:::void:do_msub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (fd, fmt, MultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), + ValueFPR (fr, fmt), fmt)); +} + +:function:::void:do_mtc1b:int rt, int fs +{ + check_fpu (SD_); + StoreFPR (fs, fmt_uninterpreted_32, VL4_8 (GPR[rt])); +} + +:function:::void:do_mul_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 +{ + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (fd, fmt, Multiply (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); +} + +:function:::void:do_neg_fmt:int fmt, int fd, int fs, address_word instruction_0 +{ + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (fd, fmt, Negate (ValueFPR (fs, fmt), fmt)); +} + +:function:::void:do_nmadd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 { - signed64 time = sim_events_time (SD); - int ok = (check_mf_cycles (SD_, hi, time, "OP") - && check_mf_cycles (SD_, lo, time, "OP")); - hi->op.timestamp = time; - lo->op.timestamp = time; - hi->op.cia = CIA; - lo->op.cia = CIA; - return ok; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (fd, fmt, NegMultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt), + ValueFPR (fr, fmt), fmt)); } -:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo -*mipsIV: -*mipsV: +:function:::void:do_nmsub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 { - signed64 time = sim_events_time (SD); - int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD) - || (check_mf_cycles (SD_, hi, time, "OP") - && check_mf_cycles (SD_, lo, time, "OP"))); - hi->op.timestamp = time; - lo->op.timestamp = time; - hi->op.cia = CIA; - lo->op.cia = CIA; - return ok; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (fd, fmt, NegMultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), + ValueFPR (fr, fmt), fmt)); } -:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo -*mips32: -*mips32r2: -*mips64: -*mips64r2: -*r3900: +:function:::void:do_pll_ps:int fd, int fs, int ft, address_word instruction_0 { - /* FIXME: could record the fact that a stall occured if we want */ - signed64 time = sim_events_time (SD); - hi->op.timestamp = time; - lo->op.timestamp = time; - hi->op.cia = CIA; - lo->op.cia = CIA; - return 1; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)), + PSLower (ValueFPR (ft, fmt_ps)))); } +:function:::void:do_plu_ps:int fd, int fs, int ft, address_word instruction_0 +{ + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)), + PSUpper (ValueFPR (ft, fmt_ps)))); +} -// check_div_hilo: -// -// Check for restriction (3) above (for ISAs/processors that have it) -// for DIV ops, and record timestamps for restriction (1) above. -// -:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo -*mipsI: -*mipsII: -*mipsIII: -*vr4100: -*vr5000: -*r3900: +:function:::void:do_pul_ps:int fd, int fs, int ft, address_word instruction_0 { - signed64 time = sim_events_time (SD); - int ok = (check_mf_cycles (SD_, hi, time, "OP") - && check_mf_cycles (SD_, lo, time, "OP")); - hi->op.timestamp = time; - lo->op.timestamp = time; - hi->op.cia = CIA; - lo->op.cia = CIA; - return ok; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)), + PSLower (ValueFPR (ft, fmt_ps)))); } -:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo -*mipsIV: -*mipsV: +:function:::void:do_puu_ps:int fd, int fs, int ft, address_word instruction_0 { - signed64 time = sim_events_time (SD); - int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD) - || (check_mf_cycles (SD_, hi, time, "OP") - && check_mf_cycles (SD_, lo, time, "OP"))); - hi->op.timestamp = time; - lo->op.timestamp = time; - hi->op.cia = CIA; - lo->op.cia = CIA; - return ok; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)), + PSUpper (ValueFPR (ft, fmt_ps)))); } -:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo +:function:::void:do_recip_fmt:int fmt, int fd, int fs +{ + check_fpu (SD_); + StoreFPR (fd, fmt, Recip (ValueFPR (fs, fmt), fmt)); +} + +:function:::void:do_round_fmt:int type, int fmt, int fd, int fs +{ + check_fpu (SD_); + StoreFPR (fd, type, Convert (FP_RM_NEAREST, ValueFPR (fs, fmt), fmt, + type)); +} + +:function:::void:do_rsqrt_fmt:int fmt, int fd, int fs +{ + check_fpu (SD_); + StoreFPR (fd, fmt, RSquareRoot (ValueFPR (fs, fmt), fmt)); +} + +:function:::void:do_prefx:int hint, int rindex, int rbase +{ + address_word base = GPR[rbase]; + address_word index = GPR[rindex]; + { + address_word vaddr = loadstore_ea (SD_, base, index); + address_word paddr = vaddr; + /* Prefetch (paddr, vaddr, isDATA, hint); */ + } +} + +:function:::void:do_sdc1:int ft, int offset, int base +*mipsII: *mips32: *mips32r2: -*mips64: -*mips64r2: +*mips32r6: +*micromips32: { - signed64 time = sim_events_time (SD); - hi->op.timestamp = time; - lo->op.timestamp = time; - hi->op.cia = CIA; - lo->op.cia = CIA; - return 1; + check_fpu (SD_); + do_store_double (SD_, GPR[base], EXTEND16 (offset), COP_SD (1, ft)); } +:function:::void:do_suxc1_32:int fs, int rindex, int rbase +*mips32r2: +*micromips32: +{ + address_word base = GPR[rbase]; + address_word index = GPR[rindex]; + address_word vaddr = base + index; + check_fpu (SD_); + if (SizeFGR () != 64) + Unpredictable (); + /* Arrange for the bottom 3 bits of (base + index) to be 0. */ + if ((vaddr & 0x7) != 0) + index -= (vaddr & 0x7); + do_store_double (SD_, base, index, COP_SD (1, fs)); +} -// Helper: -// -// Check that the 64-bit instruction can currently be used, and signal -// a ReservedInstruction exception if not. -// +:function:::void:do_suxc1_64:int fs, int rindex, int rbase +{ + address_word base = GPR[rbase]; + address_word index = GPR[rindex]; + address_word vaddr = base + index; + if (SizeFGR () != 64) + Unpredictable (); + /* Arrange for the bottom 3 bits of (base + index) to be 0. */ + if ((vaddr & 0x7) != 0) + index -= (vaddr & 0x7); + do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, fs)); +} -:function:::void:check_u64:instruction_word insn -*mipsIII: -*mipsIV: -*mipsV: -*vr4100: -*vr5000: -*vr5400: -*vr5500: +:function:::void:do_sqrt_fmt:int fmt, int fd, int fs { - // The check should be similar to mips64 for any with PX/UX bit equivalents. + check_fpu (SD_); + StoreFPR (fd, fmt, (SquareRoot (ValueFPR (fs, fmt), fmt))); } -:function:::void:check_u64:instruction_word insn -*mips16e: -*mips64: -*mips64r2: +:function:::void:do_sub_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 { -#if 0 /* XXX FIXME: enable this only after some additional testing. */ - if (UserMode && (SR & (status_UX|status_PX)) == 0) - SignalException (ReservedInstruction, insn); -#endif + check_fpu (SD_); + check_fmt_p (SD_, fmt, instruction_0); + StoreFPR (fd, fmt, Sub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); } +:function:::void:do_swc1:int ft, int roffset, int rbase, address_word instruction_0 +{ + address_word base = GPR[rbase]; + address_word offset = EXTEND16 (roffset); + check_fpu (SD_); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr = vaddr; + if ((vaddr & 3) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, + write_transfer, sim_core_unaligned_signal); + } + else + { + uword64 memval = 0; + uword64 memval1 = 0; + uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = + (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); + address_word bigendiancpu = + (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + byte = ((vaddr & mask) ^ bigendiancpu); + memval = (((uword64)COP_SW(1, ft)) << (8 * byte)); + StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL); + } + } +} -// -// MIPS Architecture: -// -// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2) -// +:function:::void:do_swxc1:int fs, int rindex, int rbase, address_word instruction_0 +{ + address_word base = GPR[rbase]; + address_word index = GPR[rindex]; + check_fpu (SD_); + check_u64 (SD_, instruction_0); + { + address_word vaddr = loadstore_ea (SD_, base, index); + address_word paddr = vaddr; + if ((vaddr & 3) != 0) + { + SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, + sim_core_unaligned_signal); + } + else + { + uint64_t memval = 0; + uint64_t memval1 = 0; + uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); + address_word reverseendian = + (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); + address_word bigendiancpu = + (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); + unsigned int byte; + paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); + byte = ((vaddr & mask) ^ bigendiancpu); + memval = (((uint64_t)COP_SW(1,fs)) << (8 * byte)); + StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, + isREAL); + } + } +} +:function:::void:do_trunc_fmt:int type, int fmt, int fd, int fs +{ + check_fpu (SD_); + StoreFPR (fd, type, Convert (FP_RM_TOZERO, ValueFPR (fs, fmt), fmt, + type)); +} 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD "add r, r, r" @@ -521,21 +1828,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) - Unpredictable (); - TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); - { - ALU32_BEGIN (GPR[RS]); - ALU32_ADD (GPR[RT]); - ALU32_END (GPR[RD]); /* This checks for overflow. */ - } - TRACE_ALU_RESULT (GPR[RD]); + do_add (SD_, RS, RT, RD); } @@ -555,20 +1856,12 @@ *vr5000: *r3900: { - if (NotWordValue (GPR[RS])) - Unpredictable (); - TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); - { - ALU32_BEGIN (GPR[RS]); - ALU32_ADD (EXTEND16 (IMMEDIATE)); - ALU32_END (GPR[RT]); /* This checks for overflow. */ - } - TRACE_ALU_RESULT (GPR[RT]); + do_addi (SD_, RS, RT, IMMEDIATE); } -:function:::void:do_addiu:int rs, int rt, unsigned16 immediate +:function:::void:do_addiu:int rs, int rt, uint16_t immediate { if (NotWordValue (GPR[rs])) Unpredictable (); @@ -586,8 +1879,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -615,8 +1910,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -642,8 +1939,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -662,15 +1961,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE); - GPR[RT] = GPR[RS] & IMMEDIATE; - TRACE_ALU_RESULT (GPR[RT]); + do_andi (SD_,RS, RT, IMMEDIATE); } @@ -698,6 +1997,17 @@ } +000100,5.RS,5.RT,16.OFFSET:R6:32::BEQ +"beq r, r, " +*mips32r6: +*mips64r6: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + if (GPR[RS] == GPR[RT]) + DELAY_SLOT (NIA + offset); + else + FORBIDDEN_SLOT (); +} 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL "beql r, r, " @@ -733,8 +2043,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -773,7 +2085,15 @@ } } - +000001,00000,10001,16.OFFSET:REGIMM:32::BAL +"bal " +*mips32r6: +*mips64r6: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + RA = (CIA + 8); + DELAY_SLOT (NIA + offset); +} 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL "bgezall r, " @@ -839,8 +2159,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -890,8 +2212,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -941,8 +2265,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -985,6 +2311,18 @@ +000001,00000,10000,16.OFFSET:REGIMM:32::NAL +"nal " +*mips32r6: +*mips64r6: +{ + address_word offset = EXTEND16 (OFFSET) << 2; + RA = (CIA + 8); + FORBIDDEN_SLOT (); +} + + + 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL "bltzall r, " *mipsII: @@ -1049,8 +2387,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1087,47 +2427,26 @@ NULLIFY_NEXT_INSTRUCTION (); } - - -000000,20.CODE,001101:SPECIAL:32::BREAK -"break %#lx" -*mipsI: -*mipsII: -*mipsIII: -*mipsIV: -*mipsV: -*mips32: -*mips32r2: -*mips64: -*mips64r2: -*vr4100: -*vr5000: -*r3900: -{ - /* Check for some break instruction which are reserved for use by the simulator. */ - unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK; - if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) || - break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) - { - sim_engine_halt (SD, CPU, NULL, cia, - sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); - } - else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) || - break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) - { - if (STATE & simDELAYSLOT) - PC = cia - 4; /* reference the branch instruction */ - else - PC = cia; - SignalException (BreakPoint, instruction_0); - } - - else - { - /* If we get this far, we're not an instruction reserved by the sim. Raise - the exception. */ - SignalException (BreakPoint, instruction_0); - } + + +000000,20.CODE,001101:SPECIAL:32::BREAK +"break %#lx" +*mipsI: +*mipsII: +*mipsIII: +*mipsIV: +*mipsV: +*mips32: +*mips32r2: +*mips32r6: +*mips64: +*mips64r2: +*mips64r6: +*vr4100: +*vr5000: +*r3900: +{ + do_break (SD_, instruction_0); } @@ -1140,21 +2459,9 @@ *mips64r2: *vr5500: { - unsigned32 temp = GPR[RS]; - unsigned32 i, mask; if (RT != RD) Unpredictable (); - if (NotWordValue (GPR[RS])) - Unpredictable (); - TRACE_ALU_INPUT1 (GPR[RS]); - for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) - { - if ((temp & mask) == 0) - break; - mask >>= 1; - } - GPR[RD] = EXTEND32 (i); - TRACE_ALU_RESULT (GPR[RD]); + do_clo (SD_, RD, RS); } @@ -1167,21 +2474,9 @@ *mips64r2: *vr5500: { - unsigned32 temp = GPR[RS]; - unsigned32 i, mask; if (RT != RD) Unpredictable (); - if (NotWordValue (GPR[RS])) - Unpredictable (); - TRACE_ALU_INPUT1 (GPR[RS]); - for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i) - { - if ((temp & mask) != 0) - break; - mask >>= 1; - } - GPR[RD] = EXTEND32 (i); - TRACE_ALU_RESULT (GPR[RD]); + do_clz (SD_, RD, RS); } @@ -1193,17 +2488,12 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { check_u64 (SD_, instruction_0); - TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); - { - ALU64_BEGIN (GPR[RS]); - ALU64_ADD (GPR[RT]); - ALU64_END (GPR[RD]); /* This checks for overflow. */ - } - TRACE_ALU_RESULT (GPR[RD]); + do_dadd (SD_, RD, RS, RT); } @@ -1219,18 +2509,12 @@ *vr5000: { check_u64 (SD_, instruction_0); - TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); - { - ALU64_BEGIN (GPR[RS]); - ALU64_ADD (EXTEND16 (IMMEDIATE)); - ALU64_END (GPR[RT]); /* This checks for overflow. */ - } - TRACE_ALU_RESULT (GPR[RT]); + do_daddi (SD_, RT, RS, IMMEDIATE); } -:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate +:function:::void:do_daddiu:int rs, int rt, uint16_t immediate { TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); GPR[rt] = GPR[rs] + EXTEND16 (immediate); @@ -1244,6 +2528,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -1267,6 +2552,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -1282,21 +2568,12 @@ *mips64r2: *vr5500: { - unsigned64 temp = GPR[RS]; - unsigned32 i; - unsigned64 mask; + if (RT != RD) + Unpredictable (); check_u64 (SD_, instruction_0); if (RT != RD) Unpredictable (); - TRACE_ALU_INPUT1 (GPR[RS]); - for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) - { - if ((temp & mask) == 0) - break; - mask >>= 1; - } - GPR[RD] = EXTEND32 (i); - TRACE_ALU_RESULT (GPR[RD]); + do_dclo (SD_, RD, RS); } @@ -1307,21 +2584,12 @@ *mips64r2: *vr5500: { - unsigned64 temp = GPR[RS]; - unsigned32 i; - unsigned64 mask; + if (RT != RD) + Unpredictable (); check_u64 (SD_, instruction_0); if (RT != RD) Unpredictable (); - TRACE_ALU_INPUT1 (GPR[RS]); - for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i) - { - if ((temp & mask) != 0) - break; - mask >>= 1; - } - GPR[RD] = EXTEND32 (i); - TRACE_ALU_RESULT (GPR[RD]); + do_dclz (SD_, RD, RS); } @@ -1331,10 +2599,10 @@ check_div_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); { - signed64 n = GPR[rs]; - signed64 d = GPR[rt]; - signed64 hi; - signed64 lo; + int64_t n = GPR[rs]; + int64_t d = GPR[rt]; + int64_t hi; + int64_t lo; if (d == 0) { lo = SIGNED64 (0x8000000000000000); @@ -1377,10 +2645,10 @@ check_div_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); { - unsigned64 n = GPR[rs]; - unsigned64 d = GPR[rt]; - unsigned64 hi; - unsigned64 lo; + uint64_t n = GPR[rs]; + uint64_t d = GPR[rt]; + uint64_t hi; + uint64_t lo; if (d == 0) { lo = SIGNED64 (0x8000000000000000); @@ -1416,8 +2684,8 @@ check_div_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); { - signed32 n = GPR[rs]; - signed32 d = GPR[rt]; + int32_t n = GPR[rs]; + int32_t d = GPR[rt]; if (d == 0) { LO = EXTEND32 (0x80000000); @@ -1462,8 +2730,8 @@ check_div_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); { - unsigned32 n = GPR[rs]; - unsigned32 d = GPR[rt]; + uint32_t n = GPR[rs]; + uint32_t d = GPR[rt]; if (d == 0) { LO = EXTEND32 (0x80000000); @@ -1499,47 +2767,47 @@ :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p { - unsigned64 lo; - unsigned64 hi; - unsigned64 m00; - unsigned64 m01; - unsigned64 m10; - unsigned64 m11; - unsigned64 mid; + uint64_t lo; + uint64_t hi; + uint64_t m00; + uint64_t m01; + uint64_t m10; + uint64_t m11; + uint64_t mid; int sign; - unsigned64 op1 = GPR[rs]; - unsigned64 op2 = GPR[rt]; + uint64_t op1 = GPR[rs]; + uint64_t op2 = GPR[rt]; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); /* make signed multiply unsigned */ sign = 0; if (signed_p) { - if ((signed64) op1 < 0) + if ((int64_t) op1 < 0) { op1 = - op1; ++sign; } - if ((signed64) op2 < 0) + if ((int64_t) op2 < 0) { op2 = - op2; ++sign; } } /* multiply out the 4 sub products */ - m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2)); - m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2)); - m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2)); - m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2)); + m00 = ((uint64_t) VL4_8 (op1) * (uint64_t) VL4_8 (op2)); + m10 = ((uint64_t) VH4_8 (op1) * (uint64_t) VL4_8 (op2)); + m01 = ((uint64_t) VL4_8 (op1) * (uint64_t) VH4_8 (op2)); + m11 = ((uint64_t) VH4_8 (op1) * (uint64_t) VH4_8 (op2)); /* add the products */ - mid = ((unsigned64) VH4_8 (m00) - + (unsigned64) VL4_8 (m10) - + (unsigned64) VL4_8 (m01)); + mid = ((uint64_t) VH4_8 (m00) + + (uint64_t) VL4_8 (m10) + + (uint64_t) VL4_8 (m01)); lo = U8_4 (mid, m00); hi = (m11 - + (unsigned64) VH4_8 (mid) - + (unsigned64) VH4_8 (m01) - + (unsigned64) VH4_8 (m10)); + + (uint64_t) VH4_8 (mid) + + (uint64_t) VH4_8 (m01) + + (uint64_t) VH4_8 (m10)); /* fix the sign */ if (sign & 1) { @@ -1614,9 +2882,9 @@ } -:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y +:function:::uint64_t:do_dror:uint64_t x,uint64_t y { - unsigned64 result; + uint64_t result; y &= 63; TRACE_ALU_INPUT2 (x, y); @@ -1628,6 +2896,7 @@ 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR "dror r, r, " *mips64r2: +*mips64r6: *vr5400: *vr5500: { @@ -1638,6 +2907,7 @@ 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 "dror32 r, r, " *mips64r2: +*mips64r6: *vr5400: *vr5500: { @@ -1648,6 +2918,7 @@ 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV "drorv r, r, r" *mips64r2: +*mips64r6: *vr5400: *vr5500: { @@ -1670,6 +2941,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -1685,14 +2957,12 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { - int s = 32 + SHIFT; check_u64 (SD_, instruction_0); - TRACE_ALU_INPUT2 (GPR[RT], s); - GPR[RD] = GPR[RT] << s; - TRACE_ALU_RESULT (GPR[RD]); + do_dsll32 (SD_, RD, RT, SHIFT); } :function:::void:do_dsllv:int rs, int rt, int rd @@ -1710,6 +2980,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -1720,7 +2991,7 @@ :function:::void:do_dsra:int rt, int rd, int shift { TRACE_ALU_INPUT2 (GPR[rt], shift); - GPR[rd] = ((signed64) GPR[rt]) >> shift; + GPR[rd] = ((int64_t) GPR[rt]) >> shift; TRACE_ALU_RESULT (GPR[rd]); } @@ -1732,6 +3003,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -1747,14 +3019,12 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { - int s = 32 + SHIFT; check_u64 (SD_, instruction_0); - TRACE_ALU_INPUT2 (GPR[RT], s); - GPR[RD] = ((signed64) GPR[RT]) >> s; - TRACE_ALU_RESULT (GPR[RD]); + do_dsra32 (SD_, RD, RT, SHIFT); } @@ -1762,7 +3032,7 @@ { int s = MASKED64 (GPR[rs], 5, 0); TRACE_ALU_INPUT2 (GPR[rt], s); - GPR[rd] = ((signed64) GPR[rt]) >> s; + GPR[rd] = ((int64_t) GPR[rt]) >> s; TRACE_ALU_RESULT (GPR[rd]); } @@ -1773,6 +3043,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -1783,7 +3054,7 @@ :function:::void:do_dsrl:int rt, int rd, int shift { TRACE_ALU_INPUT2 (GPR[rt], shift); - GPR[rd] = (unsigned64) GPR[rt] >> shift; + GPR[rd] = (uint64_t) GPR[rt] >> shift; TRACE_ALU_RESULT (GPR[rd]); } @@ -1795,6 +3066,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -1810,14 +3082,12 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { - int s = 32 + SHIFT; check_u64 (SD_, instruction_0); - TRACE_ALU_INPUT2 (GPR[RT], s); - GPR[RD] = (unsigned64) GPR[RT] >> s; - TRACE_ALU_RESULT (GPR[RD]); + do_dsrl32 (SD_, RD, RT, SHIFT); } @@ -1825,7 +3095,7 @@ { int s = MASKED64 (GPR[rs], 5, 0); TRACE_ALU_INPUT2 (GPR[rt], s); - GPR[rd] = (unsigned64) GPR[rt] >> s; + GPR[rd] = (uint64_t) GPR[rt] >> s; TRACE_ALU_RESULT (GPR[rd]); } @@ -1838,6 +3108,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -1853,17 +3124,12 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { check_u64 (SD_, instruction_0); - TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); - { - ALU64_BEGIN (GPR[RS]); - ALU64_SUB (GPR[RT]); - ALU64_END (GPR[RD]); /* This checks for overflow. */ - } - TRACE_ALU_RESULT (GPR[RD]); + do_dsub (SD_, RD, RS, RT); } @@ -1881,6 +3147,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -1898,8 +3165,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1920,8 +3189,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1943,8 +3214,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1954,8 +3227,20 @@ DELAY_SLOT (temp); } +000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB +"jalr.hb r":RD == 31 +"jalr.hb r, r" +*mips32r2: +*mips32r6: +*mips64r2: +*mips64r6: +{ + address_word temp = GPR[RS]; + GPR[RD] = CIA + 8; + DELAY_SLOT (temp); +} -000000,5.RS,000000000000000,001000:SPECIAL:32::JR +000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR "jr r" *mipsI: *mipsII: @@ -1964,8 +3249,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -1973,6 +3260,15 @@ DELAY_SLOT (GPR[RS]); } +000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB +"jr.hb r" +*mips32r2: +*mips32r6: +*mips64r2: +*mips64r6: +{ + DELAY_SLOT (GPR[RS]); +} :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset { @@ -1981,18 +3277,16 @@ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); unsigned int byte; address_word paddr; - int uncached; - unsigned64 memval; + uint64_t memval; address_word vaddr; - vaddr = loadstore_ea (SD_, base, offset); + paddr = vaddr = loadstore_ea (SD_, base, offset); if ((vaddr & access) != 0) { SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal); } - AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); - LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL); + LoadMemory (&memval, NULL, access, paddr, vaddr, isDATA, isREAL); byte = ((vaddr & mask) ^ bigendiancpu); return (memval >> (8 * byte)); } @@ -2005,16 +3299,14 @@ unsigned int byte; unsigned int word; address_word paddr; - int uncached; - unsigned64 memval; + uint64_t memval; address_word vaddr; int nr_lhs_bits; int nr_rhs_bits; unsigned_word lhs_mask; unsigned_word temp; - vaddr = loadstore_ea (SD_, base, offset); - AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); + paddr = vaddr = loadstore_ea (SD_, base, offset); paddr = (paddr ^ (reverseendian & mask)); if (BigEndianMem == 0) paddr = paddr & ~access; @@ -2027,11 +3319,11 @@ /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", - (long) ((unsigned64) vaddr >> 32), (long) vaddr, - (long) ((unsigned64) paddr >> 32), (long) paddr, + (long) ((uint64_t) vaddr >> 32), (long) vaddr, + (long) ((uint64_t) paddr >> 32), (long) paddr, word, byte, nr_lhs_bits, nr_rhs_bits); */ - LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL); + LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL); if (word == 0) { /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */ @@ -2046,9 +3338,9 @@ rt = (rt & ~lhs_mask) | (temp & lhs_mask); /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n", - (long) ((unsigned64) memval >> 32), (long) memval, - (long) ((unsigned64) temp >> 32), (long) temp, - (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask, + (long) ((uint64_t) memval >> 32), (long) memval, + (long) ((uint64_t) temp >> 32), (long) temp, + (long) ((uint64_t) lhs_mask >> 32), (long) lhs_mask, (long) (rt >> 32), (long) rt); */ return rt; } @@ -2060,19 +3352,17 @@ address_word bigendiancpu = (BigEndianCPU ? -1 : 0); unsigned int byte; address_word paddr; - int uncached; - unsigned64 memval; + uint64_t memval; address_word vaddr; - vaddr = loadstore_ea (SD_, base, offset); - AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL); + paddr = vaddr = loadstore_ea (SD_, base, offset); /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */ paddr = (paddr ^ (reverseendian & mask)); if (BigEndianMem != 0) paddr = paddr & ~access; byte = ((vaddr & mask) ^ (bigendiancpu & mask)); /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */ - LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL); + LoadMemory (&memval, NULL, access - (access & byte), paddr, vaddr, isDATA, isREAL); /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n", (long) paddr, byte, (long) paddr, (long) memval); */ { @@ -2093,13 +3383,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET))); + do_lb (SD_,RT,OFFSET,BASE); } @@ -2112,13 +3404,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)); + do_lbu (SD_, RT,OFFSET,BASE); } @@ -2129,6 +3423,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -2151,7 +3446,7 @@ *vr5000: *r3900: { - COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); + do_ldc (SD_, ZZ, RT, OFFSET, BASE); } @@ -2196,13 +3491,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET))); + do_lh (SD_,RT,OFFSET,BASE); } @@ -2215,13 +3512,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)); + do_lhu (SD_,RT,OFFSET,BASE); } @@ -2238,35 +3537,7 @@ *vr4100: *vr5000: { - address_word base = GPR[BASE]; - address_word offset = EXTEND16 (OFFSET); - { - address_word vaddr = loadstore_ea (SD_, base, offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - { - SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal); - } - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int shift = 2; - unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); - unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); - LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL); - byte = ((vaddr & mask) ^ (bigend << shift)); - GPR[RT] = EXTEND32 (memval >> (8 * byte)); - LLBIT = 1; - } - } - } + do_ll (SD_, RT, OFFSET, BASE); } @@ -2280,29 +3551,8 @@ *vr4100: *vr5000: { - address_word base = GPR[BASE]; - address_word offset = EXTEND16 (OFFSET); check_u64 (SD_, instruction_0); - { - address_word vaddr = loadstore_ea (SD_, base, offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - { - SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal); - } - else - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL); - GPR[RT] = memval; - LLBIT = 1; - } - } - } + do_lld (SD_, RT, OFFSET, BASE); } @@ -2315,15 +3565,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - TRACE_ALU_INPUT1 (IMMEDIATE); - GPR[RT] = EXTEND32 (IMMEDIATE << 16); - TRACE_ALU_RESULT (GPR[RT]); + do_lui (SD_, RT, IMMEDIATE); } @@ -2336,13 +3586,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); + do_lw (SD_,RT,OFFSET,BASE); } @@ -2361,7 +3613,7 @@ *vr5000: *r3900: { - COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); + do_lwc (SD_, ZZ, RT, OFFSET, BASE); } @@ -2380,7 +3632,7 @@ *vr5000: *r3900: { - GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); + do_lwl (SD_, RT, OFFSET, BASE); } @@ -2399,7 +3651,7 @@ *vr5000: *r3900: { - GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); + do_lwr (SD_, RT, OFFSET, BASE); } @@ -2410,11 +3662,11 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { - check_u64 (SD_, instruction_0); - GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)); + do_lwu (SD_, RT, OFFSET, BASE, instruction_0); } @@ -2422,43 +3674,42 @@ 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD "madd r, r" *mips32: -*mips32r2: *mips64: -*mips64r2: *vr5500: { - signed64 temp; - check_mult_hilo (SD_, HIHISTORY, LOHISTORY); - if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) - Unpredictable (); - TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); - temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) - + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); - LO = EXTEND32 (temp); - HI = EXTEND32 (VH4_8 (temp)); - TRACE_ALU_RESULT2 (HI, LO); + do_madd (SD_, RS, RT); } +011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD +"madd r, r":AC == 0 +"madd ac, r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + do_dsp_madd (SD_, AC, RS, RT); +} + 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU "maddu r, r" *mips32: -*mips32r2: *mips64: -*mips64r2: *vr5500: { - unsigned64 temp; - check_mult_hilo (SD_, HIHISTORY, LOHISTORY); - if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) - Unpredictable (); - TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); - temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) - + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); - LO = EXTEND32 (temp); - HI = EXTEND32 (VH4_8 (temp)); - TRACE_ALU_RESULT2 (HI, LO); + do_maddu (SD_, RS, RT); +} + + +011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU +"maddu r, r":AC == 0 +"maddu ac, r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + do_dsp_maddu (SD_, AC, RS, RT); } @@ -2477,18 +3728,26 @@ *mipsIII: *mipsIV: *mipsV: -*mips32: -*mips32r2: -*mips64: -*mips64r2: *vr4100: *vr5000: *r3900: +*mips32: +*mips64: { do_mfhi (SD_, RD); } +000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI +"mfhi r":AC == 0 +"mfhi r, ac" +*mips32r2: +*mips64r2: +*dsp: +{ + do_dsp_mfhi (SD_, AC, RD); +} + :function:::void:do_mflo:int rd { @@ -2505,18 +3764,26 @@ *mipsIII: *mipsIV: *mipsV: -*mips32: -*mips32r2: -*mips64: -*mips64r2: *vr4100: *vr5000: *r3900: +*mips32: +*mips64: { do_mflo (SD_, RD); } +000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO +"mflo r":AC == 0 +"mflo r, ac" +*mips32r2: +*mips64r2: +*dsp: +{ + do_dsp_mflo (SD_, AC, RD); +} + 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN "movn r, r, r" @@ -2528,11 +3795,7 @@ *mips64r2: *vr5000: { - if (GPR[RT] != 0) - { - GPR[RD] = GPR[RS]; - TRACE_ALU_RESULT (GPR[RD]); - } + do_movn (SD_, RD, RS, RT); } @@ -2547,11 +3810,7 @@ *mips64r2: *vr5000: { - if (GPR[RT] == 0) - { - GPR[RD] = GPR[RS]; - TRACE_ALU_RESULT (GPR[RD]); - } + do_movz (SD_, RD, RS, RT); } @@ -2559,46 +3818,44 @@ 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB "msub r, r" *mips32: -*mips32r2: *mips64: -*mips64r2: *vr5500: { - signed64 temp; - check_mult_hilo (SD_, HIHISTORY, LOHISTORY); - if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) - Unpredictable (); - TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); - temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) - - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS]))); - LO = EXTEND32 (temp); - HI = EXTEND32 (VH4_8 (temp)); - TRACE_ALU_RESULT2 (HI, LO); + do_msub (SD_, RS, RT); } +011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB +"msub r, r":AC == 0 +"msub ac, r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + do_dsp_msub (SD_, AC, RS, RT); +} + 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU "msubu r, r" *mips32: -*mips32r2: *mips64: -*mips64r2: *vr5500: { - unsigned64 temp; - check_mult_hilo (SD_, HIHISTORY, LOHISTORY); - if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) - Unpredictable (); - TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); - temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) - - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT]))); - LO = EXTEND32 (temp); - HI = EXTEND32 (VH4_8 (temp)); - TRACE_ALU_RESULT2 (HI, LO); + do_msubu (SD_, RS, RT); } +011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU +"msubu r, r":AC == 0 +"msubu ac, r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + do_dsp_msubu (SD_, AC, RS, RT); +} + 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI "mthi r" @@ -2607,19 +3864,26 @@ *mipsIII: *mipsIV: *mipsV: -*mips32: -*mips32r2: -*mips64: -*mips64r2: *vr4100: *vr5000: *r3900: +*mips32: +*mips64: { - check_mt_hilo (SD_, HIHISTORY); - HI = GPR[RS]; + do_mthi (SD_, RS); } +000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI +"mthi r":AC == 0 +"mthi r, ac" +*mips32r2: +*mips64r2: +*dsp: +{ + do_dsp_mthi (SD_, AC, RS); +} + 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO "mtlo r" @@ -2628,19 +3892,26 @@ *mipsIII: *mipsIV: *mipsV: -*mips32: -*mips32r2: -*mips64: -*mips64r2: *vr4100: *vr5000: *r3900: +*mips32: +*mips64: { - check_mt_hilo (SD_, LOHISTORY); - LO = GPR[RS]; + do_mtlo (SD_, RS); } +000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO +"mtlo r":AC == 0 +"mtlo r, ac" +*mips32r2: +*mips64r2: +*dsp: +{ + do_dsp_mtlo (SD_, AC, RS); +} + 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL "mul r, r, r" @@ -2650,29 +3921,23 @@ *mips64r2: *vr5500: { - signed64 prod; - if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) - Unpredictable (); - TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); - prod = (((signed64)(signed32) GPR[RS]) - * ((signed64)(signed32) GPR[RT])); - GPR[RD] = EXTEND32 (VL4_8 (prod)); - TRACE_ALU_RESULT (GPR[RD]); + do_mul (SD_, RD, RS, RT); } :function:::void:do_mult:int rs, int rt, int rd { - signed64 prod; + int64_t prod; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); - prod = (((signed64)(signed32) GPR[rs]) - * ((signed64)(signed32) GPR[rt])); + prod = (((int64_t)(int32_t) GPR[rs]) + * ((int64_t)(int32_t) GPR[rt])); LO = EXTEND32 (VL4_8 (prod)); HI = EXTEND32 (VH4_8 (prod)); + ACX = 0; /* SmartMIPS */ if (rd != 0) GPR[rd] = LO; TRACE_ALU_RESULT2 (HI, LO); @@ -2686,15 +3951,24 @@ *mipsIV: *mipsV: *mips32: -*mips32r2: *mips64: -*mips64r2: *vr4100: { do_mult (SD_, RS, RT, 0); } +000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT +"mult r, r":AC == 0 +"mult ac, r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + do_dsp_mult (SD_, AC, RS, RT); +} + + 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT "mult r, r":RD == 0 "mult r, r, r" @@ -2707,13 +3981,13 @@ :function:::void:do_multu:int rs, int rt, int rd { - unsigned64 prod; + uint64_t prod; check_mult_hilo (SD_, HIHISTORY, LOHISTORY); if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); - prod = (((unsigned64)(unsigned32) GPR[rs]) - * ((unsigned64)(unsigned32) GPR[rt])); + prod = (((uint64_t)(uint32_t) GPR[rs]) + * ((uint64_t)(uint32_t) GPR[rt])); LO = EXTEND32 (VL4_8 (prod)); HI = EXTEND32 (VH4_8 (prod)); if (rd != 0) @@ -2729,14 +4003,24 @@ *mipsIV: *mipsV: *mips32: -*mips32r2: *mips64: -*mips64r2: *vr4100: { do_multu (SD_, RS, RT, 0); } + +000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU +"multu r, r":AC == 0 +"multu r, r" +*mips32r2: +*mips64r2: +*dsp2: +{ + do_dsp_multu (SD_, AC, RS, RT); +} + + 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU "multu r, r":RD == 0 "multu r, r, r" @@ -2763,8 +4047,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -2789,8 +4075,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -2816,8 +4104,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -2836,23 +4126,13 @@ *mips64r2: *vr5000: { - address_word base = GPR[BASE]; - address_word offset = EXTEND16 (OFFSET); - { - address_word vaddr = loadstore_ea (SD_, base, offset); - address_word paddr; - int uncached; - { - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - Prefetch(uncached,paddr,vaddr,isDATA,HINT); - } - } + do_pref (SD_, HINT, OFFSET, BASE); } -:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y +:function:::uint64_t:do_ror:uint32_t x,uint32_t y { - unsigned64 result; + uint64_t result; y &= 31; TRACE_ALU_INPUT2 (x, y); @@ -2864,7 +4144,10 @@ 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR "ror r, r, " *mips32r2: +*mips32r6: *mips64r2: +*mips64r6: +*smartmips: *vr5400: *vr5500: { @@ -2874,7 +4157,10 @@ 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV "rorv r, r, r" *mips32r2: +*mips32r6: *mips64r2: +*mips64r6: +*smartmips: *vr5400: *vr5500: { @@ -2889,20 +4175,18 @@ address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); unsigned int byte; address_word paddr; - int uncached; - unsigned64 memval; + uint64_t memval; address_word vaddr; - vaddr = loadstore_ea (SD_, base, offset); + paddr = vaddr = loadstore_ea (SD_, base, offset); if ((vaddr & access) != 0) { SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal); } - AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); byte = ((vaddr & mask) ^ bigendiancpu); memval = (word << (8 * byte)); - StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL); + StoreMemory (access, memval, 0, paddr, vaddr, isREAL); } :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt @@ -2913,14 +4197,12 @@ unsigned int byte; unsigned int word; address_word paddr; - int uncached; - unsigned64 memval; + uint64_t memval; address_word vaddr; int nr_lhs_bits; int nr_rhs_bits; - vaddr = loadstore_ea (SD_, base, offset); - AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); + paddr = vaddr = loadstore_ea (SD_, base, offset); paddr = (paddr ^ (reverseendian & mask)); if (BigEndianMem == 0) paddr = paddr & ~access; @@ -2932,8 +4214,8 @@ nr_rhs_bits = 8 * access - 8 * byte; /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", - (long) ((unsigned64) vaddr >> 32), (long) vaddr, - (long) ((unsigned64) paddr >> 32), (long) paddr, + (long) ((uint64_t) vaddr >> 32), (long) vaddr, + (long) ((uint64_t) paddr >> 32), (long) paddr, word, byte, nr_lhs_bits, nr_rhs_bits); */ if (word == 0) @@ -2945,9 +4227,9 @@ memval = (rt << nr_lhs_bits); } /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n", - (long) ((unsigned64) rt >> 32), (long) rt, - (long) ((unsigned64) memval >> 32), (long) memval); */ - StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL); + (long) ((uint64_t) rt >> 32), (long) rt, + (long) ((uint64_t) memval >> 32), (long) memval); */ + StoreMemory (byte, memval, 0, paddr, vaddr, isREAL); } :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt @@ -2957,18 +4239,16 @@ address_word bigendiancpu = (BigEndianCPU ? -1 : 0); unsigned int byte; address_word paddr; - int uncached; - unsigned64 memval; + uint64_t memval; address_word vaddr; - vaddr = loadstore_ea (SD_, base, offset); - AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL); + paddr = vaddr = loadstore_ea (SD_, base, offset); paddr = (paddr ^ (reverseendian & mask)); if (BigEndianMem != 0) paddr &= ~access; byte = ((vaddr & mask) ^ (bigendiancpu & mask)); memval = (rt << (byte * 8)); - StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL); + StoreMemory (access - (access & byte), memval, 0, paddr, vaddr, isREAL); } @@ -2981,8 +4261,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3004,36 +4286,7 @@ *vr4100: *vr5000: { - unsigned32 instruction = instruction_0; - address_word base = GPR[BASE]; - address_word offset = EXTEND16 (OFFSET); - { - address_word vaddr = loadstore_ea (SD_, base, offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - { - SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); - } - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); - byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); - memval = ((unsigned64) GPR[RT] << (8 * byte)); - if (LLBIT) - { - StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); - } - GPR[RT] = LLBIT; - } - } - } + do_sc (SD_, RT, OFFSET, BASE, instruction_0, 1); } @@ -3047,32 +4300,8 @@ *vr4100: *vr5000: { - address_word base = GPR[BASE]; - address_word offset = EXTEND16 (OFFSET); check_u64 (SD_, instruction_0); - { - address_word vaddr = loadstore_ea (SD_, base, offset); - address_word paddr; - int uncached; - if ((vaddr & 7) != 0) - { - SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal); - } - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - memval = GPR[RT]; - if (LLBIT) - { - StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL); - } - GPR[RT] = LLBIT; - } - } - } + do_scd (SD_, RT, OFFSET, BASE, 1); } @@ -3083,6 +4312,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -3148,8 +4378,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3160,7 +4392,7 @@ :function:::void:do_sll:int rt, int rd, int shift { - unsigned32 temp = (GPR[rt] << shift); + uint32_t temp = (GPR[rt] << shift); TRACE_ALU_INPUT2 (GPR[rt], shift); GPR[rd] = EXTEND32 (temp); TRACE_ALU_RESULT (GPR[rd]); @@ -3187,23 +4419,23 @@ 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb "nop":RD == 0 && RT == 0 && SHIFT == 0 "ssnop":RD == 0 && RT == 0 && SHIFT == 1 +"ehb":RD == 0 && RT == 0 && SHIFT == 3 "sll r, r, " *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: { - /* Skip shift for NOP and SSNOP, so that there won't be lots of - extraneous trace output. */ - if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1)) - do_sll (SD_, RT, RD, SHIFT); + do_sll (SD_, RT, RD, SHIFT); } :function:::void:do_sllv:int rs, int rt, int rd { int s = MASKED (GPR[rs], 4, 0); - unsigned32 temp = (GPR[rt] << s); + uint32_t temp = (GPR[rt] << s); TRACE_ALU_INPUT2 (GPR[rt], s); GPR[rd] = EXTEND32 (temp); TRACE_ALU_RESULT (GPR[rd]); @@ -3218,8 +4450,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3244,8 +4478,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3254,7 +4490,7 @@ } -:function:::void:do_slti:int rs, int rt, unsigned16 immediate +:function:::void:do_slti:int rs, int rt, uint16_t immediate { TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)); @@ -3270,8 +4506,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3280,7 +4518,7 @@ } -:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate +:function:::void:do_sltiu:int rs, int rt, uint16_t immediate { TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)); @@ -3296,8 +4534,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3323,8 +4563,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3335,7 +4577,7 @@ :function:::void:do_sra:int rt, int rd, int shift { - signed32 temp = (signed32) GPR[rt] >> shift; + int32_t temp = (int32_t) GPR[rt] >> shift; if (NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rt], shift); @@ -3352,8 +4594,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3366,7 +4610,7 @@ :function:::void:do_srav:int rs, int rt, int rd { int s = MASKED (GPR[rs], 4, 0); - signed32 temp = (signed32) GPR[rt] >> s; + int32_t temp = (int32_t) GPR[rt] >> s; if (NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rt], s); @@ -3383,8 +4627,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3396,7 +4642,7 @@ :function:::void:do_srl:int rt, int rd, int shift { - unsigned32 temp = (unsigned32) GPR[rt] >> shift; + uint32_t temp = (uint32_t) GPR[rt] >> shift; if (NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rt], shift); @@ -3413,8 +4659,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3426,7 +4674,7 @@ :function:::void:do_srlv:int rs, int rt, int rd { int s = MASKED (GPR[rs], 4, 0); - unsigned32 temp = (unsigned32) GPR[rt] >> s; + uint32_t temp = (uint32_t) GPR[rt] >> s; if (NotWordValue (GPR[rt])) Unpredictable (); TRACE_ALU_INPUT2 (GPR[rt], s); @@ -3443,8 +4691,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3462,21 +4712,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) - Unpredictable (); - TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); - { - ALU32_BEGIN (GPR[RS]); - ALU32_SUB (GPR[RT]); - ALU32_END (GPR[RD]); /* This checks for overflow. */ - } - TRACE_ALU_RESULT (GPR[RD]); + do_sub (SD_, RD, RS, RT); } @@ -3498,8 +4742,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3517,13 +4763,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *r3900: *vr5000: { - do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); + do_sw (SD_, RT, OFFSET, BASE); } @@ -3593,8 +4841,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3612,8 +4862,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3630,13 +4882,14 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { - if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) - SignalException (Trap, instruction_0); + do_teq (SD_, RS, RT, instruction_0); } @@ -3653,8 +4906,7 @@ *vr4100: *vr5000: { - if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE)) - SignalException (Trap, instruction_0); + do_teqi (SD_, RS, IMMEDIATE, instruction_0); } @@ -3666,13 +4918,14 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { - if ((signed_word) GPR[RS] >= (signed_word) GPR[RT]) - SignalException (Trap, instruction_0); + do_tge (SD_, RS, RT, instruction_0); } @@ -3689,8 +4942,7 @@ *vr4100: *vr5000: { - if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE)) - SignalException (Trap, instruction_0); + do_tgei (SD_, RS, IMMEDIATE, instruction_0); } @@ -3707,8 +4959,7 @@ *vr4100: *vr5000: { - if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE)) - SignalException (Trap, instruction_0); + do_tgeiu (SD_, RS, IMMEDIATE, instruction_0); } @@ -3720,13 +4971,14 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { - if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT]) - SignalException (Trap, instruction_0); + do_tgeu (SD_, RS, RT, instruction_0); } @@ -3738,13 +4990,14 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { - if ((signed_word) GPR[RS] < (signed_word) GPR[RT]) - SignalException (Trap, instruction_0); + do_tlt (SD_, RS, RT, instruction_0); } @@ -3761,8 +5014,7 @@ *vr4100: *vr5000: { - if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE)) - SignalException (Trap, instruction_0); + do_tlti (SD_, RS, IMMEDIATE, instruction_0); } @@ -3779,8 +5031,7 @@ *vr4100: *vr5000: { - if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)) - SignalException (Trap, instruction_0); + do_tltiu (SD_, RS, IMMEDIATE, instruction_0); } @@ -3792,13 +5043,14 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { - if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]) - SignalException (Trap, instruction_0); + do_tltu (SD_, RS, RT, instruction_0); } @@ -3810,13 +5062,14 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { - if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) - SignalException (Trap, instruction_0); + do_tne (SD_, RS, RT, instruction_0); } @@ -3833,8 +5086,7 @@ *vr4100: *vr5000: { - if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE)) - SignalException (Trap, instruction_0); + do_tnei (SD_, RS, IMMEDIATE, instruction_0); } @@ -3854,8 +5106,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3864,7 +5118,7 @@ } -:function:::void:do_xori:int rs, int rt, unsigned16 immediate +:function:::void:do_xori:int rs, int rt, uint16_t immediate { TRACE_ALU_INPUT2 (GPR[rs], immediate); GPR[rt] = GPR[rs] ^ immediate; @@ -3880,8 +5134,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3889,7 +5145,7 @@ do_xori (SD_, RS, RT, IMMEDIATE); } - + // // MIPS Architecture: // @@ -3964,7 +5220,8 @@ *mipsIII: *mipsIV: *mips32: -*mips32r2: +*mips32r6: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -3975,10 +5232,19 @@ SignalException (ReservedInstruction, insn); } +:function:::void:check_fmt_p:int fmt, instruction_word insn +*mips32r2: +*micromips32: +{ + if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps)) + SignalException (ReservedInstruction, insn); +} + :function:::void:check_fmt_p:int fmt, instruction_word insn *mipsV: *mips64: *mips64r2: +*micromips64: { if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0))) @@ -4005,11 +5271,33 @@ *vr4100: *vr5000: *r3900: +*micromips32: +*micromips64: +{ + if (! COP_Usable (1)) + SignalExceptionCoProcessorUnusable (1); + + FCSR &= ~(fcsr_NAN2008_mask | fcsr_ABS2008_mask); + sim_fpu_quiet_nan_inverted = true; +} + +// Helper: +// +// Check that the FPU is currently usable, and signal a CoProcessorUnusable +// exception if not. +// + +:function:::void:check_fpu: +*mips32r6: +*mips64r6: { if (! COP_Usable (1)) SignalExceptionCoProcessorUnusable (1); -} + FCSR |= (fcsr_NAN2008_mask | fcsr_ABS2008_mask); + sim_fpu_quiet_nan_inverted = 0; + sim_fpu_set_mode (sim_fpu_ieee754_2008); +} // Helper: // @@ -4018,32 +5306,30 @@ // unsigned_word, which is limited to the size of the machine's registers. // -:function:::unsigned64:do_load_double:address_word base, address_word offset +:function:::uint64_t:do_load_double:address_word base, address_word offset *mipsII: *mips32: *mips32r2: +*mips32r6: +*micromips32: { int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); address_word vaddr; address_word paddr; - int uncached; - unsigned64 memval; - unsigned64 v; + uint64_t memval; + uint64_t v; - vaddr = loadstore_ea (SD_, base, offset); + paddr = vaddr = loadstore_ea (SD_, base, offset); if ((vaddr & AccessLength_DOUBLEWORD) != 0) { SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, AccessLength_DOUBLEWORD + 1, vaddr, read_transfer, sim_core_unaligned_signal); } - AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, - isREAL); - LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr, - isDATA, isREAL); - v = (unsigned64)memval; - LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4, - isDATA, isREAL); + LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL); + v = (uint64_t)memval; + LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA, + isREAL); return (bigendian ? ((v << 32) | memval) : (v | (memval << 32))); } @@ -4055,32 +5341,29 @@ // unsigned_word, which is limited to the size of the machine's registers. // -:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v +:function:::void:do_store_double:address_word base, address_word offset, uint64_t v *mipsII: *mips32: *mips32r2: +*micromips32: + *mips32r6: { int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); address_word vaddr; address_word paddr; - int uncached; - unsigned64 memval; + uint64_t memval; - vaddr = loadstore_ea (SD_, base, offset); + paddr = vaddr = loadstore_ea (SD_, base, offset); if ((vaddr & AccessLength_DOUBLEWORD) != 0) { SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, AccessLength_DOUBLEWORD + 1, vaddr, write_transfer, sim_core_unaligned_signal); } - AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, - isREAL); memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF)); - StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, - isREAL); + StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr, isREAL); memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32)); - StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, - isREAL); + StoreMemory (AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, isREAL); } @@ -4093,16 +5376,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - check_fmt_p (SD_, fmt, instruction_0); - StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt)); + do_abs_fmt (SD_, FMT, FD, FS, instruction_0); } @@ -4116,44 +5398,26 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - check_fmt_p (SD_, fmt, instruction_0); - StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); + do_add_fmt (SD_, FMT, FD, FS, FT, instruction_0); } -010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS +010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS "alnv.ps f, f, f, r" *mipsV: +*mips32r2: *mips64: *mips64r2: { - unsigned64 fs; - unsigned64 ft; - unsigned64 fd; - check_fpu (SD_); - check_u64 (SD_, instruction_0); - fs = ValueFPR (FS, fmt_ps); - if ((GPR[RS] & 0x3) != 0) - Unpredictable (); - if ((GPR[RS] & 0x4) == 0) - fd = fs; - else - { - ft = ValueFPR (FT, fmt_ps); - if (BigEndianCPU) - fd = PackPS (PSLower (fs), PSUpper (ft)); - else - fd = PackPS (PSLower (ft), PSUpper (fs)); - } - StoreFPR (FD, fmt_ps, fd); + do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0); } @@ -4238,29 +5502,25 @@ *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - check_fmt_p (SD_, fmt, instruction_0); - Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC); - TRACE_ALU_RESULT (ValueFCR (31)); + do_c_cond_fmt (SD_, COND, FMT, CC, FS, FT, instruction_0); } -010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt "ceil.l.%s f, f" *mipsIII: *mipsIV: *mipsV: +*mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt, - fmt_long)); + do_ceil_fmt (SD_, fmt_long, FMT, FD, FS, instruction_0); } @@ -4272,16 +5532,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt, - fmt_word)); + do_ceil_fmt (SD_, fmt_word, FMT, FD, FS, instruction_0); } @@ -4322,18 +5581,12 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: { - check_fpu (SD_); - if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31) - { - unsigned_word fcr = ValueFCR (FS); - TRACE_ALU_INPUT1 (fcr); - GPR[RT] = fcr; - } - /* else NOP */ - TRACE_ALU_RESULT (GPR[RT]); + do_cfc1 (SD_, RT, FS); } 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a @@ -4367,14 +5620,12 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: { - check_fpu (SD_); - TRACE_ALU_INPUT1 (GPR[RT]); - if (FS == 25 || FS == 26 || FS == 28 || FS == 31) - StoreFCR (FS, GPR[RT]); - /* else NOP */ + do_ctc1 (SD_, RT, FS); } @@ -4390,51 +5641,44 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - if ((fmt == fmt_double) | 0) - SignalException (ReservedInstruction, instruction_0); - StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt, - fmt_double)); + do_cvt_d_fmt (SD_, FMT, FD, FS, instruction_0); } -010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt "cvt.l.%s f, f" *mipsIII: *mipsIV: *mipsV: +*mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word))) - SignalException (ReservedInstruction, instruction_0); - StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt, - fmt_long)); + do_cvt_l_fmt (SD_, FMT, FD, FS, instruction_0); } -010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S +010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S "cvt.ps.s f, f, f" *mipsV: +*mips32r2: *mips64: *mips64r2: { - check_fpu (SD_); - check_u64 (SD_, instruction_0); - StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single), - ValueFPR (FT, fmt_single))); + do_cvt_ps_s (SD_, FD, FS, FT, instruction_0); } @@ -4450,42 +5694,37 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - if ((fmt == fmt_single) | 0) - SignalException (ReservedInstruction, instruction_0); - StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt, - fmt_single)); + do_cvt_s_fmt (SD_, FMT, FD, FS, instruction_0); } -010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL +010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL "cvt.s.pl f, f" *mipsV: +*mips32r2: *mips64: *mips64r2: { - check_fpu (SD_); - check_u64 (SD_, instruction_0); - StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps))); + do_cvt_s_pl (SD_, FD, FS, instruction_0); } -010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU +010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU "cvt.s.pu f, f" *mipsV: +*mips32r2: *mips64: *mips64r2: { - check_fpu (SD_); - check_u64 (SD_, instruction_0); - StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps))); + do_cvt_s_pu (SD_, FD, FS, instruction_0); } @@ -4498,18 +5737,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word))) - SignalException (ReservedInstruction, instruction_0); - StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt, - fmt_word)); + do_cvt_w_fmt (SD_, FMT, FD, FS, instruction_0); } @@ -4522,15 +5758,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); + do_div_fmt (SD_, FMT, FD, FS, FT, instruction_0); } @@ -4538,7 +5774,7 @@ "dmfc1 r, f" *mipsIII: { - unsigned64 v; + uint64_t v; check_fpu (SD_); check_u64 (SD_, instruction_0); if (SizeFGR () == 64) @@ -4557,19 +5793,14 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { check_fpu (SD_); check_u64 (SD_, instruction_0); - if (SizeFGR () == 64) - GPR[RT] = FGR[FS]; - else if ((FS & 0x1) == 0) - GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS]; - else - GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0; - TRACE_ALU_RESULT (GPR[RT]); + do_dmfc1b (SD_, RT, FS); } @@ -4577,7 +5808,7 @@ "dmtc1 r, f" *mipsIII: { - unsigned64 v; + uint64_t v; check_fpu (SD_); check_u64 (SD_, instruction_0); if (SizeFGR () == 64) @@ -4598,36 +5829,32 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { check_fpu (SD_); check_u64 (SD_, instruction_0); - if (SizeFGR () == 64) - StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); - else if ((FS & 0x1) == 0) - StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]); - else - Unpredictable (); + do_dmtc1b (SD_, RT, FS); } -010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt "floor.l.%s f, f" *mipsIII: *mipsIV: *mipsV: +*mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt, - fmt_long)); + do_floor_fmt (SD_, fmt_long, FMT, FD, FS); } @@ -4639,16 +5866,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt, - fmt_word)); + do_floor_fmt (SD_, fmt_word, FMT, FD, FS); } @@ -4657,6 +5883,7 @@ *mipsII: *mips32: *mips32r2: +*mips32r6: { check_fpu (SD_); COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET))); @@ -4670,6 +5897,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -4679,6 +5907,15 @@ } +010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1 +"ldxc1 f, r(r)" +*mips32r2: +{ + check_fpu (SD_); + COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX])); +} + + 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1 "ldxc1 f, r(r)" *mipsIV: @@ -4693,21 +5930,23 @@ } +010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1 +"luxc1 f, r(r)" +*mips32r2: +{ + do_luxc1_32 (SD_, FD, INDEX, BASE); +} + + 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1 "luxc1 f, r(r)" *mipsV: *mips64: *mips64r2: { - address_word base = GPR[BASE]; - address_word index = GPR[INDEX]; - address_word vaddr = base + index; check_fpu (SD_); check_u64 (SD_, instruction_0); - /* Arrange for the bottom 3 bits of (base + index) to be 0. */ - if ((vaddr & 0x7) != 0) - index -= (vaddr & 0x7); - COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index)); + do_luxc1_64 (SD_, FD, INDEX, BASE); } @@ -4720,46 +5959,42 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - check_fpu (SD_); - COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); + do_lwc1 (SD_, FT, OFFSET, BASE); } -010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1 +010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1 "lwxc1 f, r(r)" *mipsIV: *mipsV: +*mips32r2: *mips64: *mips64r2: *vr5000: { - check_fpu (SD_); - check_u64 (SD_, instruction_0); - COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX])); + do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0); } -010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt +010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt "madd.%s f, f, f, f" *mipsIV: *mipsV: +*mips32r2: *mips64: *mips64r2: *vr5000: { - int fmt = FMT; - check_fpu (SD_); - check_u64 (SD_, instruction_0); - check_fmt_p (SD_, fmt, instruction_0); - StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt), - ValueFPR (FR, fmt), fmt)); + do_madd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0); } @@ -4769,28 +6004,28 @@ *mipsII: *mipsIII: { - unsigned64 v; + uint64_t v; check_fpu (SD_); v = EXTEND32 (FGR[FS]); PENDING_FILL (RT, v); TRACE_ALU_RESULT (v); } - + 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b "mfc1 r, f" *mipsIV: *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: -{ - check_fpu (SD_); - GPR[RT] = EXTEND32 (FGR[FS]); - TRACE_ALU_RESULT (GPR[RT]); +{ + do_mfc1b (SD_, RT, FS); } @@ -4803,16 +6038,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - check_fmt_p (SD_, fmt, instruction_0); - StoreFPR (FD, fmt, ValueFPR (FS, fmt)); + do_mov_fmt (SD_, FMT, FD, FS, instruction_0); } @@ -4828,9 +6062,7 @@ *mips64r2: *vr5000: { - check_fpu (SD_); - if (GETFCC(CC) == TF) - GPR[RD] = GPR[RS]; + do_movtf (SD_, TF, RD, RS, CC); } @@ -4846,24 +6078,7 @@ *mips64r2: *vr5000: { - int fmt = FMT; - check_fpu (SD_); - if (fmt != fmt_ps) - { - if (GETFCC(CC) == TF) - StoreFPR (FD, fmt, ValueFPR (FS, fmt)); - else - StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */ - } - else - { - unsigned64 fd; - fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD, - fmt_ps)), - PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD, - fmt_ps))); - StoreFPR (FD, fmt_ps, fd); - } + do_movtf_fmt (SD_, TF, FMT, FD, FS, CC); } @@ -4877,11 +6092,7 @@ *mips64r2: *vr5000: { - check_fpu (SD_); - if (GPR[RT] != 0) - StoreFPR (FD, FMT, ValueFPR (FS, FMT)); - else - StoreFPR (FD, FMT, ValueFPR (FD, FMT)); + do_movn_fmt (SD_, FMT, FD, FS, RT); } @@ -4902,28 +6113,20 @@ *mips64r2: *vr5000: { - check_fpu (SD_); - if (GPR[RT] == 0) - StoreFPR (FD, FMT, ValueFPR (FS, FMT)); - else - StoreFPR (FD, FMT, ValueFPR (FD, FMT)); + do_movz_fmt (SD_, FMT, FD, FS, RT); } -010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt +010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt "msub.%s f, f, f, f" *mipsIV: *mipsV: +*mips32r2: *mips64: *mips64r2: *vr5000: { - int fmt = FMT; - check_fpu (SD_); - check_u64 (SD_, instruction_0); - check_fmt_p (SD_, fmt, instruction_0); - StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), - ValueFPR (FR, fmt), fmt)); + do_msub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0); } @@ -4932,14 +6135,14 @@ *mipsI: *mipsII: *mipsIII: -{ +{ check_fpu (SD_); if (SizeFGR () == 64) PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT]))); else PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT])); TRACE_FP_RESULT (GPR[RT]); -} +} 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b "mtc1 r, f" @@ -4947,14 +6150,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - check_fpu (SD_); - StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT])); + do_mtc1b (SD_, RT, FS); } @@ -4967,16 +6171,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - check_fmt_p (SD_, fmt, instruction_0); - StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); + do_mul_fmt (SD_, FMT, FD, FS, FT, instruction_0); } @@ -4989,122 +6192,98 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - check_fmt_p (SD_, fmt, instruction_0); - StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt)); + do_neg_fmt (SD_, FMT, FD, FS, instruction_0); } -010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt +010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt "nmadd.%s f, f, f, f" *mipsIV: *mipsV: +*mips32r2: *mips64: *mips64r2: *vr5000: { - int fmt = FMT; - check_fpu (SD_); - check_u64 (SD_, instruction_0); - check_fmt_p (SD_, fmt, instruction_0); - StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt), - ValueFPR (FR, fmt), fmt)); + do_nmadd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0); } -010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt +010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt "nmsub.%s f, f, f, f" *mipsIV: *mipsV: +*mips32r2: *mips64: *mips64r2: *vr5000: { - int fmt = FMT; - check_fpu (SD_); - check_u64 (SD_, instruction_0); - check_fmt_p (SD_, fmt, instruction_0); - StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), - ValueFPR (FR, fmt), fmt)); + do_nmsub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0); } -010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS +010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS "pll.ps f, f, f" *mipsV: +*mips32r2: *mips64: *mips64r2: { - check_fpu (SD_); - check_u64 (SD_, instruction_0); - StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)), - PSLower (ValueFPR (FT, fmt_ps)))); + do_pll_ps (SD_, FD, FS, FT, instruction_0); } -010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS +010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS "plu.ps f, f, f" *mipsV: +*mips32r2: *mips64: *mips64r2: { - check_fpu (SD_); - check_u64 (SD_, instruction_0); - StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)), - PSUpper (ValueFPR (FT, fmt_ps)))); + do_plu_ps (SD_, FD, FS, FT, instruction_0); } -010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX +010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX "prefx , r(r)" *mipsIV: *mipsV: +*mips32r2: *mips64: *mips64r2: *vr5000: { - address_word base = GPR[BASE]; - address_word index = GPR[INDEX]; - { - address_word vaddr = loadstore_ea (SD_, base, index); - address_word paddr; - int uncached; - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - Prefetch(uncached,paddr,vaddr,isDATA,HINT); - } + do_prefx (SD_, HINT, INDEX, BASE); } -010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS +010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS "pul.ps f, f, f" *mipsV: +*mips32r2: *mips64: *mips64r2: { - check_fpu (SD_); - check_u64 (SD_, instruction_0); - StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)), - PSLower (ValueFPR (FT, fmt_ps)))); + do_pul_ps (SD_, FD, FS, FT, instruction_0); } -010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS +010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS "puu.ps f, f, f" *mipsV: +*mips32r2: *mips64: *mips64r2: { - check_fpu (SD_); - check_u64 (SD_, instruction_0); - StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)), - PSUpper (ValueFPR (FT, fmt_ps)))); + do_puu_ps (SD_, FD, FS, FT, instruction_0); } @@ -5112,31 +6291,32 @@ "recip.%s f, f" *mipsIV: *mipsV: +*mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr5000: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt)); + do_recip_fmt (SD_, FMT, FD, FS); } -010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt "round.l.%s f, f" *mipsIII: *mipsIV: *mipsV: +*mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt, - fmt_long)); + do_round_fmt (SD_, fmt_long, FMT, FD, FS); } @@ -5148,16 +6328,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt, - fmt_word)); + do_round_fmt (SD_, fmt_word, FMT, FD, FS); } @@ -5165,13 +6344,14 @@ "rsqrt.%s f, f" *mipsIV: *mipsV: +*mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr5000: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt)); + do_rsqrt_fmt (SD_, FMT, FD, FS); } @@ -5180,9 +6360,9 @@ *mipsII: *mips32: *mips32r2: +*mips32r6: { - check_fpu (SD_); - do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); + do_sdc1 (SD_, FT, OFFSET, BASE); } @@ -5193,6 +6373,7 @@ *mipsV: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: @@ -5202,6 +6383,15 @@ } +010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1 +"sdxc1 f, r(r)" +*mips32r2: +{ + check_fpu (SD_); + do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); +} + + 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1 "sdxc1 f, r(r)" *mipsIV: @@ -5216,22 +6406,23 @@ } +010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1 +"suxc1 f, r(r)" +*mips32r2: +{ + do_suxc1_32 (SD_, FS, INDEX, BASE); +} + + 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1 "suxc1 f, r(r)" *mipsV: *mips64: *mips64r2: { - unsigned64 v; - address_word base = GPR[BASE]; - address_word index = GPR[INDEX]; - address_word vaddr = base + index; check_fpu (SD_); check_u64 (SD_, instruction_0); - /* Arrange for the bottom 3 bits of (base + index) to be 0. */ - if ((vaddr & 0x7) != 0) - index -= (vaddr & 0x7); - do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS)); + do_suxc1_64 (SD_, FS, INDEX, BASE); } @@ -5243,15 +6434,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt))); + do_sqrt_fmt (SD_, FMT, FD, FS); } @@ -5264,16 +6455,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - check_fmt_p (SD_, fmt, instruction_0); - StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt)); + do_sub_fmt (SD_, FMT, FD, FS, FT, instruction_0); } @@ -5287,40 +6477,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - address_word base = GPR[BASE]; - address_word offset = EXTEND16 (OFFSET); - check_fpu (SD_); - { - address_word vaddr = loadstore_ea (SD_, base, offset); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - { - SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal); - } - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - uword64 memval = 0; - uword64 memval1 = 0; - uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); - address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0); - address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0); - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); - byte = ((vaddr & mask) ^ bigendiancpu); - memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte)); - StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } + do_swc1 (SD_, FT, OFFSET, BASE, instruction_0); } @@ -5328,58 +6493,30 @@ "swxc1 f, r(r)" *mipsIV: *mipsV: +*mips32r2: *mips64: *mips64r2: *vr5000: { - - address_word base = GPR[BASE]; - address_word index = GPR[INDEX]; - check_fpu (SD_); - check_u64 (SD_, instruction_0); - { - address_word vaddr = loadstore_ea (SD_, base, index); - address_word paddr; - int uncached; - if ((vaddr & 3) != 0) - { - SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal); - } - else - { - if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL)) - { - unsigned64 memval = 0; - unsigned64 memval1 = 0; - unsigned64 mask = 0x7; - unsigned int byte; - paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2))); - byte = ((vaddr & mask) ^ (BigEndianCPU << 2)); - memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte)); - { - StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL); - } - } - } - } + do_swxc1 (SD_, FS, INDEX, BASE, instruction_0); } -010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt +010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt "trunc.l.%s f, f" *mipsIII: *mipsIV: *mipsV: +*mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt, - fmt_long)); + do_trunc_fmt (SD_, fmt_long, FMT, FD, FS); } @@ -5391,19 +6528,18 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - int fmt = FMT; - check_fpu (SD_); - StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt, - fmt_word)); + do_trunc_fmt (SD_, fmt_word, FMT, FD, FS); } - + // // MIPS Architecture: // @@ -5420,8 +6556,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: @@ -5443,8 +6581,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: @@ -5458,8 +6598,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: @@ -5472,11 +6614,23 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: +:function:::void:do_cache:int op, int rbase, int roffset, address_word instruction_0 +{ + address_word base = GPR[rbase]; + address_word offset = EXTEND16 (roffset); + { + address_word vaddr = loadstore_ea (SD_, base, offset); + address_word paddr = vaddr; + CacheOp(op, vaddr, paddr, instruction_0); + } +} 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE "cache , (r)" @@ -5491,41 +6645,35 @@ *vr5000: *r3900: { - address_word base = GPR[BASE]; - address_word offset = EXTEND16 (OFFSET); - { - address_word vaddr = loadstore_ea (SD_, base, offset); - address_word paddr; - int uncached; - if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL)) - CacheOp(OP,vaddr,paddr,instruction_0); - } + do_cache (SD_, OP, BASE, OFFSET, instruction_0); } -010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0 +010000,00001,5.RT,5.RD,00000000,3.SEL:COP0:64::DMFC0 "dmfc0 r, r" *mipsIII: *mipsIV: *mipsV: *mips64: *mips64r2: +*mips64r6: { check_u64 (SD_, instruction_0); - DecodeCoproc (instruction_0); + DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RD, SEL); } -010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0 +010000,00101,5.RT,5.RD,00000000,3.SEL:COP0:64::DMTC0 "dmtc0 r, r" *mipsIII: *mipsIV: *mipsV: *mips64: *mips64r2: +*mips64r6: { check_u64 (SD_, instruction_0); - DecodeCoproc (instruction_0); + DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RD, SEL); } @@ -5536,8 +6684,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: { @@ -5556,8 +6706,8 @@ } -010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0 -"mfc0 r, r # " +010000,00000,5.RT,5.RD,00000000,3.SEL:COP0:32::MFC0 +"mfc0 r, r # " *mipsI: *mipsII: *mipsIII: @@ -5565,19 +6715,21 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { TRACE_ALU_INPUT0 (); - DecodeCoproc (instruction_0); + DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RD, SEL); TRACE_ALU_RESULT (GPR[RT]); } -010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0 -"mtc0 r, r # " +010000,00100,5.RT,5.RD,00000000,3.SEL:COP0:32::MTC0 +"mtc0 r, r # " *mipsI: *mipsII: *mipsIII: @@ -5585,13 +6737,15 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: *r3900: { - DecodeCoproc (instruction_0); + DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RD, SEL); } @@ -5606,7 +6760,7 @@ *vr5000: *r3900: { - DecodeCoproc (instruction_0); + DecodeCoproc (instruction_0, 0, cp0_rfe, 0, 0, 0x10); } @@ -5619,12 +6773,14 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *r3900: { - DecodeCoproc (instruction_0); + DecodeCoproc (instruction_0, 2, 0, 0, 0, 0); } @@ -5638,8 +6794,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: @@ -5653,8 +6811,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: @@ -5668,8 +6828,10 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: @@ -5683,13 +6845,16 @@ *mipsV: *mips32: *mips32r2: +*mips32r6: *mips64: *mips64r2: +*mips64r6: *vr4100: *vr5000: :include:::mips3264r2.igen +:include:::mips3264r6.igen :include:::m16.igen :include:::m16e.igen :include:::mdmx.igen @@ -5697,4 +6862,9 @@ :include:::sb1.igen :include:::tx.igen :include:::vr.igen +:include:::dsp.igen +:include:::dsp2.igen +:include:::smartmips.igen +:include:::micromips.igen +:include:::micromipsdsp.igen