X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=sim%2For1k%2FMakefile.in;h=3f1c432c3720e472e3671fb28e7862e64e87d8f9;hb=de8a2781a57ecb4a852fb5b734bc7ce71bad34c9;hp=acffff4949455387286c95c039fd19864d9ab08f;hpb=fa8b7c2128cd03135b7d31ae2ecbc2d3273e990d;p=binutils-gdb.git

diff --git a/sim/or1k/Makefile.in b/sim/or1k/Makefile.in
index acffff49494..3f1c432c372 100644
--- a/sim/or1k/Makefile.in
+++ b/sim/or1k/Makefile.in
@@ -1,5 +1,5 @@
 # Makefile template for configure for the or1k simulator
-# Copyright (C) 2017 Free Software Foundation, Inc.
+# Copyright (C) 2017-2021 Free Software Foundation, Inc.
 #
 # This file is part of GDB, the GNU debugger.
 #
@@ -31,21 +31,12 @@ OR1K_OBJS = \
 
 SIM_OBJS = \
 	$(SIM_NEW_COMMON_OBJS) \
-	sim-cpu.o \
-	sim-hload.o \
-	sim-hrw.o \
-	sim-reg.o \
 	cgen-utils.o \
 	cgen-trace.o \
 	cgen-scache.o \
 	cgen-run.o \
 	cgen-fpu.o \
-	cgen-accfp.o \
-	sim-reason.o \
-	sim-engine.o \
-	sim-model.o \
-	sim-stop.o \
-	$(TRAPS_OBJ)
+	cgen-accfp.o
 
 SIM_OBJS += $(OR1K_OBJS)
 
@@ -62,9 +53,6 @@ SIM_EXTRA_CFLAGS =
 
 SIM_EXTRA_LIBS = -lm
 
-SIM_RUN_OBJS = nrun.o
-SIM_EXTRA_CLEAN = or1k-clean
-
 ## COMMON_POST_CONFIG_FRAG
 
 arch = or1k
@@ -77,24 +65,9 @@ OR1K32BF_INCLUDE_DEPS = \
 	decode.h \
 	eng.h
 
-mloop.c eng.h: stamp-mloop ; @true
-stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
-	$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
-		-mono -fast -pbb -switch sem-switch.c \
-		-cpu or1k32bf -infile $(srcdir)/mloop.in
-	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
-	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
-	touch stamp-mloop
-mloop.o: mloop.c sem-switch.c $(OR1K32BF_INCLUDE_DEPS)
 or1k.o: or1k.c $(OR1K32BF_INCLUDE_DEPS)
 	$(COMPILE) $<
 	$(POSTCOMPILE)
-arch.o: arch.c $(SIM_MAIN_DEPS)
-cpu.o: cpu.c $(OR1K32BF_INCLUDE_DEPS)
-decode.o: decode.c $(OR1K32BF_INCLUDE_DEPS)
-sem.o: sem.c $(OR1K32BF_INCLUDE_DEPS)
-sem-switch.o: sem-switch.c $(OR1K32BF_INCLUDE_DEPS)
-model.o: model.c $(OR1K32BF_INCLUDE_DEPS)
 
 sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h eng.h
 	$(COMPILE) $<
@@ -104,15 +77,7 @@ traps.o: traps.c $(SIM_MAIN_DEPS) eng.h
 	$(COMPILE) $<
 	$(POSTCOMPILE)
 
-or1k-clean:
-	rm -f mloop.c eng.h stamp-mloop
-
-# cgen support, enable with --enable-cgen-maint
-CGEN_MAINT = ; @true
-# The following line is commented in or out depending upon --enable-cgen-maint.
-@CGEN_MAINT@CGEN_MAINT =
-
-stamps: stamp-arch stamp-cpu stamp-mloop
+stamps: stamp-arch stamp-cpu
 
 # NOTE: Generated source files are specified as full paths,
 # e.g. $(srcdir)/arch.c, because make may decide the files live
@@ -131,7 +96,7 @@ stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(OR1K_CGEN_DEPS)
 	  mach=or32,or32nd \
 	  archfile=$(CPU_DIR)/or1k.cpu \
 	  FLAGS="with-scache"
-	touch $@
+	$(SILENCE) touch $@
 $(srcdir)/arch.h $(srcdir)/arch.c $(srcdir)/cpuall.h: $(CGEN_MAINT) stamp-arch
 	@true
 
@@ -142,6 +107,6 @@ stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(OR1K_CGEN_DEPS)
 	  archfile=$(CPU_DIR)/or1k.cpu \
 	  FLAGS="with-scache" \
 	  EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
-	touch $@
+	$(SILENCE) touch $@
 $(srcdir)/cpu.h $(srcdir)/cpu.c $(srcdir)/model.c $(srcdir)/sem.c $(srcdir)/sem-switch.c $(srcdir)/decode.c $(srcdir)/decode.h: $(CGEN_MAINT) stamp-cpu
 	@true