X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=simple_v_extension%2Fspecification.mdwn;h=73f0d15cc59a69f71d9bf54f7e6e02b7329a8d56;hb=9187686d66ea9c5f6feb6036fbc3cd82985d7557;hp=dea2ffd36b9f8e33cee079ae00cbbba1f35d94e2;hpb=9ee5999959ea05a06f2c91ac6cc5e9fb877a1891;p=libreriscv.git

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index dea2ffd36..73f0d15cc 100644
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -1,3 +1,4 @@
+
 # Simple-V (Parallelism Extension Proposal) Specification
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton
@@ -66,7 +67,7 @@ To emphasise that clearly: Simple-V (SV) is *not*:
 * A SIMT system
 * A Vectorisation Microarchitecture
 * A microarchitecture of any specific kind
-* A mandary parallel processor microarchitecture of any kind
+* A mandatory parallel processor microarchitecture of any kind
 * A supercomputer extension
 
 SV does **not** tell implementors how or even if they should implement