X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=simple_v_extension%2Fvblock_format_table.mdwn;h=b3b6a6586f283b360dc67386472b5cf5bc26eb31;hb=cd205febb70f4e329887cd8d18913294730c03b4;hp=68ee6646c5974eecf86b7bf0dbbe1a2b2fbacd61;hpb=73b9cfdf7fccdd398338535f4308f43526b83970;p=libreriscv.git

diff --git a/simple_v_extension/vblock_format_table.mdwn b/simple_v_extension/vblock_format_table.mdwn
index 68ee6646c..b3b6a6586 100644
--- a/simple_v_extension/vblock_format_table.mdwn
+++ b/simple_v_extension/vblock_format_table.mdwn
@@ -14,13 +14,18 @@ of the RISC-V ISA, is as follows:
 The VL/MAXVL/SubVL Block format, when 16xil != 0b111, is:
 
 [[!table  data="""
-31:30 | 29:28 | 27:22    | 21 | 20:19   | 18:16    | comment                              |
-0b00  | SubVL | imm[5:0] |rsvd| rd[4:0]           || sv.setvl rd, x0, imm    |
-0b01  | SubVL | imm[5:0] | rs1[2:0]    || rd[2:0]  | RVC reg format, sv.setvl rd, rs, imm |
-0b10  | SubVL | imm[5:0] |rsvd|  rs1[4:0]         || sv.setvl x0, rs1, imm        |
-0b11  | rsvd  | rsvd     |rsvd| rsvd              || reserved, all 0s                     |
+31:30 | 29:28 | 27:22    | 21 | 20:19   | 18:16    | comment.................. |
+0b00  | SubVL | imm[5:0] |rsvd| rd[4:0]           || sv.setvl rd, x0, imm      |
+0b01  | SubVL | imm[5:0] | rs1[2:0]    || rd[2:0]  | sv.setvl rd, rs1, imm (1) |
+0b10  | SubVL | imm[5:0] |rsvd|  rs1[4:0]         || sv.setvl x0, rs1, imm     |
+0b11  | rsvd  | rsvd     |rsvd| rsvd              || reserved, all 0s          |
 """]]
 
+Note (1) - Registers are in RVC format (x8-x15)
+
+Note (2) - [[specification/sv.setvl]] behaviour is expected, as if an sv.setvl
+instruction had actually been called.
+
 When 16xil is 0b111, this is the "Extended" Format, using the >= 192-bit
 RISC-V ISA format.  Note that the length is 96+16\*nnnnn, not 192+
 
@@ -31,12 +36,26 @@ RISC-V ISA format.  Note that the length is 96+16\*nnnnn, not 192+
 
 VBLOCK2 extends the VBLOCK fields:
 
-| 15:12 | 11:10  | 9:8    | 7:5   | 4:0  |
-| ----- | -----  | ----   | ---   | ---- |
-| rsvd  | rplen2 | pplen2 | swlen | ilen |
+| 15   | 14:12 | 11:10  | 9:8    | 7:5   | 4:0  |
+| ---- | ----- | -----  | ----   | ---   | ---- |
+| rsvd | mapsz | rplen2 | pplen2 | swlen | ilen |
 
 * ilen is the instruction length (number of 16-bit blocks)
 * swlen specifies the number of "swizzle" blocks
 * rplen2 extends rplen by 2 bits
 * pplen2 extends pplen by 2 bits
-* 4 bits are reserved for additional tables (Matrices?)
+* mapsz indicates the size of the "remap" area.  See table below for size
+* 1 bit is reserved for extensions
+
+Mapsz to Remap size is in number of 16-bit blocks:
+
+| mapsz | remap size |
+| ----- | ---------- |
+| 0     | 0          |
+| 1     | 6          |
+| 2     | 7          |
+| 3     | 8          |
+| 4     | 10         |
+| 5     | 12         |
+| 6     | 14         |
+| 7     | 16         |