X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=simple_v_extension.mdwn;h=0642ce926d702469769bae2210773b1035398a95;hb=69f396a3a5e7b113ac7f4edc60dbb3641726b176;hp=b58665fb2cd1263fe320fd28532b9e2a68dd6447;hpb=91eb02462ea301cf580510a58f6d7ee7609d30cb;p=libreriscv.git diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index b58665fb2..0642ce926 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -1,13 +1,6 @@ # Variable-width Variable-packed SIMD / Simple-V / Parallelism Extension Proposal -* TODO 23may2018: CSR-CAM-ify regfile tables -* TODO 23may2018: zero-mark predication CSR -* TODO 28may2018: sort out VSETVL: CSR length to be removed? -* TODO 09jun2018: Chennai Presentation more up-to-date -* TODO 09jun2019: elwidth only 4 values (dflt, dflt/2, 8, 16) -* TODO 09jun2019: extra register banks (future option) -* TODO 09jun2019: new Reg CSR table (incl. packed=Y/N) - +**Note: this document is out of date and involved early ideas and discussions** Key insight: Simple-V is intended as an abstraction layer to provide a consistent "API" to parallelisation of existing *and future* operations. @@ -18,8 +11,13 @@ instruction queue (FIFO), pending execution. *Actual* parallelism, if added independently of Simple-V in the form of Out-of-order restructuring (including parallel ALU lanes) or VLIW -implementations, or SIMD, or anything else, would then benefit *if* -Simple-V was added on top. +implementations, or SIMD, or anything else, would then benefit from +the uniformity of a consistent API. + +**No arithmetic operations are added or required to be added.** SV is purely a parallelism API and consequentially is suitable for use even with RV32E. + +* Talk slides: +* Specification: now move to its own page: [[specification]] [[!toc ]] @@ -364,598 +362,218 @@ absolute bare minimum level of compliance with the "API" (software-traps when vectorisation is detected), all the way up to full supercomputing level all-hardware parallelism. Options are covered in the Appendix. -# CSRs - -There are two CSR tables needed to create lookup tables which are used at -the register decode phase. - -* Integer Register N is Vector -* Integer Register N is of implicit bitwidth M (M=default,8,16,32,64) -* Floating-point Register N is Vector of length M: r(N) -> r(N..N+M-1) -* Floating-point Register N is of implicit bitwidth M (M=default,8,16,32,64) -* Integer Register N is a Predication Register (note: a key-value store) - -Also (see Appendix, "Context Switch Example") it may turn out to be important -to have a separate (smaller) set of CSRs for M-Mode (and S-Mode) so that -Vectorised LOAD / STORE may be used to load and store multiple registers: -something that is missing from the Base RV ISA. - -Notes: - -* for the purposes of LOAD / STORE, Integer Registers which are - marked as a Vector will result in a Vector LOAD / STORE. -* Vector Lengths are *not* the same as vsetl but are an integral part - of vsetl. -* Actual vector length is *multipled* by how many blocks of length - "bitwidth" may fit into an XLEN-sized register file. -* Predication is a key-value store due to the implicit referencing, - as opposed to having the predicate register explicitly in the instruction. -* Whilst the predication CSR is a key-value store it *generates* easier-to-use - state information. -* TODO: assess whether the same technique could be applied to the other - Vector CSRs, particularly as pointed out in Section 17.8 (Draft RV 0.4, - V2.3-Draft ISA Reference) it becomes possible to greatly reduce state - needed for context-switches (empty slots need never be stored). - -## Predication CSR - -The Predication CSR is a key-value store indicating whether, if a given -destination register (integer or floating-point) is referred to in an -instruction, it is to be predicated. However it is important to note -that the *actual* register is *different* from the one that ends up -being used, due to the level of indirection through the lookup table. -This includes (in the future) redirecting to a *second* bank of -integer registers (as a future option) - -* regidx is the actual register that in combination with the - i/f flag, if that integer or floating-point register is referred to, - results in the lookup table being referenced to find the predication - mask to use on the operation in which that (regidx) register has - been used -* predidx (in combination with the bank bit in the future) is the - *actual* register to be used for the predication mask. Note: - in effect predidx is actually a 6-bit register address, as the bank - bit is the MSB (and is nominally set to zero for now). -* inv indicates that the predication mask bits are to be inverted - prior to use *without* actually modifying the contents of the - register itself. -* zeroing is either 1 or 0, and if set to 1, the operation must - place zeros in any element position where the predication mask is - set to zero. If zeroing is set to 1, unpredicated elements *must* - be left alone. Some microarchitectures may choose to interpret - this as skipping the operation entirely. Others which wish to - stick more closely to a SIMD architecture may choose instead to - interpret unpredicated elements as an internal "copy element" - operation (which would be necessary in SIMD microarchitectures - that perform register-renaming) - -| PrCSR | 13 | 12 | 11 | 10 | (9..5) | (4..0) | -| ----- | - | - | - | - | ------- | ------- | -| 0 | bank0 | zero0 | inv0 | i/f | regidx | predidx | -| 1 | bank1 | zero1 | inv1 | i/f | regidx | predidx | -| .. | bank.. | zero.. | inv.. | i/f | regidx | predidx | -| 15 | bank15 | zero15 | inv15 | i/f | regidx | predidx | - -The Predication CSR Table is a key-value store, so implementation-wise -it will be faster to turn the table around (maintain topologically -equivalent state): - - struct pred { - bool zero; - bool inv; - bool bank; // 0 for now, 1=rsvd - bool enabled; - int predidx; // redirection: actual int register to use - } - - struct pred fp_pred_reg[32]; // 64 in future (bank=1) - struct pred int_pred_reg[32]; // 64 in future (bank=1) - - for (i = 0; i < 16; i++) - tb = int_pred_reg if CSRpred[i].type == 0 else fp_pred_reg; - idx = CSRpred[i].regidx - tb[idx].zero = CSRpred[i].zero - tb[idx].inv = CSRpred[i].inv - tb[idx].bank = CSRpred[i].bank - tb[idx].predidx = CSRpred[i].predidx - tb[idx].enabled = true - -So when an operation is to be predicated, it is the internal state that -is used. In Section 6.4.2 of Hwacha's Manual (EECS-2015-262) the following -pseudo-code for operations is given, where p is the explicit (direct) -reference to the predication register to be used: - - for (int i=0; i What does an ADD of two different-sized vectors do in simple-V? -[[!table data=""" -31 .. 27| 26 .. 25 |24 ... 20 | 19 15 | 14 12 | 11 .. 7 | 6 ... 0 | -funct5 | fmt | rs2 | rs1 | funct3 | rd | opcode | -5 | 2 | 5 | 5 | 3 | 4 | 7 | -10100 | 00/01/11 | src2 | src1 | 010 | pred rs3 | FEQ | -10100 | 00/01/11 | src2 | src1 | **011**| pred rs3 | FNE | -10100 | 00/01/11 | src2 | src1 | 001 | pred rs3 | FLT | -10100 | 00/01/11 | src2 | src1 | 000 | pred rs3 | FLE | -"""]] +* if the two source operands are not the same, throw an exception. +* if the destination operand is also a vector, and the source is longer + than the destination, throw an exception. -Note (**TBD**): floating-point exceptions will need to be extended -to cater for multiple exceptions (and statuses of the same). The -usual approach is to have an array of status codes and bit-fields, -and one exception, rather than throw separate exceptions for each -Vector element. +> And what about instructions like JALR?  +> What does jumping to a vector do? -In Hwacha EECS-2015-262 Section 6.7.2 the following pseudocode is given -for predicated compare operations of function "cmp": +* Throw an exception. Whether that actually results in spawning threads + as part of the trap-handling remains to be seen. - for (int i=0; i -With associated predication, vector-length adjustments and so on, -and temporarily ignoring bitwidth (which makes the comparisons more -complex), this becomes: +From the Chennai 2018 slides the following issues were raised. +Efforts to analyse and answer these questions are below. + +* Should future extra bank be included now? +* How many Register and Predication CSRs should there be? + (and how many in RV32E) +* How many in M-Mode (for doing context-switch)? +* Should use of registers be allowed to "wrap" (x30 x31 x1 x2)? +* Can CLIP be done as a CSR (mode, like elwidth) +* SIMD saturation (etc.) also set as a mode? +* Include src1/src2 predication on Comparison Ops? + (same arrangement as C.MV, with same flexibility/power) +* 8/16-bit ops is it worthwhile adding a "start offset"? + (a bit like misaligned addressing... for registers) + or just use predication to skip start? - if I/F == INT: # integer type cmp - preg = int_pred_reg[rd] - reg = int_regfile - else: - preg = fp_pred_reg[rd] - reg = fp_regfile - - s1 = reg_is_vectorised(src1); - s2 = reg_is_vectorised(src2); - if (!s2 && !s1) goto branch; - for (int i = 0; i < VL; ++i) - if (cmp(s1 ? reg[src1+i]:reg[src1], - s2 ? reg[src2+i]:reg[src2]) - preg[rs3] |= 1< +This is something that definitely needs actual evaluation and for +code to be run and the results analysed. At the time of writing +(12jul2018) that is too early to tell. An approximate best-guess +however would be 16 entries. -For full analysis of topological adaptation of RVV LOAD/STORE -see [[v_comparative_analysis]]. All three types (LD, LD.S and LD.X) -may be implicitly overloaded into the one base RV LOAD instruction, -and likewise for STORE. +RV32E however is a special case, given that it is highly unlikely +(but not outside the realm of possibility) that it would be used +for performance reasons but instead for reducing instruction count. +The number of CSR entries therefore has to be considered extremely +carefully. -Revised LOAD: +## How many CSR entries in M-Mode or S-Mode (for context-switching)? -[[!table data=""" -31 | 30 | 29 25 | 24 20 | 19 15 | 14 12 | 11 7 | 6 0 | -imm[11:0] |||| rs1 | funct3 | rd | opcode | -1 | 1 | 5 | 5 | 5 | 3 | 5 | 7 | -? | s | rs2 | imm[4:0] | base | width | dest | LOAD | -"""]] +The minimum required CSR entries would be 1 for each register-bank: +one for integer and one for floating-point. However, as shown +in the "Context Switch Example" section, for optimal efficiency +(minimal instructions in a low-latency situation) the CSRs for +the context-switch should be set up *and left alone*. -The exact same corresponding adaptation is also carried out on the single, -double and quad precision floating-point LOAD-FP and STORE-FP operations, -which fit the exact same instruction format. Thus all three types -(unit, stride and indexed) may be fitted into FLW, FLD and FLQ, -as well as FSW, FSD and FSQ. +This means that it is not really a good idea to touch the CSRs +used for context-switching in the M-Mode (or S-Mode) trap, so +if there is ever demonstrated a need for vectors then there would +need to be *at least* one more free. However just one does not make +much sense (as it one only covers scalar-vector ops) so it is more +likely that at least two extra would be needed. -Notes: +This *in addition* - in the RV32E case - if an RV32E implementation +happens also to support U/S/M modes. This would be considered quite +rare but not outside of the realm of possibility. -* LOAD remains functionally (topologically) identical to RVV LOAD - (for both integer and floating-point variants). -* Predication CSR-marking register is not explicitly shown in instruction, it's - implicit based on the CSR predicate state for the rd (destination) register -* rs2, the source, may *also be marked as a vector*, which implicitly - is taken to indicate "Indexed Load" (LD.X) -* Bit 30 indicates "element stride" or "constant-stride" (LD or LD.S) -* Bit 31 is reserved (ideas under consideration: auto-increment) -* **TODO**: include CSR SIMD bitwidth in the pseudo-code below. -* **TODO**: clarify where width maps to elsize +Conclusion: all needs careful analysis and future work. -Pseudo-code (excludes CSR SIMD bitwidth for simplicity): +## Should use of registers be allowed to "wrap" (x30 x31 x1 x2)? - if (unit-strided) stride = elsize; - else stride = areg[as2]; // constant-strided +On balance it's a neat idea however it does seem to be one where the +benefits are not really clear. It would however obviate the need for +an exception to be raised if the VL runs out of registers to put +things in (gets to x31, tries a non-existent x32 and fails), however +the "fly in the ointment" is that x0 is hard-coded to "zero". The +increment therefore would need to be double-stepped to skip over x0. +Some microarchitectures could run into difficulties (SIMD-like ones +in particular) so it needs a lot more thought. - pred_enabled = int_pred_enabled - preg = int_pred_reg[rd] +## Can CLIP be done as a CSR (mode, like elwidth) - for (int i=0; i What does an ADD of two different-sized vectors do in simple-V? +Therefore at first glance it does not make sense to use src1 and src2 +predication masks, as it breaks the rule of 3-operand instructions +to use the *destination* predication register. -* if the two source operands are not the same, throw an exception. -* if the destination operand is also a vector, and the source is longer - than the destination, throw an exception. +In this case however, the destination *is* a predication register +as opposed to being a predication mask that is applied *to* the +(vectorised) operation, element-at-a-time on src1 and src2. -> And what about instructions like JALR?  -> What does jumping to a vector do? +Thus the question is directly inter-related to whether the modification +of the predication mask should *itself* be predicated. -* Throw an exception. Whether that actually results in spawning threads - as part of the trap-handling remains to be seen. +It is quite complex, in other words, and needs careful consideration. + +## 8/16-bit ops is it worthwhile adding a "start offset"? + +The idea here is to make it possible, particularly in a "Packed SIMD" +case, to be able to avoid doing unaligned Load/Store operations +by specifying that operations, instead of being carried out +element-for-element, are offset by a fixed amount *even* in 8 and 16-bit +element Packed SIMD cases. + +For example rather than take 2 32-bit registers divided into 4 8-bit +elements and have them ADDed element-for-element as follows: + + r3[0] = add r4[0], r6[0] + r3[1] = add r4[1], r6[1] + r3[2] = add r4[2], r6[2] + r3[3] = add r4[3], r6[3] + +an offset of 1 would result in four operations as follows, instead: + + r3[0] = add r4[1], r6[0] + r3[1] = add r4[2], r6[1] + r3[2] = add r4[3], r6[2] + r3[3] = add r5[0], r6[3] + +In non-packed-SIMD mode there is no benefit at all, as a vector may +be created using a different CSR that has the offset built-in. So this +leaves just the packed-SIMD case to consider. + +Two ways in which this could be implemented / emulated (without special +hardware): + +* bit-manipulation that shuffles the data along by one byte (or one word) + either prior to or as part of the operation requiring the offset. +* just use an unaligned Load/Store sequence, even if there are performance + penalties for doing so. + +The question then is whether the performance hit is worth the extra hardware +involving byte-shuffling/shifting the data by an arbitrary offset. On +balance given that there are two reasonable instruction-based options, the +hardware-offset option should be left out for the initial version of SV, +with the option to consider it in an "advanced" version of the specification. # Impementing V on top of Simple-V @@ -1238,37 +856,35 @@ the question is asked "How can each of the proposals effectively implement ### Example Instruction translation: -Instructions "ADD r2 r4 r4" would result in three instructions being -generated and placed into the FIFO: +Instructions "ADD r7 r4 r4" would result in three instructions being +generated and placed into the FIFO. r7 and r4 are marked as "vectorised": -* ADD r2 r4 r4 -* ADD r2 r5 r5 -* ADD r2 r6 r6 +* ADD r7 r4 r4 +* ADD r8 r5 r5 +* ADD r9 r6 r6 + +Instructions "ADD r7 r4 r1" would result in three instructions being +generated and placed into the FIFO. r7 and r1 are marked as "vectorised" +whilst r4 is not: + +* ADD r7 r4 r1 +* ADD r8 r4 r2 +* ADD r9 r4 r3 ## Example of vector / vector, vector / scalar, scalar / scalar => vector add - register CSRvectorlen[XLEN][4]; # not quite decided yet about this one... - register CSRpredicate[XLEN][4]; # 2^4 is max vector length - register CSRreg_is_vectorised[XLEN]; # just for fun support scalars as well - register x[32][XLEN]; - - function op_add(rd, rs1, rs2, predr) - { -    /* note that this is ADD, not PADD */ -    int i, id, irs1, irs2; -    # checks CSRvectorlen[rd] == CSRvectorlen[rs] etc. ignored -    # also destination makes no sense as a scalar but what the hell... -    for (i = 0, id=0, irs1=0, irs2=0; i @@ -2043,6 +1659,61 @@ in advance to avoid. TBD: floating-point compare and other exception handling +------ + +Multi-LR/SC + +Please don't try to use the L1 itself. + +Use the Load and Store buffers which capture instruction state prior +to being accessed in the L1 (and prior to data arriving in the case of +Store buffer). + +Also, use the L1 Miss buffers as these already HAVE to be snooped by +coherence traffic. These are used to monitor that all participating +cache lines remain interference free, and amalgamate same into a CPU +signal accessible ia branch or predicate. + +The Load buffers manage inbound traffic +The Store buffers manage outbound traffic. + +Done properly, the participating cache lines can exceed the associativity +of the L1 cache without architectural harm (may incur additional latency). + + + +> > > so, let's say instead of another LR *cancelling* the load +> > > reservation, the SMP core / hardware thread *blocks* for +> > > up to 63 further instructions, waiting for the reservation +> > > to clear. +> > +> > Can you explain what you mean by this paragraph? +> +> best put in sequential events, probably. +> +> LR <-- 64-instruction countdown starts here +> ... 63 +> ... 62 +> LR same address <--- notes that core1 is on 61, +> so pauses for **UP TO** 61 cycles +> ... 32 +> SC <- core1 didn't reach zero, therefore valid, therefore +> core2 is now **UNBLOCKED**, is granted the +> load-reservation (and begins its **own** 64-cycle +> LR instruction countdown) +> ... 63 +> ... 62 +> ... +> ... +> SC <- also valid + +Looks to me that you could effect the same functionality by simply +holding onto the cache line in core 1 preventing core 2 from + getting past the LR. + +On the other hand, the freeze is similar to how the MP CRAYs did +ATOMIC stuff. + # References * SIMD considered harmful @@ -2080,3 +1751,5 @@ TBD: floating-point compare and other exception handling * * Full Description (last page) of RVV instructions +* PULP Low-energy Cluster Vector Processor +