X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=simple_v_extension.mdwn;h=723cc07259960db0b00ed61b10873a310b9e3ab8;hb=73743225d7873f2803c5481be1772211205c5be7;hp=2eea8dfc247c955416ff6257ca163f2d8e5a3b7a;hpb=8fc99b0a98bae3fd2876e1d201d2ff6580925d9b;p=libreriscv.git
diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 2eea8dfc2..723cc0725 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1502,37 +1502,35 @@ the question is asked "How can each of the proposals effectively implement
### Example Instruction translation:
-Instructions "ADD r2 r4 r4" would result in three instructions being
-generated and placed into the FIFO:
+Instructions "ADD r7 r4 r4" would result in three instructions being
+generated and placed into the FIFO. r7 and r4 are marked as "vectorised":
-* ADD r2 r4 r4
-* ADD r2 r5 r5
-* ADD r2 r6 r6
+* ADD r7 r4 r4
+* ADD r8 r5 r5
+* ADD r9 r6 r6
+
+Instructions "ADD r7 r4 r1" would result in three instructions being
+generated and placed into the FIFO. r7 and r1 are marked as "vectorised"
+whilst r4 is not:
+
+* ADD r7 r4 r1
+* ADD r8 r4 r2
+* ADD r9 r4 r3
## Example of vector / vector, vector / scalar, scalar / scalar => vector add
- register CSRvectorlen[XLEN][4]; # not quite decided yet about this one...
- register CSRpredicate[XLEN][4]; # 2^4 is max vector length
- register CSRreg_is_vectorised[XLEN]; # just for fun support scalars as well
- register x[32][XLEN];
-
- function op_add(rd, rs1, rs2, predr)
- {
- Â Â /* note that this is ADD, not PADD */
- Â Â int i, id, irs1, irs2;
- Â Â # checks CSRvectorlen[rd] == CSRvectorlen[rs] etc. ignored
- Â Â # also destination makes no sense as a scalar but what the hell...
- Â Â for (i = 0, id=0, irs1=0, irs2=0; i