X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=spike_main%2Fspike.cc;fp=spike_main%2Fspike.cc;h=863ee81b8e63d803f73a2073b7dfbf2811d04f41;hb=6c7c772b169d0e1a00998c48e63c7cae98e7aa6a;hp=3061b106ff9a34318b25f4bd7db04b9868ead390;hpb=85efaaaba8938a7026d5d9203c09e8be0fd66130;p=riscv-isa-sim.git

diff --git a/spike_main/spike.cc b/spike_main/spike.cc
index 3061b10..863ee81 100644
--- a/spike_main/spike.cc
+++ b/spike_main/spike.cc
@@ -28,6 +28,7 @@ static void help()
   fprintf(stderr, "  -H                 Start halted, allowing a debugger to connect\n");
   fprintf(stderr, "  --isa=<name>          RISC-V ISA string [default %s]\n", DEFAULT_ISA);
   fprintf(stderr, "  --pc=<address>        Override ELF entry point\n");
+  fprintf(stderr, "  --hartids=<a,b,...>   Explicitly specify hartids, default is 0,1,...\n");
   fprintf(stderr, "  --ic=<S>:<W>:<B>      Instantiate a cache model with S sets,\n");
   fprintf(stderr, "  --dc=<S>:<W>:<B>        W ways, and B-byte blocks (with S and\n");
   fprintf(stderr, "  --l2=<S>:<W>:<B>        B both powers of 2).\n");