X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2FSConscript;h=9f88bbeea34d8753d752cfb10403053d1f994c7c;hb=dd18ffe51d7dbef59804e7af3384fe0cc28447a5;hp=b166720a1cd4bba3a316535641328a12c09f0e0b;hpb=167fb86a694dbb49fe51cccbb4285bddcbf2cd44;p=gem5.git

diff --git a/src/SConscript b/src/SConscript
index b166720a1..9f88bbeea 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -47,6 +47,7 @@ Import('env')
 # Base sources used by all configurations.
 
 base_sources = Split('''
+	base/annotate.cc
 	base/circlebuf.cc
 	base/cprintf.cc
 	base/fast_alloc.cc
@@ -62,7 +63,6 @@ base_sources = Split('''
 	base/range.cc
 	base/random.cc
 	base/sat_counter.cc
-        base/serializer.cc
 	base/socket.cc
 	base/statistics.cc
 	base/str.cc
@@ -85,33 +85,56 @@ base_sources = Split('''
 	cpu/base.cc
 	cpu/cpuevent.cc
 	cpu/exetrace.cc
+        cpu/func_unit.cc
         cpu/op_class.cc
 	cpu/pc_event.cc
         cpu/quiesce_event.cc
 	cpu/static_inst.cc
-        cpu/sampler/sampler.cc
         cpu/simple_thread.cc
         cpu/thread_state.cc
 
-        encumbered/cpu/full/fu_pool.cc
-        
         mem/bridge.cc
         mem/bus.cc
-        mem/connector.cc
+        mem/dram.cc
         mem/mem_object.cc
         mem/packet.cc
         mem/physical.cc
         mem/port.cc
+        mem/tport.cc
+
+        mem/cache/base_cache.cc
+        mem/cache/cache.cc
+        mem/cache/coherence/coherence_protocol.cc
+        mem/cache/coherence/uni_coherence.cc
+        mem/cache/miss/blocking_buffer.cc
+        mem/cache/miss/miss_queue.cc
+        mem/cache/miss/mshr.cc
+        mem/cache/miss/mshr_queue.cc
+        mem/cache/prefetch/base_prefetcher.cc
+        mem/cache/prefetch/ghb_prefetcher.cc
+        mem/cache/prefetch/prefetcher.cc
+        mem/cache/prefetch/stride_prefetcher.cc
+        mem/cache/prefetch/tagged_prefetcher.cc
+        mem/cache/tags/base_tags.cc
+        mem/cache/tags/cache_tags.cc
+        mem/cache/tags/fa_lru.cc
+        mem/cache/tags/iic.cc
+        mem/cache/tags/lru.cc
+        mem/cache/tags/repl/gen.cc
+        mem/cache/tags/repl/repl.cc
+        mem/cache/tags/split.cc
+        mem/cache/tags/split_lifo.cc
+        mem/cache/tags/split_lru.cc
+
+        mem/cache/cache_builder.cc
 
 	sim/builder.cc
-	sim/configfile.cc
 	sim/debug.cc
 	sim/eventq.cc
 	sim/faults.cc
 	sim/main.cc
-        python/swig/main_wrap.cc
+        python/swig/cc_main_wrap.cc
 	sim/param.cc
-	sim/profile.cc
 	sim/root.cc
 	sim/serialize.cc
 	sim/sim_events.cc
@@ -197,6 +220,7 @@ full_system_sources = Split('''
 	dev/etherlink.cc
 	dev/etherpkt.cc
 	dev/ethertap.cc	
+        dev/i8254xGBe.cc
         dev/ide_ctrl.cc
 	dev/ide_disk.cc
 	dev/io_device.cc
@@ -209,7 +233,6 @@ full_system_sources = Split('''
 	dev/platform.cc
         dev/simconsole.cc
 	dev/simple_disk.cc
-	dev/sinic.cc
 	dev/tsunami.cc
 	dev/tsunami_cchip.cc
 	dev/tsunami_io.cc
@@ -219,7 +242,6 @@ full_system_sources = Split('''
 	dev/uart.cc
 	dev/uart8250.cc
 
-	kern/kernel_binning.cc
 	kern/kernel_stats.cc
 	kern/system_events.cc
 	kern/linux/events.cc
@@ -230,6 +252,7 @@ full_system_sources = Split('''
 
 	sim/pseudo_inst.cc
         ''')
+	#dev/sinic.cc
 
 
 if env['TARGET_ISA'] == 'alpha':
@@ -279,7 +302,7 @@ alpha_eio_sources = Split('''
 	encumbered/eio/eio.cc
         ''')
 
-if env['TARGET_ISA'] == 'ALPHA_ISA':
+if env['TARGET_ISA'] == 'alpha':
     syscall_emulation_sources += alpha_eio_sources
     
 memtest_sources = Split('''