X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Fnmigen_add_experiment.py;h=25beaddeab71fdcdbfc9c73c1177d2d8e3207284;hb=fa5e012497b1112e38aab538765188797a068520;hp=ef783cae007eb89e763f7224747faf1db1954b0e;hpb=f80d1cb3f97530ce7ee868cf30804675dc86f0b9;p=ieee754fpu.git

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index ef783cae..25beadde 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -170,7 +170,6 @@ class FPGetOp(FPState):
         """
         setattr(m.submodules, self.state_from, self.mod)
         m.d.comb += self.mod.in_op.eq(in_op)
-        #m.d.comb += self.out_op.eq(self.mod.out_op)
         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 
     def action(self, m):
@@ -185,22 +184,31 @@ class FPGetOp(FPState):
 
 
 class FPGet2OpMod(Trigger):
-    def __init__(self, width):
+    def __init__(self, width, id_wid):
         Trigger.__init__(self)
-        self.in_op1 = Signal(width, reset_less=True)
-        self.in_op2 = Signal(width, reset_less=True)
-        self.out_op1 = FPNumIn(None, width)
-        self.out_op2 = FPNumIn(None, width)
+        self.width = width
+        self.id_wid = id_wid
+        self.i = self.ispec()
+        self.o = self.ospec()
+
+    def ispec(self):
+        return FPADDBaseData(self.width, self.id_wid)
+
+    def ospec(self):
+        return FPNumBase2Ops(self.width, self.id_wid)
 
     def elaborate(self, platform):
         m = Trigger.elaborate(self, platform)
-        #m.submodules.get_op_in = self.in_op
-        m.submodules.get_op1_out = self.out_op1
-        m.submodules.get_op2_out = self.out_op2
+        m.submodules.get_op1_out = self.o.a
+        m.submodules.get_op2_out = self.o.b
+        out_op1 = FPNumIn(None, self.width)
+        out_op2 = FPNumIn(None, self.width)
         with m.If(self.trigger):
             m.d.comb += [
-                self.out_op1.decode(self.in_op1),
-                self.out_op2.decode(self.in_op2),
+                out_op1.decode(self.i.a),
+                out_op2.decode(self.i.b),
+                self.o.a.eq(out_op1),
+                self.o.b.eq(out_op2),
             ]
         return m
 
@@ -209,24 +217,20 @@ class FPGet2Op(FPState):
     """ gets operands
     """
 
-    def __init__(self, in_state, out_state, in_op1, in_op2, width):
+    def __init__(self, in_state, out_state, width, id_wid):
         FPState.__init__(self, in_state)
         self.out_state = out_state
-        self.mod = FPGet2OpMod(width)
-        self.in_op1 = in_op1
-        self.in_op2 = in_op2
-        self.out_op1 = FPNumIn(None, width)
-        self.out_op2 = FPNumIn(None, width)
+        self.mod = FPGet2OpMod(width, id_wid)
+        self.o = self.mod.ospec()
         self.in_stb = Signal(reset_less=True)
         self.out_ack = Signal(reset_less=True)
         self.out_decode = Signal(reset_less=True)
 
-    def setup(self, m, in_op1, in_op2, in_stb, in_ack):
+    def setup(self, m, i, in_stb, in_ack):
         """ links module to inputs and outputs
         """
         m.submodules.get_ops = self.mod
-        m.d.comb += self.mod.in_op1.eq(in_op1)
-        m.d.comb += self.mod.in_op2.eq(in_op2)
+        m.d.comb += self.mod.i.eq(i)
         m.d.comb += self.mod.stb.eq(in_stb)
         m.d.comb += self.out_ack.eq(self.mod.ack)
         m.d.comb += self.out_decode.eq(self.mod.trigger)
@@ -237,22 +241,21 @@ class FPGet2Op(FPState):
             m.next = self.out_state
             m.d.sync += [
                 self.mod.ack.eq(0),
-                #self.out_op1.v.eq(self.mod.out_op1.v),
-                #self.out_op2.v.eq(self.mod.out_op2.v),
-                self.out_op1.eq(self.mod.out_op1),
-                self.out_op2.eq(self.mod.out_op2)
+                self.o.eq(self.mod.o),
             ]
         with m.Else():
             m.d.sync += self.mod.ack.eq(1)
 
+
 class FPNumBase2Ops:
 
-    def __init__(self, width, m_extra=True):
+    def __init__(self, width, id_wid, m_extra=True):
         self.a = FPNumBase(width, m_extra)
         self.b = FPNumBase(width, m_extra)
+        self.mid = Signal(id_wid, reset_less=True)
 
     def eq(self, i):
-        return [self.a.eq(i.a), self.b.eq(i.b)]
+        return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 
 
 class FPAddSpecialCasesMod:
@@ -261,24 +264,24 @@ class FPAddSpecialCasesMod:
         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
     """
 
-    def __init__(self, width):
+    def __init__(self, width, id_wid):
         self.width = width
+        self.id_wid = id_wid
         self.i = self.ispec()
-        self.out_z = self.ospec()
+        self.o = self.ospec()
         self.out_do_z = Signal(reset_less=True)
 
     def ispec(self):
-        return FPNumBase2Ops(self.width)
+        return FPNumBase2Ops(self.width, self.id_wid)
 
     def ospec(self):
-        return FPNumOut(self.width, False)
+        return FPPackData(self.width, self.id_wid)
 
-    def setup(self, m, in_a, in_b, out_do_z):
+    def setup(self, m, i, out_do_z):
         """ links module to inputs and outputs
         """
         m.submodules.specialcases = self
-        m.d.comb += self.i.a.eq(in_a)
-        m.d.comb += self.i.b.eq(in_b)
+        m.d.comb += self.i.eq(i)
         m.d.comb += out_do_z.eq(self.out_do_z)
 
     def elaborate(self, platform):
@@ -286,7 +289,7 @@ class FPAddSpecialCasesMod:
 
         m.submodules.sc_in_a = self.i.a
         m.submodules.sc_in_b = self.i.b
-        m.submodules.sc_out_z = self.out_z
+        m.submodules.sc_out_z = self.o.z
 
         s_nomatch = Signal()
         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
@@ -297,7 +300,7 @@ class FPAddSpecialCasesMod:
         # if a is NaN or b is NaN return NaN
         with m.If(self.i.a.is_nan | self.i.b.is_nan):
             m.d.comb += self.out_do_z.eq(1)
-            m.d.comb += self.out_z.nan(0)
+            m.d.comb += self.o.z.nan(0)
 
         # XXX WEIRDNESS for FP16 non-canonical NaN handling
         # under review
@@ -325,39 +328,39 @@ class FPAddSpecialCasesMod:
         # if a is inf return inf (or NaN)
         with m.Elif(self.i.a.is_inf):
             m.d.comb += self.out_do_z.eq(1)
-            m.d.comb += self.out_z.inf(self.i.a.s)
+            m.d.comb += self.o.z.inf(self.i.a.s)
             # if a is inf and signs don't match return NaN
             with m.If(self.i.b.exp_128 & s_nomatch):
-                m.d.comb += self.out_z.nan(0)
+                m.d.comb += self.o.z.nan(0)
 
         # if b is inf return inf
         with m.Elif(self.i.b.is_inf):
             m.d.comb += self.out_do_z.eq(1)
-            m.d.comb += self.out_z.inf(self.i.b.s)
+            m.d.comb += self.o.z.inf(self.i.b.s)
 
         # if a is zero and b zero return signed-a/b
         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
             m.d.comb += self.out_do_z.eq(1)
-            m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
+            m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
                                           self.i.b.e,
                                           self.i.b.m[3:-1])
 
         # if a is zero return b
         with m.Elif(self.i.a.is_zero):
             m.d.comb += self.out_do_z.eq(1)
-            m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
+            m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
                                       self.i.b.m[3:-1])
 
         # if b is zero return a
         with m.Elif(self.i.b.is_zero):
             m.d.comb += self.out_do_z.eq(1)
-            m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
+            m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
                                       self.i.a.m[3:-1])
 
         # if a equal to -b return zero (+ve zero)
         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
             m.d.comb += self.out_do_z.eq(1)
-            m.d.comb += self.out_z.zero(0)
+            m.d.comb += self.o.z.zero(0)
 
         # Denormalised Number checks
         with m.Else():
@@ -419,25 +422,25 @@ class FPAddSpecialCasesDeNorm(FPState, FPID):
     def __init__(self, width, id_wid):
         FPState.__init__(self, "special_cases")
         FPID.__init__(self, id_wid)
-        self.smod = FPAddSpecialCasesMod(width)
+        self.smod = FPAddSpecialCasesMod(width, id_wid)
         self.out_z = self.smod.ospec()
         self.out_do_z = Signal(reset_less=True)
 
-        self.dmod = FPAddDeNormMod(width)
+        self.dmod = FPAddDeNormMod(width, id_wid)
         self.o = self.dmod.ospec()
 
-    def setup(self, m, in_a, in_b, in_mid):
+    def setup(self, m, i, in_mid):
         """ links module to inputs and outputs
         """
-        self.smod.setup(m, in_a, in_b, self.out_do_z)
-        self.dmod.setup(m, in_a, in_b)
+        self.smod.setup(m, i, self.out_do_z)
+        self.dmod.setup(m, i)
         if self.in_mid is not None:
             m.d.comb += self.in_mid.eq(in_mid)
 
     def action(self, m):
         self.idsync(m)
         with m.If(self.out_do_z):
-            m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
+            m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
             m.next = "put_z"
         with m.Else():
             m.next = "align"
@@ -447,23 +450,23 @@ class FPAddSpecialCasesDeNorm(FPState, FPID):
 
 class FPAddDeNormMod(FPState):
 
-    def __init__(self, width):
+    def __init__(self, width, id_wid):
         self.width = width
+        self.id_wid = id_wid
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPNumBase2Ops(self.width)
+        return FPNumBase2Ops(self.width, self.id_wid)
 
     def ospec(self):
-        return FPNumBase2Ops(self.width)
+        return FPNumBase2Ops(self.width, self.id_wid)
 
-    def setup(self, m, in_a, in_b):
+    def setup(self, m, i):
         """ links module to inputs and outputs
         """
         m.submodules.denormalise = self
-        m.d.comb += self.i.a.eq(in_a)
-        m.d.comb += self.i.b.eq(in_b)
+        m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):
         m = Module()
@@ -585,33 +588,34 @@ class FPAddAlignMulti(FPState, FPID):
 
 class FPNumIn2Ops:
 
-    def __init__(self, width):
+    def __init__(self, width, id_wid):
         self.a = FPNumIn(None, width)
         self.b = FPNumIn(None, width)
+        self.mid = Signal(id_wid, reset_less=True)
 
     def eq(self, i):
-        return [self.a.eq(i.a), self.b.eq(i.b)]
+        return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 
 
 class FPAddAlignSingleMod:
 
-    def __init__(self, width):
+    def __init__(self, width, id_wid):
         self.width = width
+        self.id_wid = id_wid
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPNumBase2Ops(self.width)
+        return FPNumBase2Ops(self.width, self.id_wid)
 
     def ospec(self):
-        return FPNumIn2Ops(self.width)
+        return FPNumIn2Ops(self.width, self.id_wid)
 
-    def setup(self, m, in_a, in_b):
+    def setup(self, m, i):
         """ links module to inputs and outputs
         """
         m.submodules.align = self
-        m.d.comb += self.i.a.eq(in_a)
-        m.d.comb += self.i.b.eq(in_b)
+        m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):
         """ Aligns A against B or B against A, depending on which has the
@@ -683,7 +687,7 @@ class FPAddAlignSingle(FPState, FPID):
     def __init__(self, width, id_wid):
         FPState.__init__(self, "align")
         FPID.__init__(self, id_wid)
-        self.mod = FPAddAlignSingleMod(width)
+        self.mod = FPAddAlignSingleMod(width, id_wid)
         self.out_a = FPNumIn(None, width)
         self.out_b = FPNumIn(None, width)
 
@@ -707,69 +711,72 @@ class FPAddAlignSingleAdd(FPState, FPID):
     def __init__(self, width, id_wid):
         FPState.__init__(self, "align")
         FPID.__init__(self, id_wid)
-        self.mod = FPAddAlignSingleMod(width)
-        self.o = self.mod.ospec()
+        self.width = width
+        self.id_wid = id_wid
+        self.a1o = self.ospec()
 
-        self.a0mod = FPAddStage0Mod(width)
-        self.a0_out_z = FPNumBase(width, False)
-        self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
-        self.a0_out_z = FPNumBase(width, False)
+    def ispec(self):
+        return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
 
-        self.a1mod = FPAddStage1Mod(width)
-        self.out_z = FPNumBase(width, False)
-        self.out_of = Overflow()
+    def ospec(self):
+        return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
 
-    def setup(self, m, in_a, in_b, in_mid):
+    def setup(self, m, i, in_mid):
         """ links module to inputs and outputs
         """
-        self.mod.setup(m, in_a, in_b)
-        m.d.comb += self.o.eq(self.mod.o)
+        mod = FPAddAlignSingleMod(self.width, self.id_wid)
+        mod.setup(m, i)
+        o = mod.ospec()
+        m.d.comb += o.eq(mod.o)
 
-        self.a0mod.setup(m, self.o.a, self.o.b)
-        m.d.comb += self.a0_out_z.eq(self.a0mod.o.z)
-        m.d.comb += self.out_tot.eq(self.a0mod.o.tot)
+        a0mod = FPAddStage0Mod(self.width, self.id_wid)
+        a0mod.setup(m, o)
+        a0o = a0mod.ospec()
+        m.d.comb += a0o.eq(a0mod.o)
 
-        self.a1mod.setup(m, self.out_tot, self.a0_out_z)
+        a1mod = FPAddStage1Mod(self.width, self.id_wid)
+        a1mod.setup(m, a0o)
+        self.a1modo = a1mod.o
 
         if self.in_mid is not None:
             m.d.comb += self.in_mid.eq(in_mid)
 
     def action(self, m):
         self.idsync(m)
-        m.d.sync += self.out_of.eq(self.a1mod.out_of)
-        m.d.sync += self.out_z.eq(self.a1mod.out_z)
+        m.d.sync += self.a1o.eq(self.a1modo)
         m.next = "normalise_1"
 
 
 class FPAddStage0Data:
 
-    def __init__(self, width):
+    def __init__(self, width, id_wid):
         self.z = FPNumBase(width, False)
         self.tot = Signal(self.z.m_width + 4, reset_less=True)
+        self.mid = Signal(id_wid, reset_less=True)
 
     def eq(self, i):
-        return [self.z.eq(i.z), self.tot.eq(i.tot)]
+        return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
 
 
 class FPAddStage0Mod:
 
-    def __init__(self, width):
+    def __init__(self, width, id_wid):
         self.width = width
+        self.id_wid = id_wid
         self.i = self.ispec()
         self.o = self.ospec()
 
     def ispec(self):
-        return FPNumBase2Ops(self.width)
+        return FPNumBase2Ops(self.width, self.id_wid)
 
     def ospec(self):
-        return FPAddStage0Data(self.width)
+        return FPAddStage0Data(self.width, self.id_wid)
 
-    def setup(self, m, in_a, in_b):
+    def setup(self, m, i):
         """ links module to inputs and outputs
         """
         m.submodules.add0 = self
-        m.d.comb += self.i.a.eq(in_a)
-        m.d.comb += self.i.b.eq(in_b)
+        m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):
         m = Module()
@@ -820,44 +827,58 @@ class FPAddStage0(FPState, FPID):
         FPState.__init__(self, "add_0")
         FPID.__init__(self, id_wid)
         self.mod = FPAddStage0Mod(width)
-        self.out_z = FPNumBase(width, False)
-        self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+        self.o = self.mod.ospec()
 
-    def setup(self, m, in_a, in_b, in_mid):
+    def setup(self, m, i, in_mid):
         """ links module to inputs and outputs
         """
-        self.mod.setup(m, in_a, in_b)
+        self.mod.setup(m, i)
         if self.in_mid is not None:
             m.d.comb += self.in_mid.eq(in_mid)
 
     def action(self, m):
         self.idsync(m)
         # NOTE: these could be done as combinatorial (merge add0+add1)
-        m.d.sync += self.out_z.eq(self.mod.out_z)
-        m.d.sync += self.out_tot.eq(self.mod.out_tot)
+        m.d.sync += self.o.eq(self.mod.o)
         m.next = "add_1"
 
 
+class FPAddStage1Data:
+
+    def __init__(self, width, id_wid):
+        self.z = FPNumBase(width, False)
+        self.of = Overflow()
+        self.mid = Signal(id_wid, reset_less=True)
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
+
+
+
 class FPAddStage1Mod(FPState):
     """ Second stage of add: preparation for normalisation.
         detects when tot sum is too big (tot[27] is kinda a carry bit)
     """
 
-    def __init__(self, width):
-        self.out_norm = Signal(reset_less=True)
-        self.in_z = FPNumBase(width, False)
-        self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
-        self.out_z = FPNumBase(width, False)
-        self.out_of = Overflow()
+    def __init__(self, width, id_wid):
+        self.width = width
+        self.id_wid = id_wid
+        self.i = self.ispec()
+        self.o = self.ospec()
+
+    def ispec(self):
+        return FPAddStage0Data(self.width, self.id_wid)
 
-    def setup(self, m, in_tot, in_z):
+    def ospec(self):
+        return FPAddStage1Data(self.width, self.id_wid)
+
+    def setup(self, m, i):
         """ links module to inputs and outputs
         """
         m.submodules.add1 = self
-        m.submodules.add1_out_overflow = self.out_of
+        m.submodules.add1_out_overflow = self.o.of
 
-        m.d.comb += self.in_z.eq(in_z)
-        m.d.comb += self.in_tot.eq(in_tot)
+        m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):
         m = Module()
@@ -865,25 +886,25 @@ class FPAddStage1Mod(FPState):
         #m.submodules.norm1_out_overflow = self.out_of
         #m.submodules.norm1_in_z = self.in_z
         #m.submodules.norm1_out_z = self.out_z
-        m.d.comb += self.out_z.eq(self.in_z)
+        m.d.comb += self.o.z.eq(self.i.z)
         # tot[-1] (MSB) gets set when the sum overflows. shift result down
-        with m.If(self.in_tot[-1]):
+        with m.If(self.i.tot[-1]):
             m.d.comb += [
-                self.out_z.m.eq(self.in_tot[4:]),
-                self.out_of.m0.eq(self.in_tot[4]),
-                self.out_of.guard.eq(self.in_tot[3]),
-                self.out_of.round_bit.eq(self.in_tot[2]),
-                self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
-                self.out_z.e.eq(self.in_z.e + 1)
+                self.o.z.m.eq(self.i.tot[4:]),
+                self.o.of.m0.eq(self.i.tot[4]),
+                self.o.of.guard.eq(self.i.tot[3]),
+                self.o.of.round_bit.eq(self.i.tot[2]),
+                self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
+                self.o.z.e.eq(self.i.z.e + 1)
         ]
         # tot[-1] (MSB) zero case
         with m.Else():
             m.d.comb += [
-                self.out_z.m.eq(self.in_tot[3:]),
-                self.out_of.m0.eq(self.in_tot[3]),
-                self.out_of.guard.eq(self.in_tot[2]),
-                self.out_of.round_bit.eq(self.in_tot[1]),
-                self.out_of.sticky.eq(self.in_tot[0])
+                self.o.z.m.eq(self.i.tot[3:]),
+                self.o.of.m0.eq(self.i.tot[3]),
+                self.o.of.guard.eq(self.i.tot[2]),
+                self.o.of.round_bit.eq(self.i.tot[1]),
+                self.o.of.sticky.eq(self.i.tot[0])
         ]
         return m
 
@@ -898,10 +919,10 @@ class FPAddStage1(FPState, FPID):
         self.out_of = Overflow()
         self.norm_stb = Signal()
 
-    def setup(self, m, in_tot, in_z, in_mid):
+    def setup(self, m, i, in_mid):
         """ links module to inputs and outputs
         """
-        self.mod.setup(m, in_tot, in_z)
+        self.mod.setup(m, i)
 
         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 
@@ -920,15 +941,20 @@ class FPNormaliseModSingle:
 
     def __init__(self, width):
         self.width = width
-        self.in_z = FPNumBase(width, False)
-        self.out_z = FPNumBase(width, False)
+        self.in_z = self.ispec()
+        self.out_z = self.ospec()
 
-    def setup(self, m, in_z, out_z, modname):
+    def ispec(self):
+        return FPNumBase(self.width, False)
+
+    def ospec(self):
+        return FPNumBase(self.width, False)
+
+    def setup(self, m, i):
         """ links module to inputs and outputs
         """
         m.submodules.normalise = self
-        m.d.comb += self.in_z.eq(in_z)
-        m.d.comb += out_z.eq(self.out_z)
+        m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):
         m = Module()
@@ -955,7 +981,7 @@ class FPNormaliseModSingle:
         # initialise out from in (overridden below)
         m.d.comb += self.out_z.eq(in_z)
         m.d.comb += self.out_of.eq(in_of)
-        # normalisation increase/decrease conditions
+        # normalisation decrease condition
         decrease = Signal(reset_less=True)
         m.d.comb += decrease.eq(in_z.m_msbzero)
         # decrease exponent
@@ -978,59 +1004,70 @@ class FPNormaliseModSingle:
 
         return m
 
+class FPNorm1Data:
+
+    def __init__(self, width, id_wid):
+        self.roundz = Signal(reset_less=True)
+        self.z = FPNumBase(width, False)
+        self.mid = Signal(id_wid, reset_less=True)
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
+
 
 class FPNorm1ModSingle:
 
-    def __init__(self, width):
+    def __init__(self, width, id_wid):
         self.width = width
-        self.out_norm = Signal(reset_less=True)
-        self.in_z = FPNumBase(width, False)
-        self.in_of = Overflow()
-        self.out_z = FPNumBase(width, False)
-        self.out_of = Overflow()
+        self.id_wid = id_wid
+        self.i = self.ispec()
+        self.o = self.ospec()
+
+    def ispec(self):
+        return FPAddStage1Data(self.width, self.id_wid)
+
+    def ospec(self):
+        return FPNorm1Data(self.width, self.id_wid)
 
-    def setup(self, m, in_z, in_of, out_z):
+    def setup(self, m, i):
         """ links module to inputs and outputs
         """
         m.submodules.normalise_1 = self
-
-        m.d.comb += self.in_z.eq(in_z)
-        m.d.comb += self.in_of.eq(in_of)
-
-        m.d.comb += out_z.eq(self.out_z)
+        m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):
         m = Module()
 
-        mwid = self.out_z.m_width+2
+        mwid = self.o.z.m_width+2
         pe = PriorityEncoder(mwid)
         m.submodules.norm_pe = pe
 
-        m.submodules.norm1_out_z = self.out_z
-        m.submodules.norm1_out_overflow = self.out_of
-        m.submodules.norm1_in_z = self.in_z
-        m.submodules.norm1_in_overflow = self.in_of
+        of = Overflow()
+        m.d.comb += self.o.roundz.eq(of.roundz)
 
-        in_z = FPNumBase(self.width, False)
-        in_of = Overflow()
-        m.submodules.norm1_insel_z = in_z
-        m.submodules.norm1_insel_overflow = in_of
+        m.submodules.norm1_out_z = self.o.z
+        m.submodules.norm1_out_overflow = of
+        m.submodules.norm1_in_z = self.i.z
+        m.submodules.norm1_in_overflow = self.i.of
 
-        espec = (len(in_z.e), True)
+        i = self.ispec()
+        m.submodules.norm1_insel_z = i.z
+        m.submodules.norm1_insel_overflow = i.of
+
+        espec = (len(i.z.e), True)
         ediff_n126 = Signal(espec, reset_less=True)
         msr = MultiShiftRMerge(mwid, espec)
         m.submodules.multishift_r = msr
 
-        m.d.comb += in_z.eq(self.in_z)
-        m.d.comb += in_of.eq(self.in_of)
+        m.d.comb += i.eq(self.i)
         # initialise out from in (overridden below)
-        m.d.comb += self.out_z.eq(in_z)
-        m.d.comb += self.out_of.eq(in_of)
+        m.d.comb += self.o.z.eq(i.z)
+        m.d.comb += of.eq(i.of)
         # normalisation increase/decrease conditions
         decrease = Signal(reset_less=True)
         increase = Signal(reset_less=True)
-        m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
-        m.d.comb += increase.eq(in_z.exp_lt_n126)
+        m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
+        m.d.comb += increase.eq(i.z.exp_lt_n126)
         # decrease exponent
         with m.If(decrease):
             # *sigh* not entirely obvious: count leading zeros (clz)
@@ -1038,41 +1075,41 @@ class FPNorm1ModSingle:
             # we reverse the order of the bits.
             temp_m = Signal(mwid, reset_less=True)
             temp_s = Signal(mwid+1, reset_less=True)
-            clz = Signal((len(in_z.e), True), reset_less=True)
+            clz = Signal((len(i.z.e), True), reset_less=True)
             # make sure that the amount to decrease by does NOT
             # go below the minimum non-INF/NaN exponent
-            limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
-                         in_z.exp_sub_n126)
+            limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
+                         i.z.exp_sub_n126)
             m.d.comb += [
                 # cat round and guard bits back into the mantissa
-                temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
+                temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
                 pe.i.eq(temp_m[::-1]),          # inverted
                 clz.eq(limclz),                 # count zeros from MSB down
                 temp_s.eq(temp_m << clz),       # shift mantissa UP
-                self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
-                self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
-                self.out_of.m0.eq(temp_s[2]),   # copy of mantissa[0]
+                self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
+                self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
+                of.m0.eq(temp_s[2]),          # copy of mantissa[0]
                 # overflow in bits 0..1: got shifted too (leave sticky)
-                self.out_of.guard.eq(temp_s[1]),     # guard
-                self.out_of.round_bit.eq(temp_s[0]), # round
+                of.guard.eq(temp_s[1]),       # guard
+                of.round_bit.eq(temp_s[0]),   # round
             ]
         # increase exponent
         with m.Elif(increase):
             temp_m = Signal(mwid+1, reset_less=True)
             m.d.comb += [
-                temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
-                              in_z.m)),
-                ediff_n126.eq(in_z.N126 - in_z.e),
+                temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
+                              i.z.m)),
+                ediff_n126.eq(i.z.N126 - i.z.e),
                 # connect multi-shifter to inp/out mantissa (and ediff)
                 msr.inp.eq(temp_m),
                 msr.diff.eq(ediff_n126),
-                self.out_z.m.eq(msr.m[3:]),
-                self.out_of.m0.eq(temp_s[3]),   # copy of mantissa[0]
+                self.o.z.m.eq(msr.m[3:]),
+                of.m0.eq(temp_s[3]),   # copy of mantissa[0]
                 # overflow in bits 0..1: got shifted too (leave sticky)
-                self.out_of.guard.eq(temp_s[2]),     # guard
-                self.out_of.round_bit.eq(temp_s[1]), # round
-                self.out_of.sticky.eq(temp_s[0]), # sticky
-                self.out_z.e.eq(in_z.e + ediff_n126),
+                of.guard.eq(temp_s[2]),     # guard
+                of.round_bit.eq(temp_s[1]), # round
+                of.sticky.eq(temp_s[0]),    # sticky
+                self.o.z.e.eq(i.z.e + ediff_n126),
             ]
 
         return m
@@ -1083,7 +1120,6 @@ class FPNorm1ModMulti:
     def __init__(self, width, single_cycle=True):
         self.width = width
         self.in_select = Signal(reset_less=True)
-        self.out_norm = Signal(reset_less=True)
         self.in_z = FPNumBase(width, False)
         self.in_of = Overflow()
         self.temp_z = FPNumBase(width, False)
@@ -1152,14 +1188,13 @@ class FPNorm1Single(FPState, FPID):
         FPID.__init__(self, id_wid)
         FPState.__init__(self, "normalise_1")
         self.mod = FPNorm1ModSingle(width)
-        self.out_norm = Signal(reset_less=True)
-        self.out_z = FPNumBase(width)
+        self.out_z = FPNumBase(width, False)
         self.out_roundz = Signal(reset_less=True)
 
-    def setup(self, m, in_z, in_of, in_mid):
+    def setup(self, m, i, in_mid):
         """ links module to inputs and outputs
         """
-        self.mod.setup(m, in_z, in_of, self.out_z)
+        self.mod.setup(m, i, self.out_z)
 
         if self.in_mid is not None:
             m.d.comb += self.in_mid.eq(in_mid)
@@ -1222,35 +1257,41 @@ class FPNormToPack(FPState, FPID):
     def __init__(self, width, id_wid):
         FPID.__init__(self, id_wid)
         FPState.__init__(self, "normalise_1")
+        self.id_wid = id_wid
         self.width = width
 
-    def setup(self, m, in_z, in_of, in_mid):
+    def ispec(self):
+        return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
+
+    def ospec(self):
+        return FPPackData(self.width, self.id_wid) # FPPackMod ospec
+
+    def setup(self, m, i, in_mid):
         """ links module to inputs and outputs
         """
 
         # Normalisation (chained to input in_z+in_of)
-        nmod = FPNorm1ModSingle(self.width)
-        n_out_z = FPNumBase(self.width)
-        n_out_roundz = Signal(reset_less=True)
-        nmod.setup(m, in_z, in_of, n_out_z)
+        nmod = FPNorm1ModSingle(self.width, self.id_wid)
+        nmod.setup(m, i)
+        n_out = nmod.ospec()
+        m.d.comb += n_out.eq(nmod.o)
 
         # Rounding (chained to normalisation)
-        rmod = FPRoundMod(self.width)
-        r_out_z = FPNumBase(self.width)
-        rmod.setup(m, n_out_z, n_out_roundz)
-        m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
+        rmod = FPRoundMod(self.width, self.id_wid)
+        rmod.setup(m, n_out)
+        r_out_z = rmod.ospec()
         m.d.comb += r_out_z.eq(rmod.out_z)
 
         # Corrections (chained to rounding)
-        cmod = FPCorrectionsMod(self.width)
-        c_out_z = FPNumBase(self.width)
+        cmod = FPCorrectionsMod(self.width, self.id_wid)
         cmod.setup(m, r_out_z)
+        c_out_z = cmod.ospec()
         m.d.comb += c_out_z.eq(cmod.out_z)
 
         # Pack (chained to corrections)
-        self.pmod = FPPackMod(self.width)
-        self.out_z = FPNumBase(self.width)
+        self.pmod = FPPackMod(self.width, self.id_wid)
         self.pmod.setup(m, c_out_z)
+        self.out_z = self.pmod.ospec()
 
         # Multiplex ID
         if self.in_mid is not None:
@@ -1258,30 +1299,45 @@ class FPNormToPack(FPState, FPID):
 
     def action(self, m):
         self.idsync(m) # copies incoming ID to outgoing
-        m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
+        m.d.sync += self.out_z.z.v.eq(self.pmod.o.z.v) # outputs packed result
         m.next = "pack_put_z"
 
 
+class FPRoundData:
+
+    def __init__(self, width, id_wid):
+        self.z = FPNumBase(width, False)
+        self.mid = Signal(id_wid, reset_less=True)
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.mid.eq(i.mid)]
+
+
 class FPRoundMod:
 
-    def __init__(self, width):
-        self.in_roundz = Signal(reset_less=True)
-        self.in_z = FPNumBase(width, False)
-        self.out_z = FPNumBase(width, False)
+    def __init__(self, width, id_wid):
+        self.width = width
+        self.id_wid = id_wid
+        self.i = self.ispec()
+        self.out_z = self.ospec()
 
-    def setup(self, m, in_z, roundz):
-        m.submodules.roundz = self
+    def ispec(self):
+        return FPNorm1Data(self.width, self.id_wid)
 
-        m.d.comb += self.in_z.eq(in_z)
-        m.d.comb += self.in_roundz.eq(roundz)
+    def ospec(self):
+        return FPRoundData(self.width, self.id_wid)
+
+    def setup(self, m, i):
+        m.submodules.roundz = self
+        m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.out_z.eq(self.in_z)
-        with m.If(self.in_roundz):
-            m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
-            with m.If(self.in_z.m == self.in_z.m1s): # all 1s
-                m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
+        m.d.comb += self.out_z.eq(self.i)
+        with m.If(self.i.roundz):
+            m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
+            with m.If(self.i.z.m == self.i.z.m1s): # all 1s
+                m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
         return m
 
 
@@ -1291,12 +1347,18 @@ class FPRound(FPState, FPID):
         FPState.__init__(self, "round")
         FPID.__init__(self, id_wid)
         self.mod = FPRoundMod(width)
-        self.out_z = FPNumBase(width)
+        self.out_z = self.ospec()
+
+    def ispec(self):
+        return self.mod.ispec()
 
-    def setup(self, m, in_z, roundz, in_mid):
+    def ospec(self):
+        return self.mod.ospec()
+
+    def setup(self, m, i, in_mid):
         """ links module to inputs and outputs
         """
-        self.mod.setup(m, in_z, roundz)
+        self.mod.setup(m, i)
 
         if self.in_mid is not None:
             m.d.comb += self.in_mid.eq(in_mid)
@@ -1309,23 +1371,31 @@ class FPRound(FPState, FPID):
 
 class FPCorrectionsMod:
 
-    def __init__(self, width):
-        self.in_z = FPNumOut(width, False)
-        self.out_z = FPNumOut(width, False)
+    def __init__(self, width, id_wid):
+        self.width = width
+        self.id_wid = id_wid
+        self.i = self.ispec()
+        self.out_z = self.ospec()
 
-    def setup(self, m, in_z):
+    def ispec(self):
+        return FPRoundData(self.width, self.id_wid)
+
+    def ospec(self):
+        return FPRoundData(self.width, self.id_wid)
+
+    def setup(self, m, i):
         """ links module to inputs and outputs
         """
         m.submodules.corrections = self
-        m.d.comb += self.in_z.eq(in_z)
+        m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.corr_in_z = self.in_z
-        m.submodules.corr_out_z = self.out_z
-        m.d.comb += self.out_z.eq(self.in_z)
-        with m.If(self.in_z.is_denormalised):
-            m.d.comb += self.out_z.e.eq(self.in_z.N127)
+        m.submodules.corr_in_z = self.i.z
+        m.submodules.corr_out_z = self.out_z.z
+        m.d.comb += self.out_z.eq(self.i)
+        with m.If(self.i.z.is_denormalised):
+            m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
         return m
 
 
@@ -1335,7 +1405,13 @@ class FPCorrections(FPState, FPID):
         FPState.__init__(self, "corrections")
         FPID.__init__(self, id_wid)
         self.mod = FPCorrectionsMod(width)
-        self.out_z = FPNumBase(width)
+        self.out_z = self.ospec()
+
+    def ispec(self):
+        return self.mod.ispec()
+
+    def ospec(self):
+        return self.mod.ospec()
 
     def setup(self, m, in_z, in_mid):
         """ links module to inputs and outputs
@@ -1350,35 +1426,68 @@ class FPCorrections(FPState, FPID):
         m.next = "pack"
 
 
+class FPPackData:
+
+    def __init__(self, width, id_wid):
+        self.z = FPNumOut(width, False)
+        self.mid = Signal(id_wid, reset_less=True)
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.mid.eq(i.mid)]
+
+
 class FPPackMod:
 
-    def __init__(self, width):
-        self.in_z = FPNumOut(width, False)
-        self.out_z = FPNumOut(width, False)
+    def __init__(self, width, id_wid):
+        self.width = width
+        self.id_wid = id_wid
+        self.i = self.ispec()
+        self.o = self.ospec()
+
+    def ispec(self):
+        return FPRoundData(self.width, self.id_wid)
+
+    def ospec(self):
+        return FPPackData(self.width, self.id_wid)
 
     def setup(self, m, in_z):
         """ links module to inputs and outputs
         """
         m.submodules.pack = self
-        m.d.comb += self.in_z.eq(in_z)
+        m.d.comb += self.i.eq(in_z)
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.pack_in_z = self.in_z
-        with m.If(self.in_z.is_overflowed):
-            m.d.comb += self.out_z.inf(self.in_z.s)
+        m.submodules.pack_in_z = self.i.z
+        with m.If(self.i.z.is_overflowed):
+            m.d.comb += self.o.z.inf(self.i.z.s)
         with m.Else():
-            m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
+            m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
         return m
 
 
+class FPPackData:
+    def __init__(self, width, id_wid):
+        self.z = FPNumOut(width, False)
+        self.mid = Signal(id_wid, reset_less=True)
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.mid.eq(i.mid)]
+
+
 class FPPack(FPState, FPID):
 
     def __init__(self, width, id_wid):
         FPState.__init__(self, "pack")
         FPID.__init__(self, id_wid)
         self.mod = FPPackMod(width)
-        self.out_z = FPNumOut(width, False)
+        self.out_z = self.ospec()
+
+    def ispec(self):
+        return self.mod.ispec()
+
+    def ospec(self):
+        return self.mod.ospec()
 
     def setup(self, m, in_z, in_mid):
         """ links module to inputs and outputs
@@ -1409,13 +1518,13 @@ class FPPutZ(FPState):
         if self.in_mid is not None:
             m.d.sync += self.out_mid.eq(self.in_mid)
         m.d.sync += [
-          self.out_z.v.eq(self.in_z.v)
+          self.out_z.z.v.eq(self.in_z.v)
         ]
-        with m.If(self.out_z.stb & self.out_z.ack):
-            m.d.sync += self.out_z.stb.eq(0)
+        with m.If(self.out_z.z.stb & self.out_z.z.ack):
+            m.d.sync += self.out_z.z.stb.eq(0)
             m.next = self.to_state
         with m.Else():
-            m.d.sync += self.out_z.stb.eq(1)
+            m.d.sync += self.out_z.z.stb.eq(1)
 
 
 class FPPutZIdx(FPState):
@@ -1444,6 +1553,27 @@ class FPPutZIdx(FPState):
         with m.Else():
             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
 
+class FPADDBaseData:
+
+    def __init__(self, width, id_wid):
+        self.width = width
+        self.id_wid = id_wid
+        self.a  = Signal(width)
+        self.b  = Signal(width)
+        self.mid = Signal(id_wid, reset_less=True)
+
+    def eq(self, i):
+        return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
+
+
+class FPOpData:
+    def __init__(self, width, id_wid):
+        self.z = FPOp(width)
+        self.mid = Signal(id_wid, reset_less=True)
+
+    def eq(self, i):
+        return [self.z.eq(i.z), self.mid.eq(i.mid)]
+
 
 class FPADDBaseMod(FPID):
 
@@ -1457,16 +1587,22 @@ class FPADDBaseMod(FPID):
         """
         FPID.__init__(self, id_wid)
         self.width = width
+        self.id_wid = id_wid
         self.single_cycle = single_cycle
         self.compact = compact
 
         self.in_t = Trigger()
-        self.in_a  = Signal(width)
-        self.in_b  = Signal(width)
-        self.out_z = FPOp(width)
+        self.i = self.ispec()
+        self.o = self.ospec()
 
         self.states = []
 
+    def ispec(self):
+        return FPADDBaseData(self.width, self.id_wid)
+
+    def ospec(self):
+        return FPOpData(self.width, self.id_wid)
+
     def add_state(self, state):
         self.states.append(state)
         return state
@@ -1475,7 +1611,7 @@ class FPADDBaseMod(FPID):
         """ creates the HDL code-fragment for FPAdd
         """
         m = Module()
-        m.submodules.out_z = self.out_z
+        m.submodules.out_z = self.o.z
         m.submodules.in_t = self.in_t
         if self.compact:
             self.get_compact_fragment(m, platform)
@@ -1493,8 +1629,8 @@ class FPADDBaseMod(FPID):
     def get_longer_fragment(self, m, platform=None):
 
         get = self.add_state(FPGet2Op("get_ops", "special_cases",
-                                      self.in_a, self.in_b, self.width))
-        get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
+                                      self.width))
+        get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
         a = get.out_op1
         b = get.out_op2
 
@@ -1542,24 +1678,22 @@ class FPADDBaseMod(FPID):
     def get_compact_fragment(self, m, platform=None):
 
         get = self.add_state(FPGet2Op("get_ops", "special_cases",
-                                      self.in_a, self.in_b, self.width))
-        get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
-        a = get.out_op1
-        b = get.out_op2
+                                      self.width, self.id_wid))
+        get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
 
         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
-        sc.setup(m, a, b, self.in_mid)
+        sc.setup(m, get.o, self.in_mid)
 
         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
-        alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
+        alm.setup(m, sc.o, sc.in_mid)
 
         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
-        n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
+        n1.setup(m, alm.a1o, alm.in_mid)
 
-        ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
+        ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
                                     n1.in_mid, self.out_mid))
 
-        pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
+        pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
                                     sc.in_mid, self.out_mid))
 
 
@@ -1577,39 +1711,40 @@ class FPADDBase(FPState, FPID):
         self.width = width
         self.single_cycle = single_cycle
         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
+        self.o = self.ospec()
 
         self.in_t = Trigger()
-        self.in_a  = Signal(width)
-        self.in_b  = Signal(width)
-        #self.out_z = FPOp(width)
+        self.i = self.ispec()
 
         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
         self.in_accept = Signal(reset_less=True)
         self.add_stb = Signal(reset_less=True)
         self.add_ack = Signal(reset=0, reset_less=True)
 
-    def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
-        self.out_z = out_z
-        self.out_mid = out_mid
-        m.d.comb += [self.in_a.eq(a),
-                     self.in_b.eq(b),
-                     self.mod.in_a.eq(self.in_a),
-                     self.mod.in_b.eq(self.in_b),
+    def ispec(self):
+        return self.mod.ispec()
+
+    def ospec(self):
+        return self.mod.ospec()
+
+    def setup(self, m, i, add_stb, in_mid):
+        m.d.comb += [self.i.eq(i),
+                     self.mod.i.eq(self.i),
                      self.in_mid.eq(in_mid),
                      self.mod.in_mid.eq(self.in_mid),
-                     self.z_done.eq(self.mod.out_z.trigger),
+                     self.z_done.eq(self.mod.o.z.trigger),
                      #self.add_stb.eq(add_stb),
                      self.mod.in_t.stb.eq(self.in_t.stb),
                      self.in_t.ack.eq(self.mod.in_t.ack),
-                     self.out_mid.eq(self.mod.out_mid),
-                     self.out_z.v.eq(self.mod.out_z.v),
-                     self.out_z.stb.eq(self.mod.out_z.stb),
-                     self.mod.out_z.ack.eq(self.out_z.ack),
+                     self.o.mid.eq(self.mod.o.mid),
+                     self.o.z.v.eq(self.mod.o.z.v),
+                     self.o.z.stb.eq(self.mod.o.z.stb),
+                     self.mod.o.z.ack.eq(self.o.z.ack),
                     ]
 
         m.d.sync += self.add_stb.eq(add_stb)
         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
-        m.d.sync += self.out_z.ack.eq(0) # likewise
+        m.d.sync += self.o.z.ack.eq(0) # likewise
         #m.d.sync += self.in_t.stb.eq(0)
 
         m.submodules.fpadd = self.mod
@@ -1631,7 +1766,7 @@ class FPADDBase(FPState, FPID):
             with m.Else():
                 m.d.sync += [self.add_ack.eq(0),
                              self.in_t.stb.eq(0),
-                             self.out_z.ack.eq(1),
+                             self.o.z.ack.eq(1),
                             ]
         with m.Else():
             # done: acknowledge, and write out id and value
@@ -1655,6 +1790,7 @@ class FPADDBase(FPState, FPID):
             with m.Else():
                 m.d.sync += self.out_z.stb.eq(1)
 
+
 class ResArray:
     def __init__(self, width, id_wid):
         self.width = width
@@ -1750,10 +1886,6 @@ class FPADD(FPID):
         in_a = self.rs[0][0]
         in_b = self.rs[0][1]
 
-        out_z = FPOp(self.width)
-        out_mid = Signal(self.id_wid, reset_less=True)
-        m.submodules.out_z = out_z
-
         geta = self.add_state(FPGetOp("get_a", "get_b",
                                       in_a, self.width))
         geta.setup(m, in_a)
@@ -1766,11 +1898,13 @@ class FPADD(FPID):
 
         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
         ab = self.add_state(ab)
-        ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
-                 out_z, out_mid)
+        abd = ab.ispec() # create an input spec object for FPADDBase
+        m.d.sync += [abd.a.eq(a), abd.b.eq(b), abd.mid.eq(self.ids.in_mid)]
+        ab.setup(m, abd, getb.out_decode, self.ids.in_mid)
+        o = ab.o
 
-        pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
-                                    out_mid, "get_a"))
+        pz = self.add_state(FPPutZIdx("put_z", o.z, self.res,
+                                    o.mid, "get_a"))
 
         with m.FSM() as fsm: