X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Fnmigen_add_experiment.py;h=fc1735d75d3a54a2afd2dcab78105ccac321eb2c;hb=3e074b3bc5123a3d615379d56c4d18874dbf3576;hp=5f4642c4b8d1e2985b99d9f60256bcd885f36af4;hpb=80580ea474b77c136f7e588e8dc673407e56a99d;p=ieee754fpu.git

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 5f4642c4..a036a4c3 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -3,619 +3,893 @@
 # 2013-12-12
 
 from nmigen import Module, Signal, Cat
-from nmigen.cli import main
+from nmigen.cli import main, verilog
 
+from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
 
-class FPNum:
-    """ Floating-point Number Class, variable-width TODO (currently 32-bit)
 
-        Contains signals for an incoming copy of the value, decoded into
-        sign / exponent / mantissa.
-        Also contains encoding functions, creation and recognition of
-        zero, NaN and inf (all signed)
+class FPState(FPBase):
+    def __init__(self, state_from):
+        self.state_from = state_from
 
-        Four extra bits are included in the mantissa: the top bit
-        (m[-1]) is effectively a carry-overflow.  The other three are
-        guard (m[2]), round (m[1]), and sticky (m[0])
-    """
-    def __init__(self, width, m_width=None):
-        self.width = width
-        if m_width is None:
-            m_width = width - 5 # mantissa extra bits (top,guard,round)
-        self.v = Signal(width)      # Latched copy of value
-        self.m = Signal(m_width)    # Mantissa
-        self.e = Signal((10, True)) # Exponent: 10 bits, signed
-        self.s = Signal()           # Sign bit
+    def set_inputs(self, inputs):
+        self.inputs = inputs
+        for k,v in inputs.items():
+            setattr(self, k, v)
+
+    def set_outputs(self, outputs):
+        self.outputs = outputs
+        for k,v in outputs.items():
+            setattr(self, k, v)
 
-    def decode(self):
-        """ decodes a latched value into sign / exponent / mantissa
 
-            bias is subtracted here, from the exponent.
+class FPGetOpMod:
+    def __init__(self, width):
+        self.in_op = FPOp(width)
+        self.out_op = FPNumIn(self.in_op, width)
+        self.out_decode = Signal(reset_less=True)
+
+    def setup(self, m, in_op, out_op, out_decode):
+        """ links module to inputs and outputs
         """
-        v = self.v
-        return [self.m.eq(Cat(0, 0, 0, v[0:23])), # mantissa
-                self.e.eq(Cat(v[23:31]) - 127),   # exponent (take off bias)
-                self.s.eq(Cat(v[31])),            # sign
-                ]
+        m.d.comb += self.in_op.copy(in_op)
+        m.d.comb += out_op.v.eq(self.out_op.v)
+        m.d.comb += out_decode.eq(self.out_decode)
 
-    def create(self, s, e, m):
-        """ creates a value from sign / exponent / mantissa
+    def elaborate(self, platform):
+        m = Module()
+        m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
+        #m.submodules.get_op_in = self.in_op
+        m.submodules.get_op_out = self.out_op
+        with m.If(self.out_decode):
+            m.d.comb += [
+                self.out_op.decode(self.in_op.v),
+            ]
+        return m
+
+
+class FPGetOp(FPState):
+    """ gets operand
+    """
 
-            bias is added here, to the exponent
+    def __init__(self, in_state, out_state, in_op, width):
+        FPState.__init__(self, in_state)
+        self.out_state = out_state
+        self.mod = FPGetOpMod(width)
+        self.in_op = in_op
+        self.out_op = FPNumIn(in_op, width)
+        self.out_decode = Signal(reset_less=True)
+
+    def action(self, m):
+        with m.If(self.out_decode):
+            m.next = self.out_state
+            m.d.sync += [
+                self.in_op.ack.eq(0),
+                self.out_op.copy(self.mod.out_op)
+            ]
+        with m.Else():
+            m.d.sync += self.in_op.ack.eq(1)
+
+
+class FPGetOpB(FPState):
+    """ gets operand b
+    """
+
+    def __init__(self, in_b, width):
+        FPState.__init__(self, "get_b")
+        self.in_b = in_b
+        self.b = FPNumIn(self.in_b, width)
+
+    def action(self, m):
+        self.get_op(m, self.in_b, self.b, "special_cases")
+
+
+class FPAddSpecialCasesMod:
+    """ special cases: NaNs, infs, zeros, denormalised
+        NOTE: some of these are unique to add.  see "Special Operations"
+        https://steve.hollasch.net/cgindex/coding/ieeefloat.html
+    """
+
+    def __init__(self, width):
+        self.in_a = FPNumBase(width)
+        self.in_b = FPNumBase(width)
+        self.out_z = FPNumOut(width, False)
+        self.out_do_z = Signal(reset_less=True)
+
+    def setup(self, m, in_a, in_b, out_z, out_do_z):
+        """ links module to inputs and outputs
         """
-        return [
-          self.v[31].eq(s),          # sign
-          self.v[23:31].eq(e + 127), # exp (add on bias)
-          self.v[0:23].eq(m)         # mantissa
-        ]
+        m.d.comb += self.in_a.copy(in_a)
+        m.d.comb += self.in_b.copy(in_b)
+        m.d.comb += out_z.v.eq(self.out_z.v)
+        m.d.comb += out_do_z.eq(self.out_do_z)
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.submodules.sc_in_a = self.in_a
+        m.submodules.sc_in_b = self.in_b
+        m.submodules.sc_out_z = self.out_z
+
+        s_nomatch = Signal()
+        m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
+
+        m_match = Signal()
+        m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
+
+        # if a is NaN or b is NaN return NaN
+        with m.If(self.in_a.is_nan | self.in_b.is_nan):
+            m.d.comb += self.out_do_z.eq(1)
+            m.d.comb += self.out_z.nan(0)
+
+        # XXX WEIRDNESS for FP16 non-canonical NaN handling
+        # under review
+
+        ## if a is zero and b is NaN return -b
+        #with m.If(a.is_zero & (a.s==0) & b.is_nan):
+        #    m.d.comb += self.out_do_z.eq(1)
+        #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
+
+        ## if b is zero and a is NaN return -a
+        #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
+        #    m.d.comb += self.out_do_z.eq(1)
+        #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
+
+        ## if a is -zero and b is NaN return -b
+        #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
+        #    m.d.comb += self.out_do_z.eq(1)
+        #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
+
+        ## if b is -zero and a is NaN return -a
+        #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
+        #    m.d.comb += self.out_do_z.eq(1)
+        #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
+
+        # if a is inf return inf (or NaN)
+        with m.Elif(self.in_a.is_inf):
+            m.d.comb += self.out_do_z.eq(1)
+            m.d.comb += self.out_z.inf(self.in_a.s)
+            # if a is inf and signs don't match return NaN
+            with m.If(self.in_b.exp_128 & s_nomatch):
+                m.d.comb += self.out_z.nan(0)
+
+        # if b is inf return inf
+        with m.Elif(self.in_b.is_inf):
+            m.d.comb += self.out_do_z.eq(1)
+            m.d.comb += self.out_z.inf(self.in_b.s)
+
+        # if a is zero and b zero return signed-a/b
+        with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
+            m.d.comb += self.out_do_z.eq(1)
+            m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
+                                          self.in_b.e,
+                                          self.in_b.m[3:-1])
+
+        # if a is zero return b
+        with m.Elif(self.in_a.is_zero):
+            m.d.comb += self.out_do_z.eq(1)
+            m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
+                                      self.in_b.m[3:-1])
+
+        # if b is zero return a
+        with m.Elif(self.in_b.is_zero):
+            m.d.comb += self.out_do_z.eq(1)
+            m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
+                                      self.in_a.m[3:-1])
+
+        # if a equal to -b return zero (+ve zero)
+        with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
+            m.d.comb += self.out_do_z.eq(1)
+            m.d.comb += self.out_z.zero(0)
+
+        # Denormalised Number checks
+        with m.Else():
+            m.d.comb += self.out_do_z.eq(0)
+
+        return m
+
+
+class FPAddSpecialCases(FPState):
+    """ special cases: NaNs, infs, zeros, denormalised
+        NOTE: some of these are unique to add.  see "Special Operations"
+        https://steve.hollasch.net/cgindex/coding/ieeefloat.html
+    """
+
+    def __init__(self, width):
+        FPState.__init__(self, "special_cases")
+        self.mod = FPAddSpecialCasesMod(width)
+        self.out_z = FPNumOut(width, False)
+        self.out_do_z = Signal(reset_less=True)
+
+    def action(self, m):
+        with m.If(self.out_do_z):
+            m.d.sync += self.z.v.eq(self.out_z.v) # only take the output
+            m.next = "put_z"
+        with m.Else():
+            m.next = "denormalise"
+
 
-    def shift_down(self):
-        """ shifts a mantissa down by one. exponent is increased to compensate
+class FPAddDeNormMod(FPState):
 
-            accuracy is lost as a result in the mantissa however there are 3
-            guard bits (the latter of which is the "sticky" bit)
+    def __init__(self, width):
+        self.in_a = FPNumBase(width)
+        self.in_b = FPNumBase(width)
+        self.out_a = FPNumBase(width)
+        self.out_b = FPNumBase(width)
+
+    def setup(self, m, in_a, in_b, out_a, out_b):
+        """ links module to inputs and outputs
         """
-        return self.create(self.s,
-                           self.e + 1,
-                           Cat(self.m[0] | self.m[1], self.m[1:-5], 0))
+        m.d.comb += self.in_a.copy(in_a)
+        m.d.comb += self.in_b.copy(in_b)
+        m.d.comb += out_a.copy(self.out_a)
+        m.d.comb += out_b.copy(self.out_b)
 
-    def nan(self, s):
-        return self.create(s, 0x80, 1<<22)
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.denorm_in_a = self.in_a
+        m.submodules.denorm_in_b = self.in_b
+        m.submodules.denorm_out_a = self.out_a
+        m.submodules.denorm_out_b = self.out_b
+        # hmmm, don't like repeating identical code
+        m.d.comb += self.out_a.copy(self.in_a)
+        with m.If(self.in_a.exp_n127):
+            m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
+        with m.Else():
+            m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
+
+        m.d.comb += self.out_b.copy(self.in_b)
+        with m.If(self.in_b.exp_n127):
+            m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
+        with m.Else():
+            m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 
-    def inf(self, s):
-        return self.create(s, 0x80, 0)
+        return m
 
-    def zero(self, s):
-        return self.create(s, -127, 0)
 
-    def is_nan(self):
-        return (self.e == 128) & (self.m != 0)
+class FPAddDeNorm(FPState):
 
-    def is_inf(self):
-        return (self.e == 128) & (self.m == 0)
+    def __init__(self, width):
+        FPState.__init__(self, "denormalise")
+        self.mod = FPAddDeNormMod(width)
+        self.out_a = FPNumBase(width)
+        self.out_b = FPNumBase(width)
 
-    def is_zero(self):
-        return (self.e == -127) & (self.m == 0)
+    def action(self, m):
+        # Denormalised Number checks
+        m.next = "align"
+        m.d.sync += self.a.copy(self.out_a)
+        m.d.sync += self.b.copy(self.out_b)
 
 
-class FPADD:
+class FPAddAlignMultiMod(FPState):
+
     def __init__(self, width):
-        self.width = width
+        self.in_a = FPNumBase(width)
+        self.in_b = FPNumBase(width)
+        self.out_a = FPNumIn(None, width)
+        self.out_b = FPNumIn(None, width)
+        self.exp_eq = Signal(reset_less=True)
+
+    def setup(self, m, in_a, in_b, out_a, out_b, exp_eq):
+        """ links module to inputs and outputs
+        """
+        m.d.comb += self.in_a.copy(in_a)
+        m.d.comb += self.in_b.copy(in_b)
+        m.d.comb += out_a.copy(self.out_a)
+        m.d.comb += out_b.copy(self.out_b)
+        m.d.comb += exp_eq.eq(self.exp_eq)
+
+    def elaborate(self, platform):
+        # This one however (single-cycle) will do the shift
+        # in one go.
+
+        m = Module()
+
+        #m.submodules.align_in_a = self.in_a
+        #m.submodules.align_in_b = self.in_b
+        m.submodules.align_out_a = self.out_a
+        m.submodules.align_out_b = self.out_b
+
+        # NOTE: this does *not* do single-cycle multi-shifting,
+        #       it *STAYS* in the align state until exponents match
+
+        # exponent of a greater than b: shift b down
+        m.d.comb += self.exp_eq.eq(0)
+        m.d.comb += self.out_a.copy(self.in_a)
+        m.d.comb += self.out_b.copy(self.in_b)
+        agtb = Signal(reset_less=True)
+        altb = Signal(reset_less=True)
+        m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
+        m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
+        with m.If(agtb):
+            m.d.comb += self.out_b.shift_down(self.in_b)
+        # exponent of b greater than a: shift a down
+        with m.Elif(altb):
+            m.d.comb += self.out_a.shift_down(self.in_a)
+        # exponents equal: move to next stage.
+        with m.Else():
+            m.d.comb += self.exp_eq.eq(1)
+        return m
 
-        self.in_a     = Signal(width)
-        self.in_a_stb = Signal()
-        self.in_a_ack = Signal()
 
-        self.in_b     = Signal(width)
-        self.in_b_stb = Signal()
-        self.in_b_ack = Signal()
+class FPAddAlignMulti(FPState):
+
+    def __init__(self, width):
+        FPState.__init__(self, "align")
+        self.mod = FPAddAlignMultiMod(width)
+        self.out_a = FPNumIn(None, width)
+        self.out_b = FPNumIn(None, width)
+        self.exp_eq = Signal(reset_less=True)
+
+    def action(self, m):
+        m.d.sync += self.a.copy(self.out_a)
+        m.d.sync += self.b.copy(self.out_b)
+        with m.If(self.exp_eq):
+            m.next = "add_0"
 
-        self.out_z     = Signal(width)
-        self.out_z_stb = Signal()
-        self.out_z_ack = Signal()
 
-    def get_fragment(self, platform):
+class FPAddAlignSingleMod:
+
+    def __init__(self, width):
+        self.in_a = FPNumBase(width)
+        self.in_b = FPNumBase(width)
+        self.out_a = FPNumIn(None, width)
+        self.out_b = FPNumIn(None, width)
+        #self.out_a = FPNumBase(width)
+        #self.out_b = FPNumBase(width)
+
+    def setup(self, m, in_a, in_b, out_a, out_b):
+        """ links module to inputs and outputs
+        """
+        m.d.comb += self.in_a.copy(in_a)
+        m.d.comb += self.in_b.copy(in_b)
+        m.d.comb += out_a.copy(self.out_a)
+        m.d.comb += out_b.copy(self.out_b)
+
+    def elaborate(self, platform):
+        # This one however (single-cycle) will do the shift
+        # in one go.
+
         m = Module()
 
-        # Latches
-        a = FPNum(self.width)
-        b = FPNum(self.width)
-        z = FPNum(self.width, 24)
+        #m.submodules.align_in_a = self.in_a
+        #m.submodules.align_in_b = self.in_b
+        m.submodules.align_out_a = self.out_a
+        m.submodules.align_out_b = self.out_b
+
+        # XXX TODO: the shifter used here is quite expensive
+        # having only one would be better
+
+        ediff = Signal((len(self.in_a.e), True), reset_less=True)
+        ediffr = Signal((len(self.in_a.e), True), reset_less=True)
+        m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
+        m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
+        m.d.comb += self.out_a.copy(self.in_a)
+        m.d.comb += self.out_b.copy(self.in_b)
+        with m.If(ediff > 0):
+            m.d.comb += self.out_b.shift_down_multi(ediff)
+        # exponent of b greater than a: shift a down
+        with m.Elif(ediff < 0):
+            m.d.comb += self.out_a.shift_down_multi(ediffr)
+        return m
 
-        tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
 
-        guard = Signal()     # tot[2]
-        round_bit = Signal() # tot[1]
-        sticky = Signal()    # tot[0]
+class FPAddAlignSingle(FPState):
 
-        with m.FSM() as fsm:
+    def __init__(self, width):
+        FPState.__init__(self, "align")
+        self.mod = FPAddAlignSingleMod(width)
+        self.out_a = FPNumIn(None, width)
+        self.out_b = FPNumIn(None, width)
 
-            # ******
-            # gets operand a
+    def action(self, m):
+        m.d.sync += self.a.copy(self.out_a)
+        m.d.sync += self.b.copy(self.out_b)
+        m.next = "add_0"
 
-            with m.State("get_a"):
-                with m.If((self.in_a_ack) & (self.in_a_stb)):
-                    m.next = "get_b"
-                    m.d.sync += [
-                        a.v.eq(self.in_a),
-                        self.in_a_ack.eq(0)
-                    ]
-                with m.Else():
-                    m.d.sync += self.in_a_ack.eq(1)
-
-            # ******
-            # gets operand b
-
-            with m.State("get_b"):
-                with m.If((self.in_b_ack) & (self.in_b_stb)):
-                    m.next = "get_a"
-                    m.d.sync += [
-                        b.v.eq(self.in_b),
-                        self.in_b_ack.eq(0)
-                    ]
-                with m.Else():
-                    m.d.sync += self.in_b_ack.eq(1)
-
-            # ******
-            # unpacks operands into sign, mantissa and exponent
-
-            with m.State("unpack"):
-                m.next = "special_cases"
-                m.d.sync += a.decode()
-                m.d.sync += b.decode()
-
-            # ******
-            # special cases: NaNs, infs, zeros, denormalised
-
-            with m.State("special_cases"):
-
-                # if a is NaN or b is NaN return NaN
-                with m.If(a.is_nan() | b.is_nan()):
-                    m.next = "put_z"
-                    m.d.sync += z.nan(1)
-
-                # if a is inf return inf (or NaN)
-                with m.Elif(a.is_inf()):
-                    m.next = "put_z"
-                    m.d.sync += z.inf(a.s)
-                    # if a is inf and signs don't match return NaN
-                    with m.If((b.e == 128) & (a.s != b.s)):
-                        m.d.sync += z.nan(b.s)
-
-                # if b is inf return inf
-                with m.Elif(b.is_inf()):
-                    m.next = "put_z"
-                    m.d.sync += z.inf(b.s)
-
-                # if a is zero and b zero return signed-a/b
-                with m.Elif(a.is_zero() & b.is_zero()):
-                    m.next = "put_z"
-                    m.d.sync += z.create(a.s & b.s, b.e[0:8], b.m[3:26])
-
-                # if a is zero return b
-                with m.Elif(a.is_zero()):
-                    m.next = "put_z"
-                    m.d.sync += z.create(b.s, b.e[0:8], b.m[3:26])
-
-                # if b is zero return a
-                with m.Elif(b.is_zero()):
-                    m.next = "put_z"
-                    m.d.sync += z.create(a.s, a.e[0:8], a.m[3:26])
-
-                # Denormalised Number checks
-                with m.Else():
-                    m.next = "align"
-                    # denormalise a check
-                    with m.If(a.e == -127):
-                        m.d.sync += a.e.eq(-126) # limit a exponent
-                    with m.Else():
-                        m.d.sync += a.m[26].eq(1) # set highest mantissa bit
-                    # denormalise b check
-                    with m.If(b.e == -127):
-                        m.d.sync += b.e.eq(-126) # limit b exponent
-                    with m.Else():
-                        m.d.sync += b.m[26].eq(1) # set highest mantissa bit
-
-            # ******
-            # align.  NOTE: this does *not* do single-cycle multi-shifting,
-            #         it *STAYS* in the align state until the exponents match
-
-            with m.State("align"):
-                # exponent of a greater than b: increment b exp, shift b mant
-                with m.If(a.e > b.e):
-                    m.d.sync += b.shift_down()
-                # exponent of b greater than a: increment a exp, shift a mant
-                with m.Elif(a.e < b.e):
-                    m.d.sync += a.shift_down()
-                # exponents equal: move to next stage.
-                with m.Else():
-                    m.next = "add_0"
-
-            # ******
-            # First stage of add.  covers same-sign (add) and subtract
-            # special-casing when mantissas are greater or equal, to
-            # give greatest accuracy.
-
-            with m.State("add_0"):
-                m.next = "add_1"
-                m.d.sync += z.e.eq(a.e)
-                # same-sign (both negative or both positive) add mantissas
-                with m.If(a.s == b.s):
-                    m.d.sync += [
-                        tot.eq(a.m + b.m),
-                        z.s.eq(a.s)
-                    ]
-                # a mantissa greater than b, use a
-                with m.Elif(a.m >= b.m):
-                    m.d.sync += [
-                        tot.eq(a.m - b.m),
-                        z.s.eq(a.s)
-                    ]
-                # b mantissa greater than a, use b
-                with m.Else():
-                    m.d.sync += [
-                        tot.eq(b.m - a.m),
-                        z.s.eq(b.s)
-                ]
 
-            # ******
-            # Second stage of add: preparation for normalisation.
-            # detects when tot sum is too big (tot[27] is kinda a carry bit)
-
-            with m.State("add_1"):
-                m.next = "normalise_1"
-                # tot[27] gets set when the sum overflows. shift result down
-                with m.If(tot[27]):
-                    m.d.sync += [
-                        z.m.eq(tot[4:28]),
-                        guard.eq(tot[3]),
-                        round_bit.eq(tot[2]),
-                        sticky.eq(tot[1] | tot[0]),
-                        z.e.eq(z.e + 1)
-                ]
-                # tot[27] zero case
-                with m.Else():
-                    m.d.sync += [
-                        z.m.eq(tot[3:27]),
-                        guard.eq(tot[2]),
-                        round_bit.eq(tot[1]),
-                        sticky.eq(tot[0])
-                ]
+class FPAddStage0Mod:
 
-            # ******
-            # First stage of normalisation.
-            # NOTE: just like "align", this one keeps going round every clock
-            #       until the result's exponent is within acceptable "range"
-            # NOTE: the weirdness of reassigning guard and round is due to
-            #       the extra mantissa bits coming from tot[0..2]
-
-            with m.State("normalise_1"):
-                with m.If((z.m[23] == 0) & (z.e > -126)):
-                    m.d.sync +=[
-                        z.e.eq(z.e - 1),  # DECREASE exponent
-                        z.m.eq(z.m << 1), # shift mantissa UP
-                        z.m[0].eq(guard), # steal guard bit (was tot[2])
-                        guard.eq(round_bit), # steal round_bit (was tot[1])
-                    ]
-                with m.Else():
-                    m.next = "normalize_2"
-
-            # ******
-            # Second stage of normalisation.
-            # NOTE: just like "align", this one keeps going round every clock
-            #       until the result's exponent is within acceptable "range"
-            # NOTE: the weirdness of reassigning guard and round is due to
-            #       the extra mantissa bits coming from tot[0..2]
-
-            with m.State("normalise_2"):
-                with m.If(z.e < -126):
-                    m.d.sync +=[
-                        z.e.eq(z.e + 1),  # INCREASE exponent
-                        z.m.eq(z.m >> 1), # shift mantissa DOWN
-                        guard.eq(z.m[0]),
-                        round_bit.eq(guard),
-                        sticky.eq(sticky | round_bit)
+    def __init__(self, width):
+        self.in_a = FPNumBase(width)
+        self.in_b = FPNumBase(width)
+        self.in_z = FPNumBase(width, False)
+        self.out_z = FPNumBase(width, False)
+        self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+
+    def setup(self, m, in_a, in_b, in_z, out_z, out_tot):
+        """ links module to inputs and outputs
+        """
+        m.d.comb += self.in_a.copy(in_a)
+        m.d.comb += self.in_b.copy(in_b)
+        m.d.comb += self.in_z.copy(in_z)
+        m.d.comb += out_z.copy(self.out_z)
+        m.d.comb += out_tot.eq(self.out_tot)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.add0_in_a = self.in_a
+        m.submodules.add0_in_b = self.in_b
+        #m.submodules.add0_in_z = self.in_z
+        #m.submodules.add0_out_z = self.out_z
+
+        m.d.comb += self.out_z.e.eq(self.in_a.e)
+
+        # store intermediate tests (and zero-extended mantissas)
+        seq = Signal(reset_less=True)
+        mge = Signal(reset_less=True)
+        am0 = Signal(len(self.in_a.m)+1, reset_less=True)
+        bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
+        m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
+                     mge.eq(self.in_a.m >= self.in_b.m),
+                     am0.eq(Cat(self.in_a.m, 0)),
+                     bm0.eq(Cat(self.in_b.m, 0))
                     ]
-                with m.Else():
-                    m.next = "round"
-
-            # ******
-            # rounding stage
-
-            with m.State("round"):
-                m.next = "pack"
-                with m.If(guard & (round_bit | sticky | z.m[0])):
-                    m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
-                    with m.If(z.m == 0xffffff): # all 1s
-                        m.d.sync += z.e.eq(z.e + 1) # exponent rounds up
-
-            # ******
-            # pack stage
-            with m.State("pack"):
-                m.next = "put_z"
-                m.d.sync += [
-                    z[0:22].eq(z_m[0:22]),
-                    z[22:31].eq(z_e[0:7]),
-                    z[31].eq(z_s)
+        # same-sign (both negative or both positive) add mantissas
+        with m.If(seq):
+            m.d.comb += [
+                self.out_tot.eq(am0 + bm0),
+                self.out_z.s.eq(self.in_a.s)
+            ]
+        # a mantissa greater than b, use a
+        with m.Elif(mge):
+            m.d.comb += [
+                self.out_tot.eq(am0 - bm0),
+                self.out_z.s.eq(self.in_a.s)
+            ]
+        # b mantissa greater than a, use b
+        with m.Else():
+            m.d.comb += [
+                self.out_tot.eq(bm0 - am0),
+                self.out_z.s.eq(self.in_b.s)
+        ]
+        return m
+
+
+class FPAddStage0(FPState):
+    """ First stage of add.  covers same-sign (add) and subtract
+        special-casing when mantissas are greater or equal, to
+        give greatest accuracy.
+    """
+
+    def __init__(self, width):
+        FPState.__init__(self, "add_0")
+        self.mod = FPAddStage0Mod(width)
+        self.out_z = FPNumBase(width, False)
+        self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
+
+    def action(self, m):
+        m.next = "add_1"
+        m.d.sync += self.z.copy(self.out_z)
+
+
+class FPAddStage1Mod(FPState):
+    """ Second stage of add: preparation for normalisation.
+        detects when tot sum is too big (tot[27] is kinda a carry bit)
+    """
+
+    def __init__(self, width):
+        self.out_norm = Signal(reset_less=True)
+        self.in_z = FPNumBase(width, False)
+        self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
+        self.out_z = FPNumBase(width, False)
+        self.out_of = Overflow()
+
+    def setup(self, m, in_tot, in_z, out_z, out_of):
+        """ links module to inputs and outputs
+        """
+        m.d.comb += self.in_z.copy(in_z)
+        m.d.comb += self.in_tot.eq(in_tot)
+        #m.d.comb += out_z.copy(self.out_z)
+        #m.d.comb += out_of.copy(self.out_of)
+
+    def elaborate(self, platform):
+        m = Module()
+        #m.submodules.norm1_in_overflow = self.in_of
+        #m.submodules.norm1_out_overflow = self.out_of
+        #m.submodules.norm1_in_z = self.in_z
+        #m.submodules.norm1_out_z = self.out_z
+        m.d.comb += self.out_z.copy(self.in_z)
+        # tot[27] gets set when the sum overflows. shift result down
+        with m.If(self.in_tot[-1]):
+            m.d.comb += [
+                self.out_z.m.eq(self.in_tot[4:]),
+                self.out_of.m0.eq(self.in_tot[4]),
+                self.out_of.guard.eq(self.in_tot[3]),
+                self.out_of.round_bit.eq(self.in_tot[2]),
+                self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
+                self.out_z.e.eq(self.in_z.e + 1)
+        ]
+        # tot[27] zero case
+        with m.Else():
+            m.d.comb += [
+                self.out_z.m.eq(self.in_tot[3:]),
+                self.out_of.m0.eq(self.in_tot[3]),
+                self.out_of.guard.eq(self.in_tot[2]),
+                self.out_of.round_bit.eq(self.in_tot[1]),
+                self.out_of.sticky.eq(self.in_tot[0])
+        ]
+        return m
+
+
+class FPAddStage1(FPState):
+
+    def __init__(self, width):
+        FPState.__init__(self, "add_1")
+        self.mod = FPAddStage1Mod(width)
+        self.out_z = FPNumBase(width, False)
+        self.out_of = Overflow()
+        self.norm_stb = Signal()
+
+    def action(self, m):
+        m.submodules.add1_out_overflow = self.out_of
+        m.d.sync += self.out_of.copy(self.mod.out_of)
+        m.d.sync += self.out_z.copy(self.mod.out_z)
+        m.d.sync += self.norm_stb.eq(1)
+        m.next = "normalise_1"
+
+
+class FPNorm1Mod:
+
+    def __init__(self, width):
+        self.width = width
+        self.in_select = Signal(reset_less=True)
+        self.out_norm = Signal(reset_less=True)
+        self.in_z = FPNumBase(width, False)
+        self.in_of = Overflow()
+        self.temp_z = FPNumBase(width, False)
+        self.temp_of = Overflow()
+        self.out_z = FPNumBase(width, False)
+        self.out_of = Overflow()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.norm1_out_z = self.out_z
+        m.submodules.norm1_out_overflow = self.out_of
+        m.submodules.norm1_temp_z = self.temp_z
+        m.submodules.norm1_temp_of = self.temp_of
+        m.submodules.norm1_in_z = self.in_z
+        m.submodules.norm1_in_overflow = self.in_of
+        in_z = FPNumBase(self.width, False)
+        in_of = Overflow()
+        m.submodules.norm1_insel_z = in_z
+        m.submodules.norm1_insel_overflow = in_of
+        # select which of temp or in z/of to use
+        with m.If(self.in_select):
+            m.d.comb += in_z.copy(self.in_z)
+            m.d.comb += in_of.copy(self.in_of)
+        with m.Else():
+            m.d.comb += in_z.copy(self.temp_z)
+            m.d.comb += in_of.copy(self.temp_of)
+        # initialise out from in (overridden below)
+        m.d.comb += self.out_z.copy(in_z)
+        m.d.comb += self.out_of.copy(in_of)
+        # normalisation increase/decrease conditions
+        decrease = Signal(reset_less=True)
+        increase = Signal(reset_less=True)
+        m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
+        m.d.comb += increase.eq(in_z.exp_lt_n126)
+        m.d.comb += self.out_norm.eq(decrease | increase) # loop-end condition
+        # decrease exponent
+        with m.If(decrease):
+            m.d.comb += [
+                self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
+                self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
+                self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
+                self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
+                self.out_of.round_bit.eq(0),        # reset round bit
+                self.out_of.m0.eq(in_of.guard),
             ]
-                with m.If(z_e == -126 & z_m[23] == 0):
-                    m.d.sync += z[23:31].eq(0)
-                with m.If(z_e == -126 & z_m[0:23] == x): #how to convert 24'h0 into format understandable by nmigen?
-                    m.d.sync += z[23:31].eq(0)
-                with m.If(z_e > 127):
-                    m.d.sync += [
-                        z[0:22].eq(0),
-                        z[23:31].eq(255),
-                        z[31].eq(z_s),
+        # increase exponent
+        with m.If(increase):
+            m.d.comb += [
+                self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
+                self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
+                self.out_of.guard.eq(in_z.m[0]),
+                self.out_of.m0.eq(in_z.m[1]),
+                self.out_of.round_bit.eq(in_of.guard),
+                self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
+            ]
+
+        return m
+
+
+class FPNorm1(FPState):
+
+    def __init__(self, width):
+        FPState.__init__(self, "normalise_1")
+        self.mod = FPNorm1Mod(width)
+        self.stb = Signal(reset_less=True)
+        self.ack = Signal(reset=0, reset_less=True)
+        self.out_norm = Signal(reset_less=True)
+        self.in_accept = Signal(reset_less=True)
+        self.temp_z = FPNumBase(width)
+        self.temp_of = Overflow()
+        self.out_z = FPNumBase(width)
+        self.out_of = Overflow()
+
+    def setup(self, m, in_z, in_of, norm_stb):
+        """ links module to inputs and outputs
+        """
+        m.submodules.normalise_1 = self.mod
+
+        m.d.comb += self.mod.in_z.copy(in_z)
+        m.d.comb += self.mod.in_of.copy(in_of)
+
+        m.d.comb += self.mod.in_select.eq(self.in_accept)
+        m.d.comb += self.mod.temp_z.copy(self.temp_z)
+        m.d.comb += self.mod.temp_of.copy(self.temp_of)
+
+        m.d.comb += self.out_z.copy(self.mod.out_z)
+        m.d.comb += self.out_of.copy(self.mod.out_of)
+        m.d.comb += self.out_norm.eq(self.mod.out_norm)
+
+        m.d.comb += self.stb.eq(norm_stb)
+        m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
+
+    def action(self, m):
+        m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
+        m.d.sync += self.of.copy(self.out_of)
+        m.d.sync += self.z.copy(self.out_z)
+        m.d.sync += self.temp_of.copy(self.out_of)
+        m.d.sync += self.temp_z.copy(self.out_z)
+        with m.If(self.out_norm):
+            with m.If(self.in_accept):
+                m.d.sync += [
+                    self.ack.eq(1),
                 ]
-            """ TODO: see if z.create can be used *later*.  convert
-                verilog first (and commit), *second* phase, convert nmigen
-                code to use FPNum.create() (as a separate commit)
-
-              pack:
-              begin
-                z[22 : 0] <= z_m[22:0];
-                z[30 : 23] <= z_e[7:0] + 127;
-                z[31] <= z_s;
-                if ($signed(z_e) == -126 && z_m[23] == 0) begin
-                  z[30 : 23] <= 0;
-                end
-                if ($signed(z_e) == -126 && z_m[23:0] == 24'h0) begin
-                  z[31] <= 1'b0; // FIX SIGN BUG: -a + a = +0.
-                end
-                //if overflow occurs, return inf
-                if ($signed(z_e) > 127) begin
-                  z[22 : 0] <= 0;
-                  z[30 : 23] <= 255;
-                  z[31] <= z_s;
-                end
-                state <= put_z;
-              end
-            """
-
-            # ******
-            # put_z stage
-
-            """
-              put_z:
-              begin
-                s_out_z_stb <= 1;
-                s_out_z <= z;
-                if (s_out_z_stb && out_z_ack) begin
-                  s_out_z_stb <= 0;
-                  state <= get_a;
-                end
-              end
-            """
+            with m.Else():
+                m.d.sync += self.ack.eq(0)
+        with m.Else():
+            # normalisation not required (or done).
+            m.next = "round"
+            m.d.sync += self.ack.eq(1)
+
+
+class FPRoundMod:
+
+    def __init__(self, width):
+        self.in_roundz = Signal(reset_less=True)
+        self.in_z = FPNumBase(width, False)
+        self.out_z = FPNumBase(width, False)
+
+    def setup(self, m, in_z, out_z, in_of):
+        """ links module to inputs and outputs
+        """
+        m.d.comb += self.in_z.copy(in_z)
+        m.d.comb += out_z.copy(self.out_z)
+        m.d.comb += self.in_roundz.eq(in_of.roundz)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.comb += self.out_z.copy(self.in_z)
+        with m.If(self.in_roundz):
+            m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
+            with m.If(self.in_z.m == self.in_z.m1s): # all 1s
+                m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
+        return m
+
+
+class FPRound(FPState):
+
+    def __init__(self, width):
+        FPState.__init__(self, "round")
+        self.mod = FPRoundMod(width)
+        self.out_z = FPNumBase(width)
+
+    def action(self, m):
+        m.d.sync += self.z.copy(self.out_z)
+        m.next = "corrections"
+
+
+class FPCorrectionsMod:
+
+    def __init__(self, width):
+        self.in_z = FPNumOut(width, False)
+        self.out_z = FPNumOut(width, False)
+
+    def setup(self, m, in_z, out_z):
+        """ links module to inputs and outputs
+        """
+        m.d.comb += self.in_z.copy(in_z)
+        m.d.comb += out_z.copy(self.out_z)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.corr_in_z = self.in_z
+        m.submodules.corr_out_z = self.out_z
+        m.d.comb += self.out_z.copy(self.in_z)
+        with m.If(self.in_z.is_denormalised):
+            m.d.comb += self.out_z.e.eq(self.in_z.N127)
+
+        #        with m.If(self.in_z.is_overflowed):
+        #            m.d.comb += self.out_z.inf(self.in_z.s)
+        #        with m.Else():
+        #            m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
+        return m
+
+
+class FPCorrections(FPState):
+
+    def __init__(self, width):
+        FPState.__init__(self, "corrections")
+        self.mod = FPCorrectionsMod(width)
+        self.out_z = FPNumBase(width)
+
+    def action(self, m):
+        m.d.sync += self.z.copy(self.out_z)
+        m.next = "pack"
+
+
+class FPPackMod:
+
+    def __init__(self, width):
+        self.in_z = FPNumOut(width, False)
+        self.out_z = FPNumOut(width, False)
+
+    def setup(self, m, in_z, out_z):
+        """ links module to inputs and outputs
+        """
+        m.d.comb += self.in_z.copy(in_z)
+        m.d.comb += out_z.v.eq(self.out_z.v)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.pack_in_z = self.in_z
+        with m.If(self.in_z.is_overflowed):
+            m.d.comb += self.out_z.inf(self.in_z.s)
+        with m.Else():
+            m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
+        return m
+
+
+class FPPack(FPState):
+
+    def __init__(self, width):
+        FPState.__init__(self, "pack")
+        self.mod = FPPackMod(width)
+        self.out_z = FPNumOut(width, False)
+
+    def action(self, m):
+        m.d.sync += self.z.v.eq(self.out_z.v)
+        m.next = "pack_put_z"
+
+
+class FPPutZ(FPState):
+
+    def action(self, m):
+        self.put_z(m, self.z, self.out_z, "get_a")
+
+
+class FPADD:
+
+    def __init__(self, width, single_cycle=False):
+        self.width = width
+        self.single_cycle = single_cycle
+
+        self.in_a  = FPOp(width)
+        self.in_b  = FPOp(width)
+        self.out_z = FPOp(width)
+
+        self.states = []
+
+    def add_state(self, state):
+        self.states.append(state)
+        return state
+
+    def get_fragment(self, platform=None):
+        """ creates the HDL code-fragment for FPAdd
+        """
+        m = Module()
+
+        # Latches
+        z = FPNumOut(self.width, False)
+        m.submodules.fpnum_z = z
+
+        w = z.m_width + 4
+
+        geta = self.add_state(FPGetOp("get_a", "get_b",
+                                      self.in_a, self.width))
+        a = geta.out_op
+        geta.mod.setup(m, self.in_a, geta.out_op, geta.out_decode)
+        m.submodules.get_a = geta.mod
+
+        getb = self.add_state(FPGetOp("get_b", "special_cases",
+                                      self.in_b, self.width))
+        b = getb.out_op
+        getb.mod.setup(m, self.in_b, getb.out_op, getb.out_decode)
+        m.submodules.get_b = getb.mod
+
+        sc = self.add_state(FPAddSpecialCases(self.width))
+        sc.set_inputs({"a": a, "b": b})
+        sc.set_outputs({"z": z})
+        sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
+        m.submodules.specialcases = sc.mod
+
+        dn = self.add_state(FPAddDeNorm(self.width))
+        dn.set_inputs({"a": a, "b": b})
+        #dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
+        dn.mod.setup(m, a, b, dn.out_a, dn.out_b)
+        m.submodules.denormalise = dn.mod
+
+        if self.single_cycle:
+            alm = self.add_state(FPAddAlignSingle(self.width))
+            alm.set_inputs({"a": a, "b": b})
+            alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
+            alm.mod.setup(m, a, b, alm.out_a, alm.out_b)
+        else:
+            alm = self.add_state(FPAddAlignMulti(self.width))
+            alm.set_inputs({"a": a, "b": b})
+            #alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
+            alm.mod.setup(m, a, b, alm.out_a, alm.out_b, alm.exp_eq)
+        m.submodules.align = alm.mod
+
+        az1 = FPNumOut(self.width, False)
+        m.submodules.fpnum_az1 = az1
+
+        add0 = self.add_state(FPAddStage0(self.width))
+        add0.set_inputs({"a": alm.out_a, "b": alm.out_b})
+        add0.set_outputs({"z": az1})
+        add0.mod.setup(m, alm.out_a, alm.out_b, az1, add0.out_z, add0.out_tot)
+        m.submodules.add0 = add0.mod
+
+        add1 = self.add_state(FPAddStage1(self.width))
+        #add1.set_outputs({"z": az})  # XXX Z as output
+        add1.mod.setup(m, add0.out_tot, az1, None, add1.out_of)
+        m.submodules.add1 = add1.mod
+        m.d.sync += add1.norm_stb.eq(0) # sets to zero when not in add1 state
+
+        az = add1.out_z
+
+        n1 = self.add_state(FPNorm1(self.width))
+        n1.set_inputs({"z": az, "of": add1.out_of})  # XXX Z as output
+        n1.set_outputs({"z": az})  # XXX Z as output
+        n1.setup(m, az, add1.out_of, add1.norm_stb)
+
+        rnz = FPNumOut(self.width, False)
+        m.submodules.fpnum_rnz = rnz
+
+        rn = self.add_state(FPRound(self.width))
+        rn.set_inputs({"of": n1.out_of})
+        rn.set_outputs({"z": rnz})
+        rn.mod.setup(m, n1.out_z, rn.out_z, add1.out_of)
+        m.submodules.roundz = rn.mod
+
+        cor = self.add_state(FPCorrections(self.width))
+        cor.set_inputs({"z": rnz})  # XXX Z as output
+        cor.mod.setup(m, rnz, cor.out_z)
+        m.submodules.corrections = cor.mod
+
+        pa = self.add_state(FPPack(self.width))
+        pa.set_inputs({"z": cor.out_z})  # XXX Z as output
+        pa.mod.setup(m, cor.out_z, pa.out_z)
+        m.submodules.pack = pa.mod
+
+        ppz = self.add_state(FPPutZ("pack_put_z"))
+        ppz.set_inputs({"z": pa.out_z})
+        ppz.set_outputs({"out_z": self.out_z})
+
+        pz = self.add_state(FPPutZ("put_z"))
+        pz.set_inputs({"z": z})
+        pz.set_outputs({"out_z": self.out_z})
+
+        with m.FSM() as fsm:
+
+            for state in self.states:
+                with m.State(state.state_from):
+                    state.action(m)
 
         return m
 
-"""
-  always @(posedge clk)
-  begin
-
-    case(state)
-
-      get_a:
-      begin
-        s_in_a_ack <= 1;
-        if (s_in_a_ack && in_a_stb) begin
-          a <= in_a;
-          s_in_a_ack <= 0;
-          state <= get_b;
-        end
-      end
-
-      get_b:
-      begin
-        s_in_b_ack <= 1;
-        if (s_in_b_ack && in_b_stb) begin
-          b <= in_b;
-          s_in_b_ack <= 0;
-          state <= unpack;
-        end
-      end
-
-      unpack:
-      begin
-        a_m <= {a[22 : 0], 3'd0};
-        b_m <= {b[22 : 0], 3'd0};
-        a_e <= a[30 : 23] - 127;
-        b_e <= b[30 : 23] - 127;
-        a_s <= a[31];
-        b_s <= b[31];
-        state <= special_cases;
-      end
-
-      special_cases:
-      begin
-        //if a is NaN or b is NaN return NaN
-        if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
-          z[31] <= 1;
-          z[30:23] <= 255;
-          z[22] <= 1;
-          z[21:0] <= 0;
-          state <= put_z;
-        //if a is inf return inf
-        end else if (a_e == 128) begin
-          z[31] <= a_s;
-          z[30:23] <= 255;
-          z[22:0] <= 0;
-          //if a is inf and signs don't match return nan
-          if ((b_e == 128) && (a_s != b_s)) begin
-              z[31] <= b_s;
-              z[30:23] <= 255;
-              z[22] <= 1;
-              z[21:0] <= 0;
-          end
-          state <= put_z;
-        //if b is inf return inf
-        end else if (b_e == 128) begin
-          z[31] <= b_s;
-          z[30:23] <= 255;
-          z[22:0] <= 0;
-          state <= put_z;
-        //if a is zero return b
-        end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
-          z[31] <= a_s & b_s;
-          z[30:23] <= b_e[7:0] + 127;
-          z[22:0] <= b_m[26:3];
-          state <= put_z;
-        //if a is zero return b
-        end else if (($signed(a_e) == -127) && (a_m == 0)) begin
-          z[31] <= b_s;
-          z[30:23] <= b_e[7:0] + 127;
-          z[22:0] <= b_m[26:3];
-          state <= put_z;
-        //if b is zero return a
-        end else if (($signed(b_e) == -127) && (b_m == 0)) begin
-          z[31] <= a_s;
-          z[30:23] <= a_e[7:0] + 127;
-          z[22:0] <= a_m[26:3];
-          state <= put_z;
-        end else begin
-          //Denormalised Number
-          if ($signed(a_e) == -127) begin
-            a_e <= -126;
-          end else begin
-            a_m[26] <= 1;
-          end
-          //Denormalised Number
-          if ($signed(b_e) == -127) begin
-            b_e <= -126;
-          end else begin
-            b_m[26] <= 1;
-          end
-          state <= align;
-        end
-      end
-
-      align:
-      begin
-        if ($signed(a_e) > $signed(b_e)) begin
-          b_e <= b_e + 1;
-          b_m <= b_m >> 1;
-          b_m[0] <= b_m[0] | b_m[1];
-        end else if ($signed(a_e) < $signed(b_e)) begin
-          a_e <= a_e + 1;
-          a_m <= a_m >> 1;
-          a_m[0] <= a_m[0] | a_m[1];
-        end else begin
-          state <= add_0;
-        end
-      end
-
-      add_0:
-      begin
-        z_e <= a_e;
-        if (a_s == b_s) begin
-          tot <= a_m + b_m;
-          z_s <= a_s;
-        end else begin
-          if (a_m >= b_m) begin
-            tot <= a_m - b_m;
-            z_s <= a_s;
-          end else begin
-            tot <= b_m - a_m;
-            z_s <= b_s;
-          end
-        end
-        state <= add_1;
-      end
-
-      add_1:
-      begin
-        if (tot[27]) begin
-          z_m <= tot[27:4];
-          guard <= tot[3];
-          round_bit <= tot[2];
-          sticky <= tot[1] | tot[0];
-          z_e <= z_e + 1;
-        end else begin
-          z_m <= tot[26:3];
-          guard <= tot[2];
-          round_bit <= tot[1];
-          sticky <= tot[0];
-        end
-        state <= normalise_1;
-      end
-
-      normalise_1:
-      begin
-        if (z_m[23] == 0 && $signed(z_e) > -126) begin
-          z_e <= z_e - 1;
-          z_m <= z_m << 1;
-          z_m[0] <= guard;
-          guard <= round_bit;
-          round_bit <= 0;
-        end else begin
-          state <= normalise_2;
-        end
-      end
-
-      normalise_2:
-      begin
-        if ($signed(z_e) < -126) begin
-          z_e <= z_e + 1;
-          z_m <= z_m >> 1;
-          guard <= z_m[0];
-          round_bit <= guard;
-          sticky <= sticky | round_bit;
-        end else begin
-          state <= round;
-        end
-      end
-
-      round:
-      begin
-        if (guard && (round_bit | sticky | z_m[0])) begin
-          z_m <= z_m + 1;
-          if (z_m == 24'hffffff) begin
-            z_e <=z_e + 1;
-          end
-        end
-        state <= pack;
-      end
-
-      pack:
-      begin
-        z[22 : 0] <= z_m[22:0];
-        z[30 : 23] <= z_e[7:0] + 127;
-        z[31] <= z_s;
-        if ($signed(z_e) == -126 && z_m[23] == 0) begin
-          z[30 : 23] <= 0;
-        end
-        if ($signed(z_e) == -126 && z_m[23:0] == 24'h0) begin
-          z[31] <= 1'b0; // FIX SIGN BUG: -a + a = +0.
-        end
-        //if overflow occurs, return inf
-        if ($signed(z_e) > 127) begin
-          z[22 : 0] <= 0;
-          z[30 : 23] <= 255;
-          z[31] <= z_s;
-        end
-        state <= put_z;
-      end
-
-      put_z:
-      begin
-        s_out_z_stb <= 1;
-        s_out_z <= z;
-        if (s_out_z_stb && out_z_ack) begin
-          s_out_z_stb <= 0;
-          state <= get_a;
-        end
-      end
-
-    endcase
-
-    if (rst == 1) begin
-      state <= get_a;
-      s_in_a_ack <= 0;
-      s_in_b_ack <= 0;
-      s_out_z_stb <= 0;
-    end
-
-  end
-  assign in_a_ack = s_in_a_ack;
-  assign in_b_ack = s_in_b_ack;
-  assign out_z_stb = s_out_z_stb;
-  assign out_z = s_out_z;
-
-endmodule
-"""
 
 if __name__ == "__main__":
     alu = FPADD(width=32)
-    main(alu, ports=[
-                    alu.in_a, alu.in_a_stb, alu.in_a_ack,
-                    alu.in_b, alu.in_b_stb, alu.in_b_ack,
-                    alu.out_z, alu.out_z_stb, alu.out_z_ack,
-        ])
-
-
-"""
-print(verilog.convert(alu, ports=[in_a, in_a_stb, in_a_ack, #doesnt work for some reason
-                    in_b, in_b_stb, in_b_ack,
-                    out_z, out_z_stb, out_z_ack]))
-"""
+    main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
+
+
+    # works... but don't use, just do "python fname.py convert -t v"
+    #print (verilog.convert(alu, ports=[
+    #                        ports=alu.in_a.ports() + \
+    #                              alu.in_b.ports() + \
+    #                              alu.out_z.ports())