X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ftest_buf_pipe.py;h=8590ccadb8331c29488aa644352a6d13120cd45e;hb=ce7a1d5c48e987cbfb40236f13b17ffcea55b585;hp=9c53431a3f78dfb7b0bdbc83371be12e56b253aa;hpb=481d00c37b31e7908e624235e6e9c93b12baeebb;p=ieee754fpu.git

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 9c53431a..8590ccad 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -86,35 +86,54 @@ def testbench2(dut):
     yield
 
 
-def testbench3(dut):
-    data = []
-    for i in range(10000):
-        #data.append(randint(0, 1<<16-1))
-        data.append(i+1)
-    i = 0
-    o = 0
-    while True:
-        stall = randint(0, 3) == 0
-        send = randint(0, 5) != 0
-        yield dut.i_n_busy.eq(stall)
-        o_p_busy = yield dut.o_p_busy
-        if not o_p_busy:
-            if send and i != len(data):
-                yield dut.i_p_stb.eq(1)
-                yield dut.stage.i_data.eq(data[i])
-                i += 1
-            else:
-                yield dut.i_p_stb.eq(0)
-        yield
-        o_n_stb = yield dut.o_n_stb
-        i_n_busy = yield dut.i_n_busy
-        if o_n_stb and not i_n_busy:
-            o_data = yield dut.stage.o_data
-            assert o_data == data[o] + 1, "%d-%d data %x not match %x\n" \
-                                        % (i, o, o_data, data[o])
-            o += 1
-            if o == len(data):
-                break
+class Test3:
+    def __init__(self, dut):
+        self.dut = dut
+        self.data = []
+        for i in range(10000):
+            #data.append(randint(0, 1<<16-1))
+            self.data.append(i+1)
+        self.i = 0
+        self.o = 0
+
+    def send(self):
+        while self.o != len(self.data):
+            send_range = randint(0, 3)
+            for j in range(randint(1,10)):
+                if send_range == 0:
+                    send = True
+                else:
+                    send = randint(0, send_range) != 0
+                o_p_busy = yield self.dut.o_p_busy
+                if o_p_busy:
+                    yield
+                    continue
+                if send and self.i != len(self.data):
+                    yield self.dut.i_p_stb.eq(1)
+                    yield self.dut.stage.i_data.eq(self.data[self.i])
+                    self.i += 1
+                else:
+                    yield self.dut.i_p_stb.eq(0)
+                yield
+
+    def rcv(self):
+        while self.o != len(self.data):
+            stall_range = randint(0, 3)
+            for j in range(randint(1,10)):
+                stall = randint(0, stall_range) == 0
+                yield self.dut.i_n_busy.eq(stall)
+                yield
+                o_n_stb = yield self.dut.o_n_stb
+                i_n_busy = yield self.dut.i_n_busy
+                if not o_n_stb or i_n_busy:
+                    continue
+                o_data = yield self.dut.stage.o_data
+                assert o_data == self.data[self.o] + 1, \
+                            "%d-%d data %x not match %x\n" \
+                            % (self.i, self.o, o_data, self.data[self.o])
+                self.o += 1
+                if self.o == len(self.data):
+                    break
 
 
 def testbench4(dut):
@@ -193,14 +212,19 @@ class BufPipe2:
         return m
 
 if __name__ == '__main__':
+    print ("test 1")
     dut = BufPipe()
     run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")
 
+    print ("test 2")
     dut = BufPipe2()
     run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")
 
+    print ("test 3")
     dut = BufPipe()
-    run_simulation(dut, testbench3(dut), vcd_name="test_bufpipe3.vcd")
+    test = Test3(dut)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")
 
+    print ("test 4")
     dut = BufPipe2()
     run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")