X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ftest_inout_mux_pipe.py;h=3bb7c4010dedb43d57ef5c884a999468d4e84cc5;hb=f2f2a40f1f6d714e0aa36919e7157cc7a492fb23;hp=8861f281d5e4cea7800bf91225ca7b9c9b6c7ec5;hpb=c66bd3a38a109a6aaeb8649218610b71d155431c;p=ieee754fpu.git

diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index 8861f281..3bb7c401 100644
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -7,7 +7,7 @@
 
 from random import randint
 from math import log
-from nmigen import Module, Signal, Cat, Value
+from nmigen import Module, Signal, Cat, Value, Elaboratable
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
@@ -183,7 +183,7 @@ class TestMuxOutPipe(CombMuxOutPipe):
         CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
 
-class TestInOutPipe:
+class TestInOutPipe(Elaboratable):
     def __init__(self, num_rows=4):
         self.num_rows = num_rows
         self.inpipe = TestPriorityMuxPipe(num_rows) # fan-in (combinatorial)