X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fadd%2Ftest_inout_mux_pipe.py;h=d0ff6489212935c2a3c2bab2fcb93cc19ff894cc;hb=6d7f448a7ba1f400e724eaafc2d56ee3532b549b;hp=57b5676a018ac6835e763800da9ba0ec7b77d375;hpb=adbbd779461acb1ac334be219958fbb457318899;p=ieee754fpu.git

diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index 57b5676a..d0ff6489 100644
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -1,4 +1,4 @@
-""" key strategic example showing how to do multi-input fan-in into a 
+""" key strategic example showing how to do multi-input fan-in into a
     multi-stage pipeline, then multi-output fanout.
 
     the multiplex ID from the fan-in is passed in to the pipeline, preserved,
@@ -11,33 +11,11 @@ from nmigen import Module, Signal, Cat, Value
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMultiOutPipeline
-from multipipe import CombMultiInPipeline, InputPriorityArbiter
+from multipipe import CombMultiOutPipeline, CombMuxOutPipe
+from multipipe import PriorityCombMuxInPipe
 from singlepipe import UnbufferedPipeline
 
 
-class PriorityUnbufferedPipeline(CombMultiInPipeline):
-    def __init__(self, stage, p_len):
-        p_mux = InputPriorityArbiter(self, p_len)
-        CombMultiInPipeline.__init__(self, stage, p_len=p_len, p_mux=p_mux)
-
-    def ports(self):
-        return self.p_mux.ports()
-        #return UnbufferedPipeline.ports(self) + self.p_mux.ports()
-
-
-class MuxUnbufferedPipeline(CombMultiOutPipeline):
-    def __init__(self, stage, n_len):
-        # HACK: stage is also the n-way multiplexer
-        CombMultiOutPipeline.__init__(self, stage, n_len=n_len, n_mux=stage)
-
-        # HACK: n-mux is also the stage... so set the muxid equal to input mid
-        stage.m_id = self.p.i_data.mid
-
-    def ports(self):
-        return self.p_mux.ports()
-
-
 class PassData: # (Value):
     def __init__(self):
         self.mid = Signal(2, reset_less=True)
@@ -66,7 +44,7 @@ class PassThroughStage:
         return PassData()
     def ospec(self):
         return self.ispec() # same as ospec
-                
+
     def process(self, i):
         return i # pass-through
 
@@ -160,21 +138,11 @@ class InputTest:
         print ("recv ended", mid)
 
 
-class TestPriorityMuxPipe(PriorityUnbufferedPipeline):
+class TestPriorityMuxPipe(PriorityCombMuxInPipe):
     def __init__(self, num_rows):
         self.num_rows = num_rows
         stage = PassThroughStage()
-        PriorityUnbufferedPipeline.__init__(self, stage, p_len=self.num_rows)
-
-    def ports(self):
-        res = []
-        for i in range(len(self.p)):
-            res += [self.p[i].i_valid, self.p[i].o_ready] + \
-                    self.p[i].i_data.ports()
-        res += [self.n.i_ready, self.n.o_valid] + \
-                self.n.o_data.ports()
-        return res
-
+        PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
 
 
 class OutputTest:
@@ -214,19 +182,11 @@ class OutputTest:
         yield rs.i_valid.eq(0)
 
 
-class TestMuxOutPipe(MuxUnbufferedPipeline):
+class TestMuxOutPipe(CombMuxOutPipe):
     def __init__(self, num_rows):
         self.num_rows = num_rows
         stage = PassThroughStage()
-        MuxUnbufferedPipeline.__init__(self, stage, n_len=self.num_rows)
-
-    def ports(self):
-        res = [self.p.i_valid, self.p.o_ready] + \
-                self.p.i_data.ports()
-        for i in range(len(self.n)):
-            res += [self.n[i].i_ready, self.n[i].o_valid] + \
-                    self.n[i].o_data.ports()
-        return res
+        CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
 
 class TestInOutPipe: