X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fcommon%2Fac_gpu_info.c;h=6c4630f044499e651a18de362d2597e131646d55;hb=24e90047088599e686b636fde9bda3a96f34a35c;hp=3f39a089ecb59a2ca22473d456c6a9fec9bcbc30;hpb=81945ded0dc3d25d55eaf682dce220fa4c2de9fe;p=mesa.git diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 3f39a089ecb..6c4630f0444 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -84,6 +84,14 @@ static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info) } } +static bool has_syncobj(int fd) +{ + uint64_t value; + if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value)) + return false; + return value ? true : false; +} + bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, struct radeon_info *info, struct amdgpu_gpu_info *amdinfo) @@ -92,7 +100,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, struct amdgpu_heap_info vram, vram_vis, gtt; struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = {}, vcn_dec = {}; uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0; - uint32_t unused_feature; int r, i, j; drmDevicePtr devinfo; @@ -168,21 +175,24 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, } r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0, - &info->me_fw_version, &unused_feature); + &info->me_fw_version, + &info->me_fw_feature); if (r) { fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n"); return false; } r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0, - &info->pfp_fw_version, &unused_feature); + &info->pfp_fw_version, + &info->pfp_fw_feature); if (r) { fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n"); return false; } r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0, - &info->ce_fw_version, &unused_feature); + &info->ce_fw_version, + &info->ce_fw_feature); if (r) { fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n"); return false; @@ -213,7 +223,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->vce_harvest_config = amdinfo->vce_harvest_config; switch (info->pci_id) { -#define CHIPSET(pci_id, name, cfamily) case pci_id: info->family = CHIP_##cfamily; break; +#define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break; #include "pci_ids/radeonsi_pci_ids.h" #undef CHIPSET @@ -258,8 +268,15 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->vce_fw_version = vce.available_rings ? vce_version : 0; info->has_userptr = true; + info->has_syncobj = has_syncobj(fd); + info->has_sync_file = info->has_syncobj && info->drm_minor >= 21; + info->has_ctx_priority = info->drm_minor >= 22; info->num_render_backends = amdinfo->rb_pipes; info->clock_crystal_freq = amdinfo->gpu_counter_freq; + if (!info->clock_crystal_freq) { + fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n"); + info->clock_crystal_freq = 1; + } info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */ if (info->chip_class == GFX9) { info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg); @@ -301,3 +318,30 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, return true; } +void ac_compute_driver_uuid(char *uuid, size_t size) +{ + char amd_uuid[] = "AMD-MESA-DRV"; + + assert(size >= sizeof(amd_uuid)); + + memset(uuid, 0, size); + strncpy(uuid, amd_uuid, size); +} + +void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size) +{ + uint32_t *uint_uuid = (uint32_t*)uuid; + + assert(size >= sizeof(uint32_t)*4); + + /** + * Use the device info directly instead of using a sha1. GL/VK UUIDs + * are 16 byte vs 20 byte for sha1, and the truncation that would be + * required would get rid of part of the little entropy we have. + * */ + memset(uuid, 0, size); + uint_uuid[0] = info->pci_domain; + uint_uuid[1] = info->pci_bus; + uint_uuid[2] = info->pci_dev; + uint_uuid[3] = info->pci_func; +}