X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fcommon%2Fac_gpu_info.c;h=afbb0239628dde8c7c3b45fd30d495b21afe9afa;hb=78c551aca1c785470e3c0480e33a072b0b5f8928;hp=e2e41f0f47ad4dbb61834d7605abb48b6a93a77a;hpb=8b58a14ef76f6d6e6c71fff2cb5c8fa6662a1882;p=mesa.git diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index e2e41f0f47a..afbb0239628 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -96,10 +96,10 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, struct radeon_info *info, struct amdgpu_gpu_info *amdinfo) { + struct drm_amdgpu_info_device device_info = {}; struct amdgpu_buffer_size_alignments alignment_info = {}; - struct amdgpu_heap_info vram, vram_vis, gtt; struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}; - struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}; + struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {}; struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {}; struct amdgpu_gds_resource_info gds = {}; uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0; @@ -125,29 +125,16 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, return false; } - r = amdgpu_query_buffer_size_alignment(dev, &alignment_info); + r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info), + &device_info); if (r) { - fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n"); + fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n"); return false; } - r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram); - if (r) { - fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n"); - return false; - } - - r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, - &vram_vis); - if (r) { - fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n"); - return false; - } - - r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t); + r = amdgpu_query_buffer_size_alignment(dev, &alignment_info); if (r) { - fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n"); + fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n"); return false; } @@ -199,6 +186,14 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, } } + if (info->drm_major == 3 && info->drm_minor >= 27) { + r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg); + if (r) { + fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n"); + return false; + } + } + r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0, &info->me_fw_version, &info->me_fw_feature); @@ -255,12 +250,62 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, return false; } + if (info->drm_minor >= 9) { + struct drm_amdgpu_memory_info meminfo = {}; + + r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo); + if (r) { + fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n"); + return false; + } + + /* Note: usable_heap_size values can be random and can't be relied on. */ + info->gart_size = meminfo.gtt.total_heap_size; + info->vram_size = meminfo.vram.total_heap_size; + info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size; + } else { + /* This is a deprecated interface, which reports usable sizes + * (total minus pinned), but the pinned size computation is + * buggy, so the values returned from these functions can be + * random. + */ + struct amdgpu_heap_info vram, vram_vis, gtt; + + r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram); + if (r) { + fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n"); + return false; + } + + r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, + AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, + &vram_vis); + if (r) { + fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n"); + return false; + } + + r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t); + if (r) { + fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n"); + return false; + } + + info->gart_size = gtt.heap_size; + info->vram_size = vram.heap_size; + info->vram_vis_size = vram_vis.heap_size; + } + /* Set chip identification. */ info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */ info->vce_harvest_config = amdinfo->vce_harvest_config; switch (info->pci_id) { -#define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break; +#define CHIPSET(pci_id, cfamily) \ + case pci_id: \ + info->family = CHIP_##cfamily; \ + info->name = #cfamily; \ + break; #include "pci_ids/radeonsi_pci_ids.h" #undef CHIPSET @@ -269,6 +314,12 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, return false; } + /* Raven2 uses the same PCI IDs as Raven1, but different revision IDs. */ + if (info->family == CHIP_RAVEN && amdinfo->chip_rev >= 0x8) { + info->family = CHIP_RAVEN2; + info->name = "RAVEN2"; + } + if (info->family >= CHIP_VEGA10) info->chip_class = GFX9; else if (info->family >= CHIP_TONGA) @@ -286,22 +337,25 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->has_dedicated_vram = !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION); - /* Set hardware information. */ - info->gart_size = gtt.heap_size; - info->vram_size = vram.heap_size; - info->vram_vis_size = vram_vis.heap_size; - info->gds_size = gds.gds_total_size; - info->gds_gfx_partition_size = gds.gds_gfx_partition_size; /* The kernel can split large buffers in VRAM but not in GTT, so large * allocations can fail or cause buffer movement failures in the kernel. */ - info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size * 0.7); + if (info->has_dedicated_vram) + info->max_alloc_size = info->vram_size * 0.8; + else + info->max_alloc_size = info->gart_size * 0.7; + + /* Set hardware information. */ + info->gds_size = gds.gds_total_size; + info->gds_gfx_partition_size = gds.gds_gfx_partition_size; /* convert the shader clock from KHz to MHz */ info->max_shader_clock = amdinfo->max_engine_clk / 1000; + info->num_tcc_blocks = device_info.num_tcc_blocks; info->max_se = amdinfo->num_shader_engines; info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine; info->has_hw_decode = - (uvd.available_rings != 0) || (vcn_dec.available_rings != 0); + (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) || + (vcn_jpeg.available_rings != 0); info->uvd_fw_version = uvd.available_rings ? uvd_version : 0; info->vce_fw_version = @@ -313,11 +367,30 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20; info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21; info->has_ctx_priority = info->drm_minor >= 22; - /* TODO: Enable this once the kernel handles it efficiently. */ - info->has_local_buffers = info->drm_minor >= 20 && - !info->has_dedicated_vram; + info->has_local_buffers = info->drm_minor >= 20; info->kernel_flushes_hdp_before_ib = true; info->htile_cmask_support_1d_tiling = true; + info->si_TA_CS_BC_BASE_ADDR_allowed = true; + info->has_bo_metadata = true; + info->has_gpu_reset_status_query = true; + info->has_gpu_reset_counter_query = false; + info->has_eqaa_surface_allocator = true; + info->has_format_bc1_through_bc7 = true; + /* DRM 3.1.0 doesn't flush TC for VI correctly. */ + info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI || + info->drm_minor >= 2; + info->has_indirect_compute_dispatch = true; + /* SI doesn't support unaligned loads. */ + info->has_unaligned_shader_loads = info->chip_class != SI; + /* Disable sparse mappings on SI due to VM faults in CP DMA. Enable them once + * these faults are mitigated in software. + * Disable sparse mappings on GFX9 due to hangs. + */ + info->has_sparse_vm_mappings = + info->chip_class >= CIK && info->chip_class <= VI && + info->drm_minor >= 13; + info->has_2d_tiling = true; + info->has_read_registers_query = true; info->num_render_backends = amdinfo->rb_pipes; /* The value returned by the kernel driver was wrong. */ @@ -354,6 +427,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, for (j = 0; j < info->max_sh_per_se; j++) info->num_good_compute_units += util_bitcount(amdinfo->cu_bitmap[i][j]); + info->num_good_cu_per_sh = info->num_good_compute_units / + (info->max_se * info->max_sh_per_se); memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode, sizeof(amdinfo->gb_tile_mode)); @@ -377,9 +452,18 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, ib_align = MAX2(ib_align, vce.ib_start_alignment); ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment); ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment); - assert(ib_align); + ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment); + assert(ib_align); info->ib_start_alignment = ib_align; + if (info->drm_minor >= 31 && + (info->family == CHIP_RAVEN || + info->family == CHIP_RAVEN2)) { + if (info->num_render_backends == 1) + info->use_display_dcc_unaligned = true; + else + info->use_display_dcc_with_retile_blit = true; + } return true; } @@ -425,6 +509,9 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq); printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size); + printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned); + printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit); + printf("Memory info:\n"); printf(" pte_fragment_size = %u\n", info->pte_fragment_size); printf(" gart_page_size = %u\n", info->gart_page_size); @@ -456,7 +543,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" vce_fw_version = %u\n", info->vce_fw_version); printf(" vce_harvest_config = %i\n", info->vce_harvest_config); - printf("Kernel info:\n"); + printf("Kernel & winsys capabilities:\n"); printf(" drm = %i.%i.%i\n", info->drm_major, info->drm_minor, info->drm_patchlevel); printf(" has_userptr = %i\n", info->has_userptr); @@ -467,10 +554,24 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" has_local_buffers = %u\n", info->has_local_buffers); printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib); printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling); + printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed); + printf(" has_bo_metadata = %u\n", info->has_bo_metadata); + printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query); + printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query); + printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator); + printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7); + printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib); + printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch); + printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads); + printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings); + printf(" has_2d_tiling = %u\n", info->has_2d_tiling); + printf(" has_read_registers_query = %u\n", info->has_read_registers_query); printf("Shader core info:\n"); printf(" max_shader_clock = %i\n", info->max_shader_clock); printf(" num_good_compute_units = %i\n", info->num_good_compute_units); + printf(" num_good_cu_per_sh = %i\n", info->num_good_cu_per_sh); + printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks); printf(" max_se = %i\n", info->max_se); printf(" max_sh_per_se = %i\n", info->max_sh_per_se); @@ -567,9 +668,10 @@ ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family) void ac_get_raster_config(struct radeon_info *info, uint32_t *raster_config_p, - uint32_t *raster_config_1_p) + uint32_t *raster_config_1_p, + uint32_t *se_tile_repeat_p) { - unsigned raster_config, raster_config_1; + unsigned raster_config, raster_config_1, se_tile_repeat; switch (info->family) { /* 1 SE / 1 RB */ @@ -646,8 +748,16 @@ ac_get_raster_config(struct radeon_info *info, raster_config_1 = 0x0000002a; } + unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config); + unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config); + + /* I don't know how to calculate this, though this is probably a good guess. */ + se_tile_repeat = MAX2(se_width, se_height) * info->max_se; + *raster_config_p = raster_config; *raster_config_1_p = raster_config_1; + if (se_tile_repeat_p) + *se_tile_repeat_p = se_tile_repeat; } void