X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fcommon%2Fac_gpu_info.h;h=946c2df82d00227aefe21c14cffc7c5e1aa459ae;hb=bfb92875992599d9c5ca5ecf39fce36a1719272d;hp=5e404714db6056090eedb3d9c409b3d49f404c6c;hpb=64265ac8d53367c143050df9a8b08b224185e9ae;p=mesa.git

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 5e404714db6..946c2df82d0 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -47,6 +47,9 @@ struct radeon_info {
 	uint32_t                    pci_func;
 
 	/* Device info. */
+	const char                  *name;
+	const char                  *marketing_name;
+	bool                        is_pro_graphics;
 	uint32_t                    pci_id;
 	enum radeon_family          family;
 	enum chip_class             chip_class;
@@ -55,6 +58,12 @@ struct radeon_info {
 	uint32_t                    clock_crystal_freq;
 	uint32_t                    tcc_cache_line_size;
 
+	/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
+	/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
+	bool                        use_display_dcc_unaligned;
+	/* Allocate both aligned and unaligned DCC and use the retile blit. */
+	bool                        use_display_dcc_with_retile_blit;
+
 	/* Memory info. */
 	uint32_t                    pte_fragment_size;
 	uint32_t                    gart_page_size;
@@ -105,11 +114,18 @@ struct radeon_info {
 	bool                        has_eqaa_surface_allocator;
 	bool                        has_format_bc1_through_bc7;
 	bool                        kernel_flushes_tc_l2_after_ib;
+	bool                        has_indirect_compute_dispatch;
+	bool                        has_unaligned_shader_loads;
+	bool                        has_sparse_vm_mappings;
+	bool                        has_2d_tiling;
+	bool                        has_read_registers_query;
 
 	/* Shader cores. */
 	uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 	uint32_t                    max_shader_clock;
 	uint32_t                    num_good_compute_units;
+	uint32_t                    num_good_cu_per_sh;
+	uint32_t                    num_tcc_blocks;
 	uint32_t                    max_se; /* shader engines */
 	uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 
@@ -142,7 +158,8 @@ void ac_print_gpu_info(struct radeon_info *info);
 int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family);
 void ac_get_raster_config(struct radeon_info *info,
 			  uint32_t *raster_config_p,
-			  uint32_t *raster_config_1_p);
+			  uint32_t *raster_config_1_p,
+			  uint32_t *se_tile_repeat_p);
 void ac_get_harvested_configs(struct radeon_info *info,
 			      unsigned raster_config,
 			      unsigned *cik_raster_config_1_p,
@@ -163,6 +180,12 @@ static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
 	}
 }
 
+static inline uint32_t
+ac_get_num_physical_sgprs(enum chip_class chip_class)
+{
+	return chip_class >= VI ? 800 : 512;
+}
+
 #ifdef __cplusplus
 }
 #endif