X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fcommon%2Fac_gpu_info.h;h=c9e3e90848bd4c964b484bf773c5847e521d93b1;hb=4a0d2e2880fb4752666bbd4faaf340437aea1a04;hp=c850da22d4ec053b1a5f3b1ff79b717bf16d6360;hpb=fd54fc85aa6ad6f6d904ee7d7cf9955257fa703f;p=mesa.git

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index c850da22d4e..c9e3e90848b 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -53,11 +53,12 @@ struct radeon_info {
 	enum chip_class             chip_class;
 	uint32_t                    family_id;
 	uint32_t                    chip_external_rev;
+	uint32_t                    clock_crystal_freq;
+
+	/* Features. */
 	bool                        has_graphics; /* false if the chip is compute-only */
 	uint32_t                    num_compute_rings;
 	uint32_t                    num_sdma_rings;
-	uint32_t                    clock_crystal_freq;
-	uint32_t                    tcc_cache_line_size;
 	bool                        has_clear_state;
 	bool                        has_distributed_tess;
 	bool                        has_dcc_constant_encode;
@@ -66,7 +67,12 @@ struct radeon_info {
 	bool                        has_load_ctx_reg_pkt;
 	bool                        has_out_of_order_rast;
 	bool                        cpdma_prefetch_writes_memory;
+	bool                        has_gfx9_scissor_bug;
+	bool                        has_tc_compat_zrange_bug;
+	bool                        has_msaa_sample_loc_bug;
+	bool                        has_ls_vgpr_init_bug;
 
+	/* Display features. */
 	/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
 	/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
 	bool                        use_display_dcc_unaligned;
@@ -86,6 +92,10 @@ struct radeon_info {
 	uint32_t                    address32_hi;
 	bool                        has_dedicated_vram;
 	bool                        r600_has_virtual_memory;
+	uint32_t                    num_sdp_interfaces;
+	uint32_t                    num_tcc_blocks;
+	uint32_t                    tcc_cache_line_size;
+	bool			    tcc_harvested;
 
 	/* CP info. */
 	bool                        gfx_ib_pad_with_type2;
@@ -136,9 +146,11 @@ struct radeon_info {
 	uint32_t                    max_shader_clock;
 	uint32_t                    num_good_compute_units;
 	uint32_t                    num_good_cu_per_sh;
-	uint32_t                    num_tcc_blocks;
 	uint32_t                    max_se; /* shader engines */
 	uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
+	uint32_t                    max_wave64_per_simd;
+	uint32_t                    num_physical_sgprs_per_simd;
+	uint32_t                    num_physical_wave64_vgprs_per_simd;
 
 	/* Render backends (color + depth blocks). */
 	uint32_t                    r300_num_gb_pipes;
@@ -153,16 +165,11 @@ struct radeon_info {
 	uint32_t                    pipe_interleave_bytes;
 	uint32_t                    enabled_rb_mask; /* GCN harvest config */
 	uint64_t                    max_alignment; /* from addrlib */
+	uint32_t                    pbb_max_alloc_count;
 
 	/* Tile modes. */
 	uint32_t                    si_tile_mode_array[32];
 	uint32_t                    cik_macrotile_mode_array[16];
-
-	/* Hardware bugs. */
-	bool                        has_gfx9_scissor_bug;
-	bool                        has_tc_compat_zrange_bug;
-	bool                        has_msaa_sample_loc_bug;
-	bool                        has_ls_vgpr_init_bug;
 };
 
 bool ac_query_gpu_info(int fd, void *dev_p,
@@ -187,27 +194,6 @@ unsigned ac_get_compute_resource_limits(struct radeon_info *info,
 					unsigned max_waves_per_sh,
 					unsigned threadgroups_per_cu);
 
-static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
-{
-
-	switch (family) {
-	/* These always have 8 waves: */
-	case CHIP_POLARIS10:
-	case CHIP_POLARIS11:
-	case CHIP_POLARIS12:
-	case CHIP_VEGAM:
-		return 8;
-	default:
-		return 10;
-	}
-}
-
-static inline uint32_t
-ac_get_num_physical_sgprs(enum chip_class chip_class)
-{
-	return chip_class >= GFX8 ? 800 : 512;
-}
-
 #ifdef __cplusplus
 }
 #endif