X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fcommon%2Fac_gpu_info.h;h=fc961bbcd0d85db851dfa4a61850a482ba2b77e4;hb=3de4f6c9f0322830a9a1138e64079228ad410061;hp=f8e4adf0d41f61b5eb7d50d5048bafdb45f1702c;hpb=2bd2c173e8e2fe9c9a589e9944a03672336fe0c6;p=mesa.git diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index f8e4adf0d41..fc961bbcd0d 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -35,8 +35,6 @@ extern "C" { #endif -/* Prior to C11 the following may trigger a typedef redeclaration warning */ -typedef struct amdgpu_device *amdgpu_device_handle; struct amdgpu_gpu_info; struct radeon_info { @@ -47,13 +45,39 @@ struct radeon_info { uint32_t pci_func; /* Device info. */ + const char *name; + const char *marketing_name; + bool is_pro_graphics; uint32_t pci_id; + uint32_t pci_rev_id; enum radeon_family family; enum chip_class chip_class; - uint32_t num_compute_rings; - uint32_t num_sdma_rings; + uint32_t family_id; + uint32_t chip_external_rev; uint32_t clock_crystal_freq; - uint32_t tcc_cache_line_size; + + /* Features. */ + bool has_graphics; /* false if the chip is compute-only */ + uint32_t num_rings[NUM_RING_TYPES]; + bool has_clear_state; + bool has_distributed_tess; + bool has_dcc_constant_encode; + bool has_rbplus; /* if RB+ registers exist */ + bool rbplus_allowed; /* if RB+ is allowed */ + bool has_load_ctx_reg_pkt; + bool has_out_of_order_rast; + bool cpdma_prefetch_writes_memory; + bool has_gfx9_scissor_bug; + bool has_tc_compat_zrange_bug; + bool has_msaa_sample_loc_bug; + bool has_ls_vgpr_init_bug; + + /* Display features. */ + /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ + /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ + bool use_display_dcc_unaligned; + /* Allocate both aligned and unaligned DCC and use the retile blit. */ + bool use_display_dcc_with_retile_blit; /* Memory info. */ uint32_t pte_fragment_size; @@ -61,13 +85,27 @@ struct radeon_info { uint64_t gart_size; uint64_t vram_size; uint64_t vram_vis_size; + uint32_t vram_bit_width; + uint32_t vram_type; unsigned gds_size; unsigned gds_gfx_partition_size; uint64_t max_alloc_size; uint32_t min_alloc_size; uint32_t address32_hi; bool has_dedicated_vram; + bool has_l2_uncached; bool r600_has_virtual_memory; + uint32_t num_sdp_interfaces; + uint32_t num_tcc_blocks; + uint32_t tcc_cache_line_size; + bool tcc_harvested; + unsigned pc_lines; + uint32_t lds_size_per_cu; + uint32_t lds_granularity; + uint32_t max_memory_clock; + uint32_t ce_ram_size; + uint32_t l1_cache_size; + uint32_t l2_cache_size; /* CP info. */ bool gfx_ib_pad_with_type2; @@ -90,6 +128,7 @@ struct radeon_info { uint32_t drm_major; /* version */ uint32_t drm_minor; uint32_t drm_patchlevel; + bool is_amdgpu; bool has_userptr; bool has_syncobj; bool has_syncobj_wait_for_submit; @@ -101,15 +140,34 @@ struct radeon_info { bool si_TA_CS_BC_BASE_ADDR_allowed; bool has_bo_metadata; bool has_gpu_reset_status_query; - bool has_gpu_reset_counter_query; bool has_eqaa_surface_allocator; + bool has_format_bc1_through_bc7; + bool kernel_flushes_tc_l2_after_ib; + bool has_indirect_compute_dispatch; + bool has_unaligned_shader_loads; + bool has_sparse_vm_mappings; + bool has_2d_tiling; + bool has_read_registers_query; + bool has_gds_ordered_append; + bool has_scheduled_fence_dependency; /* Shader cores. */ uint32_t r600_max_quad_pipes; /* wave size / 16 */ uint32_t max_shader_clock; uint32_t num_good_compute_units; + uint32_t num_good_cu_per_sh; uint32_t max_se; /* shader engines */ uint32_t max_sh_per_se; /* shader arrays per shader engine */ + uint32_t max_wave64_per_simd; + uint32_t num_physical_sgprs_per_simd; + uint32_t num_physical_wave64_vgprs_per_simd; + uint32_t num_simd_per_compute_unit; + uint32_t min_sgpr_alloc; + uint32_t max_sgpr_alloc; + uint32_t sgpr_alloc_granularity; + uint32_t min_vgpr_alloc; + uint32_t max_vgpr_alloc; + uint32_t vgpr_alloc_granularity; /* Render backends (color + depth blocks). */ uint32_t r300_num_gb_pipes; @@ -118,18 +176,20 @@ struct radeon_info { bool r600_gb_backend_map_valid; uint32_t r600_num_banks; uint32_t gb_addr_config; + uint32_t pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */ uint32_t num_render_backends; uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ uint32_t pipe_interleave_bytes; uint32_t enabled_rb_mask; /* GCN harvest config */ uint64_t max_alignment; /* from addrlib */ + uint32_t pbb_max_alloc_count; /* Tile modes. */ uint32_t si_tile_mode_array[32]; uint32_t cik_macrotile_mode_array[16]; }; -bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, +bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, struct amdgpu_gpu_info *amdinfo); @@ -140,26 +200,16 @@ void ac_print_gpu_info(struct radeon_info *info); int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family); void ac_get_raster_config(struct radeon_info *info, uint32_t *raster_config_p, - uint32_t *raster_config_1_p); + uint32_t *raster_config_1_p, + uint32_t *se_tile_repeat_p); void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config, unsigned *cik_raster_config_1_p, unsigned *raster_config_se); - -static inline unsigned ac_get_max_simd_waves(enum radeon_family family) -{ - - switch (family) { - /* These always have 8 waves: */ - case CHIP_POLARIS10: - case CHIP_POLARIS11: - case CHIP_POLARIS12: - case CHIP_VEGAM: - return 8; - default: - return 10; - } -} +unsigned ac_get_compute_resource_limits(struct radeon_info *info, + unsigned waves_per_threadgroup, + unsigned max_waves_per_sh, + unsigned threadgroups_per_cu); #ifdef __cplusplus }