X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fcommon%2Fac_surface.c;h=92aab57920a35feda4c678389f177c3f63a74aeb;hb=f0ed67b770619b74120444aa3788197eef28597f;hp=a23952717e3831092cc8a20549e4fc127c840daf;hpb=c6f1d360198c52d208645c0ccb5e988cded408e8;p=mesa.git diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index a23952717e3..92aab57920a 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -27,7 +27,7 @@ #include "ac_surface.h" #include "amd_family.h" -#include "addrlib/amdgpu_asic_addr.h" +#include "addrlib/src/amdgpu_asic_addr.h" #include "ac_gpu_info.h" #include "util/macros.h" #include "util/u_atomic.h" @@ -39,7 +39,7 @@ #include #include -#include "addrlib/addrinterface.h" +#include "addrlib/inc/addrinterface.h" #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A @@ -49,109 +49,6 @@ #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D #endif -static unsigned get_first(unsigned x, unsigned y) -{ - return x; -} - -static void addrlib_family_rev_id(enum radeon_family family, - unsigned *addrlib_family, - unsigned *addrlib_revid) -{ - switch (family) { - case CHIP_TAHITI: - *addrlib_family = FAMILY_SI; - *addrlib_revid = get_first(AMDGPU_TAHITI_RANGE); - break; - case CHIP_PITCAIRN: - *addrlib_family = FAMILY_SI; - *addrlib_revid = get_first(AMDGPU_PITCAIRN_RANGE); - break; - case CHIP_VERDE: - *addrlib_family = FAMILY_SI; - *addrlib_revid = get_first(AMDGPU_CAPEVERDE_RANGE); - break; - case CHIP_OLAND: - *addrlib_family = FAMILY_SI; - *addrlib_revid = get_first(AMDGPU_OLAND_RANGE); - break; - case CHIP_HAINAN: - *addrlib_family = FAMILY_SI; - *addrlib_revid = get_first(AMDGPU_HAINAN_RANGE); - break; - case CHIP_BONAIRE: - *addrlib_family = FAMILY_CI; - *addrlib_revid = get_first(AMDGPU_BONAIRE_RANGE); - break; - case CHIP_KAVERI: - *addrlib_family = FAMILY_KV; - *addrlib_revid = get_first(AMDGPU_SPECTRE_RANGE); - break; - case CHIP_KABINI: - *addrlib_family = FAMILY_KV; - *addrlib_revid = get_first(AMDGPU_KALINDI_RANGE); - break; - case CHIP_HAWAII: - *addrlib_family = FAMILY_CI; - *addrlib_revid = get_first(AMDGPU_HAWAII_RANGE); - break; - case CHIP_MULLINS: - *addrlib_family = FAMILY_KV; - *addrlib_revid = get_first(AMDGPU_GODAVARI_RANGE); - break; - case CHIP_TONGA: - *addrlib_family = FAMILY_VI; - *addrlib_revid = get_first(AMDGPU_TONGA_RANGE); - break; - case CHIP_ICELAND: - *addrlib_family = FAMILY_VI; - *addrlib_revid = get_first(AMDGPU_ICELAND_RANGE); - break; - case CHIP_CARRIZO: - *addrlib_family = FAMILY_CZ; - *addrlib_revid = get_first(AMDGPU_CARRIZO_RANGE); - break; - case CHIP_STONEY: - *addrlib_family = FAMILY_CZ; - *addrlib_revid = get_first(AMDGPU_STONEY_RANGE); - break; - case CHIP_FIJI: - *addrlib_family = FAMILY_VI; - *addrlib_revid = get_first(AMDGPU_FIJI_RANGE); - break; - case CHIP_POLARIS10: - *addrlib_family = FAMILY_VI; - *addrlib_revid = get_first(AMDGPU_POLARIS10_RANGE); - break; - case CHIP_POLARIS11: - *addrlib_family = FAMILY_VI; - *addrlib_revid = get_first(AMDGPU_POLARIS11_RANGE); - break; - case CHIP_POLARIS12: - *addrlib_family = FAMILY_VI; - *addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE); - break; - case CHIP_VEGAM: - *addrlib_family = FAMILY_VI; - *addrlib_revid = get_first(AMDGPU_VEGAM_RANGE); - break; - case CHIP_VEGA10: - *addrlib_family = FAMILY_AI; - *addrlib_revid = get_first(AMDGPU_VEGA10_RANGE); - break; - case CHIP_VEGA12: - *addrlib_family = FAMILY_AI; - *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE); - break; - case CHIP_RAVEN: - *addrlib_family = FAMILY_RV; - *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE); - break; - default: - fprintf(stderr, "amdgpu: Unknown family.\n"); - } -} - static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput) { return malloc(pInput->sizeInBytes); @@ -171,7 +68,7 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info, ADDR_CREATE_OUTPUT addrCreateOutput = {0}; ADDR_REGISTER_VALUE regValue = {0}; ADDR_CREATE_FLAGS createFlags = {{0}}; - ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0}; + ADDR_GET_MAX_ALIGNMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0}; ADDR_E_RETURNCODE addrRet; addrCreateInput.size = sizeof(ADDR_CREATE_INPUT); @@ -180,13 +77,14 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info, regValue.gbAddrConfig = amdinfo->gb_addr_cfg; createFlags.value = 0; - addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision); + addrCreateInput.chipFamily = info->family_id; + addrCreateInput.chipRevision = info->chip_external_rev; + if (addrCreateInput.chipFamily == FAMILY_UNKNOWN) return NULL; if (addrCreateInput.chipFamily >= FAMILY_AI) { addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND; - regValue.blockVarSizeLog2 = 0; } else { regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3; regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2; @@ -227,8 +125,16 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info, return addrCreateOutput.hLib; } -static int surf_config_sanity(const struct ac_surf_config *config) +static int surf_config_sanity(const struct ac_surf_config *config, + unsigned flags) { + /* FMASK is allocated together with the color surface and can't be + * allocated separately. + */ + assert(!(flags & RADEON_SURF_FMASK)); + if (flags & RADEON_SURF_FMASK) + return -EINVAL; + /* all dimension must be at least 1 ! */ if (!config->info.width || !config->info.height || !config->info.depth || !config->info.array_size || !config->info.levels) @@ -241,10 +147,27 @@ static int surf_config_sanity(const struct ac_surf_config *config) case 4: case 8: break; + case 16: + if (flags & RADEON_SURF_Z_OR_SBUFFER) + return -EINVAL; + break; default: return -EINVAL; } + if (!(flags & RADEON_SURF_Z_OR_SBUFFER)) { + switch (config->info.storage_samples) { + case 0: + case 1: + case 2: + case 4: + case 8: + break; + default: + return -EINVAL; + } + } + if (config->is_3d && config->info.array_size > 1) return -EINVAL; if (config->is_cube && config->info.depth > 1) @@ -276,13 +199,24 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, */ if (config->info.levels == 1 && AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED && - AddrSurfInfoIn->bpp) { + AddrSurfInfoIn->bpp && + util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) { unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8); - assert(util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)); AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment); } + /* addrlib assumes the bytes/pixel is a divisor of 64, which is not + * true for r32g32b32 formats. */ + if (AddrSurfInfoIn->bpp == 96) { + assert(config->info.levels == 1); + assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED); + + /* The least common multiple of 64 bytes and 12 bytes/pixel is + * 192 bytes, or 16 pixels. */ + AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 16); + } + if (config->is_3d) AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level); else if (config->is_cube) @@ -343,6 +277,9 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, /* The previous level's flag tells us if we can use DCC for this level. */ if (AddrSurfInfoIn->flags.dccCompatible && (level == 0 || AddrDccOut->subLvlCompressible)) { + bool prev_level_clearable = level == 0 || + AddrDccOut->dccRamSizeAligned; + AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize; AddrDccIn->tileMode = AddrSurfInfoOut->tileMode; AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo; @@ -355,19 +292,69 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, if (ret == ADDR_OK) { surf_level->dcc_offset = surf->dcc_size; - surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize; surf->num_dcc_levels = level + 1; surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize; surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign); + + /* If the DCC size of a subresource (1 mip level or 1 slice) + * is not aligned, the DCC memory layout is not contiguous for + * that subresource, which means we can't use fast clear. + * + * We only do fast clears for whole mipmap levels. If we did + * per-slice fast clears, the same restriction would apply. + * (i.e. only compute the slice size and see if it's aligned) + * + * The last level can be non-contiguous and still be clearable + * if it's interleaved with the next level that doesn't exist. + */ + if (AddrDccOut->dccRamSizeAligned || + (prev_level_clearable && level == config->info.levels - 1)) + surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize; + else + surf_level->dcc_fast_clear_size = 0; + + /* Compute the DCC slice size because addrlib doesn't + * provide this info. As DCC memory is linear (each + * slice is the same size) it's easy to compute. + */ + surf->dcc_slice_size = AddrDccOut->dccRamSize / config->info.array_size; + + /* For arrays, we have to compute the DCC info again + * with one slice size to get a correct fast clear + * size. + */ + if (config->info.array_size > 1) { + AddrDccIn->colorSurfSize = AddrSurfInfoOut->sliceSize; + AddrDccIn->tileMode = AddrSurfInfoOut->tileMode; + AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo; + AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex; + AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex; + + ret = AddrComputeDccInfo(addrlib, + AddrDccIn, AddrDccOut); + if (ret == ADDR_OK) { + /* If the DCC memory isn't properly + * aligned, the data are interleaved + * accross slices. + */ + if (AddrDccOut->dccRamSizeAligned) + surf_level->dcc_slice_fast_clear_size = AddrDccOut->dccFastClearSize; + else + surf_level->dcc_slice_fast_clear_size = 0; + } + } else { + surf_level->dcc_slice_fast_clear_size = surf_level->dcc_fast_clear_size; + } } } - /* TC-compatible HTILE. */ + /* HTILE. */ if (!is_stencil && AddrSurfInfoIn->flags.depth && surf_level->mode == RADEON_SURF_MODE_2D && - level == 0) { - AddrHtileIn->flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible; + level == 0 && + !(surf->flags & RADEON_SURF_NO_HTILE)) { + AddrHtileIn->flags.tcCompatible = AddrSurfInfoOut->tcCompatible; AddrHtileIn->pitch = AddrSurfInfoOut->pitch; AddrHtileIn->height = AddrSurfInfoOut->height; AddrHtileIn->numSlices = AddrSurfInfoOut->depth; @@ -392,6 +379,7 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib, } #define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03) +#define V_009910_ADDR_SURF_THICK_MICRO_TILING 0x03 #define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07) static void gfx6_set_micro_tile_mode(struct radeon_surf *surf, @@ -399,7 +387,7 @@ static void gfx6_set_micro_tile_mode(struct radeon_surf *surf, { uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]]; - if (info->chip_class >= CIK) + if (info->chip_class >= GFX7) surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode); else surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode); @@ -425,8 +413,8 @@ static bool get_display_flag(const struct ac_surf_config *config, unsigned num_channels = config->info.num_channels; unsigned bpe = surf->bpe; - if (surf->flags & RADEON_SURF_SCANOUT && - !(surf->flags & RADEON_SURF_FMASK) && + if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && + surf->flags & RADEON_SURF_SCANOUT && config->info.samples <= 1 && surf->blk_w <= 2 && surf->blk_h == 1) { /* subsampled */ @@ -473,8 +461,8 @@ static int gfx6_surface_settings(ADDR_HANDLE addrlib, } /* Compute tile swizzle. */ - /* TODO: fix tile swizzle with mipmapping for SI */ - if ((info->chip_class >= CIK || config->info.levels == 1) && + /* TODO: fix tile swizzle with mipmapping for GFX6 */ + if ((info->chip_class >= GFX7 || config->info.levels == 1) && config->info.surf_index && surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D && !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) && @@ -503,6 +491,68 @@ static int gfx6_surface_settings(ADDR_HANDLE addrlib, return 0; } +static void ac_compute_cmask(const struct radeon_info *info, + const struct ac_surf_config *config, + struct radeon_surf *surf) +{ + unsigned pipe_interleave_bytes = info->pipe_interleave_bytes; + unsigned num_pipes = info->num_tile_pipes; + unsigned cl_width, cl_height; + + if (surf->flags & RADEON_SURF_Z_OR_SBUFFER || + (config->info.samples >= 2 && !surf->fmask_size)) + return; + + assert(info->chip_class <= GFX8); + + switch (num_pipes) { + case 2: + cl_width = 32; + cl_height = 16; + break; + case 4: + cl_width = 32; + cl_height = 32; + break; + case 8: + cl_width = 64; + cl_height = 32; + break; + case 16: /* Hawaii */ + cl_width = 64; + cl_height = 64; + break; + default: + assert(0); + return; + } + + unsigned base_align = num_pipes * pipe_interleave_bytes; + + unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width*8); + unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height*8); + unsigned slice_elements = (width * height) / (8*8); + + /* Each element of CMASK is a nibble. */ + unsigned slice_bytes = slice_elements / 2; + + surf->u.legacy.cmask_slice_tile_max = (width * height) / (128*128); + if (surf->u.legacy.cmask_slice_tile_max) + surf->u.legacy.cmask_slice_tile_max -= 1; + + unsigned num_layers; + if (config->is_3d) + num_layers = config->info.depth; + else if (config->is_cube) + num_layers = 6; + else + num_layers = config->info.array_size; + + surf->cmask_alignment = MAX2(256, base_align); + surf->cmask_slice_size = align(slice_bytes, base_align); + surf->cmask_size = surf->cmask_slice_size * num_layers; +} + /** * Fill in the tiling information in \p surf based on the given surface config. * @@ -537,9 +587,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, compressed = surf->blk_w == 4 && surf->blk_h == 4; - /* MSAA and FMASK require 2D tiling. */ - if (config->info.samples > 1 || - (surf->flags & RADEON_SURF_FMASK)) + /* MSAA requires 2D tiling. */ + if (config->info.samples > 1) mode = RADEON_SURF_MODE_2D; /* DB doesn't support linear layouts. */ @@ -582,13 +631,18 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, } AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = - config->info.samples ? config->info.samples : 1; + MAX2(1, config->info.samples); AddrSurfInfoIn.tileIndex = -1; + if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) { + AddrDccIn.numSamples = AddrSurfInfoIn.numFrags = + MAX2(1, config->info.storage_samples); + } + /* Set the micro tile type. */ if (surf->flags & RADEON_SURF_SCANOUT) AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE; - else if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK)) + else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER) AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER; else AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE; @@ -596,7 +650,6 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER); AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0; AddrSurfInfoIn.flags.cube = config->is_cube; - AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0; AddrSurfInfoIn.flags.display = get_display_flag(config, surf); AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1; AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0; @@ -616,7 +669,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, * driver team). */ AddrSurfInfoIn.flags.dccCompatible = - info->chip_class >= VI && + info->chip_class >= GFX8 && + info->has_graphics && /* disable DCC on compute-only chips */ !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed && @@ -624,9 +678,9 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, config->info.levels == 1); AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0; - AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth; + AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER); - /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit) + /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit) * for Z and stencil. This can cause a number of problems which we work * around here: * @@ -661,8 +715,6 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw && surf->u.legacy.bankh && surf->u.legacy.mtilea && surf->u.legacy.tile_split) { - assert(!(surf->flags & RADEON_SURF_FMASK)); - /* If any of these parameters are incorrect, the calculation * will fail. */ AddrTileInfoIn.banks = surf->u.legacy.num_banks; @@ -685,7 +737,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1); - if (info->chip_class == SI) { + if (info->chip_class == GFX6) { if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) { if (surf->bpe == 2) AddrSurfInfoIn.tileIndex = 11; /* 16bpp */ @@ -702,7 +754,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */ } } else { - /* CIK - VI */ + /* GFX7 - GFX8 */ if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */ else @@ -737,19 +789,12 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, if (level > 0) continue; - /* Check that we actually got a TC-compatible HTILE if - * we requested it (only for level 0, since we're not - * supporting HTILE on higher mip levels anyway). */ - assert(AddrSurfInfoOut.tcCompatible || - !AddrSurfInfoIn.flags.tcCompatible || - AddrSurfInfoIn.flags.matchStencilTileCfg); + if (!AddrSurfInfoOut.tcCompatible) { + AddrSurfInfoIn.flags.tcCompatible = 0; + surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE; + } if (AddrSurfInfoIn.flags.matchStencilTileCfg) { - if (!AddrSurfInfoOut.tcCompatible) { - AddrSurfInfoIn.flags.tcCompatible = 0; - surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE; - } - AddrSurfInfoIn.flags.matchStencilTileCfg = 0; AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex; stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx; @@ -809,6 +854,69 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, } } + /* Compute FMASK. */ + if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color && + info->has_graphics && !(surf->flags & RADEON_SURF_NO_FMASK)) { + ADDR_COMPUTE_FMASK_INFO_INPUT fin = {0}; + ADDR_COMPUTE_FMASK_INFO_OUTPUT fout = {0}; + ADDR_TILEINFO fmask_tile_info = {}; + + fin.size = sizeof(fin); + fout.size = sizeof(fout); + + fin.tileMode = AddrSurfInfoOut.tileMode; + fin.pitch = AddrSurfInfoOut.pitch; + fin.height = config->info.height; + fin.numSlices = AddrSurfInfoIn.numSlices; + fin.numSamples = AddrSurfInfoIn.numSamples; + fin.numFrags = AddrSurfInfoIn.numFrags; + fin.tileIndex = -1; + fout.pTileInfo = &fmask_tile_info; + + r = AddrComputeFmaskInfo(addrlib, &fin, &fout); + if (r) + return r; + + surf->fmask_size = fout.fmaskBytes; + surf->fmask_alignment = fout.baseAlign; + surf->fmask_tile_swizzle = 0; + + surf->u.legacy.fmask.slice_tile_max = + (fout.pitch * fout.height) / 64; + if (surf->u.legacy.fmask.slice_tile_max) + surf->u.legacy.fmask.slice_tile_max -= 1; + + surf->u.legacy.fmask.tiling_index = fout.tileIndex; + surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight; + surf->u.legacy.fmask.pitch_in_pixels = fout.pitch; + surf->u.legacy.fmask.slice_size = fout.sliceSize; + + /* Compute tile swizzle for FMASK. */ + if (config->info.fmask_surf_index && + !(surf->flags & RADEON_SURF_SHAREABLE)) { + ADDR_COMPUTE_BASE_SWIZZLE_INPUT xin = {0}; + ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT xout = {0}; + + xin.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_INPUT); + xout.size = sizeof(ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT); + + /* This counter starts from 1 instead of 0. */ + xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index); + xin.tileIndex = fout.tileIndex; + xin.macroModeIndex = fout.macroModeIndex; + xin.pTileInfo = fout.pTileInfo; + xin.tileMode = fin.tileMode; + + int r = AddrComputeBaseSwizzle(addrlib, &xin, &xout); + if (r != ADDR_OK) + return r; + + assert(xout.tileSwizzle <= + u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); + surf->fmask_tile_swizzle = xout.tileSwizzle; + } + } + /* Recalculate the whole DCC miptree size including disabled levels. * This is what addrlib does, but calling addrlib would be a lot more * complicated. @@ -829,13 +937,34 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, /* Make sure HTILE covers the whole miptree, because the shader reads * TC-compatible HTILE even for levels where it's disabled by DB. */ - if (surf->htile_size && config->info.levels > 1) - surf->htile_size *= 2; + if (surf->htile_size && config->info.levels > 1 && + surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) { + /* MSAA can't occur with levels > 1, so ignore the sample count. */ + const unsigned total_pixels = surf->surf_size / surf->bpe; + const unsigned htile_block_size = 8 * 8; + const unsigned htile_element_size = 4; + + surf->htile_size = (total_pixels / htile_block_size) * + htile_element_size; + surf->htile_size = align(surf->htile_size, surf->htile_alignment); + } surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED; surf->is_displayable = surf->is_linear || surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY || surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED; + + /* The rotated micro tile mode doesn't work if both CMASK and RB+ are + * used at the same time. This case is not currently expected to occur + * because we don't use rotated. Enforce this restriction on all chips + * to facilitate testing. + */ + if (surf->micro_tile_mode == RADEON_MICRO_MODE_ROTATED) { + assert(!"rotate micro tile mode is unsupported"); + return ADDR_ERROR; + } + + ac_compute_cmask(info, config, surf); return 0; } @@ -843,8 +972,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, static int gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, ADDR2_COMPUTE_SURFACE_INFO_INPUT *in, - bool is_fmask, unsigned flags, - AddrSwizzleMode *swizzle_mode) + bool is_fmask, AddrSwizzleMode *swizzle_mode) { ADDR_E_RETURNCODE ret; ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0}; @@ -860,7 +988,6 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, /* TODO: We could allow some of these: */ sin.forbiddenBlock.micro = 1; /* don't allow the 256B swizzle modes */ sin.forbiddenBlock.var = 1; /* don't allow the variable-sized swizzle modes */ - sin.forbiddenBlock.linear = 1; /* don't allow linear swizzle modes */ sin.bpp = in->bpp; sin.width = in->width; sin.height = in->height; @@ -869,16 +996,6 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, sin.numSamples = in->numSamples; sin.numFrags = in->numFrags; - if (flags & RADEON_SURF_SCANOUT) { - sin.preferredSwSet.sw_D = 1; - /* Raven only allows S for displayable surfaces with < 64 bpp, so - * allow it as fallback */ - sin.preferredSwSet.sw_S = 1; - } else if (in->flags.depth || in->flags.stencil || is_fmask) - sin.preferredSwSet.sw_Z = 1; - else - sin.preferredSwSet.sw_S = 1; - if (is_fmask) { sin.flags.display = 0; sin.flags.color = 0; @@ -893,7 +1010,16 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, return 0; } +static bool gfx9_is_dcc_capable(const struct radeon_info *info, unsigned sw_mode) +{ + if (info->chip_class >= GFX10) + return sw_mode == ADDR_SW_64KB_Z_X || sw_mode == ADDR_SW_64KB_R_X; + + return sw_mode != ADDR_SW_LINEAR; +} + static int gfx9_compute_miptree(ADDR_HANDLE addrlib, + const struct radeon_info *info, const struct ac_surf_config *config, struct radeon_surf *surf, bool compressed, ADDR2_COMPUTE_SURFACE_INFO_INPUT *in) @@ -936,13 +1062,18 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, surf->surf_alignment = out.baseAlign; if (in->swizzleMode == ADDR_SW_LINEAR) { - for (unsigned i = 0; i < in->numMipLevels; i++) + for (unsigned i = 0; i < in->numMipLevels; i++) { surf->u.gfx9.offset[i] = mip_info[i].offset; + surf->u.gfx9.pitch[i] = mip_info[i].pitch; + } } if (in->flags.depth) { assert(in->swizzleMode != ADDR_SW_LINEAR); + if (surf->flags & RADEON_SURF_NO_HTILE) + return 0; + /* HTILE */ ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0}; ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0}; @@ -958,6 +1089,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, hin.unalignedHeight = in->height; hin.numSlices = in->numSlices; hin.numMipLevels = in->numMipLevels; + hin.firstMipIdInTail = out.firstMipIdInTail; ret = Addr2ComputeHtileInfo(addrlib, &hin, &hout); if (ret != ADDR_OK) @@ -968,7 +1100,10 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, surf->htile_size = hout.htileBytes; surf->htile_slice_size = hout.sliceSize; surf->htile_alignment = hout.baseAlign; - } else { + return 0; + } + + { /* Compute tile swizzle for the color surface. * All *_X and *_T modes can use the swizzle. */ @@ -1001,9 +1136,10 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, } /* DCC */ - if (!(surf->flags & RADEON_SURF_DISABLE_DCC) && + if (info->has_graphics && + !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed && - in->swizzleMode != ADDR_SW_LINEAR) { + gfx9_is_dcc_capable(info, in->swizzleMode)) { ADDR2_COMPUTE_DCCINFO_INPUT din = {0}; ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0}; ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {}; @@ -1024,6 +1160,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, din.numFrags = in->numFrags; din.numMipLevels = in->numMipLevels; din.dataSurfaceSize = out.surfSize; + din.firstMipIdInTail = out.firstMipIdInTail; ret = Addr2ComputeDccInfo(addrlib, &din, &dout); if (ret != ADDR_OK) @@ -1031,7 +1168,6 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned; surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned; - surf->u.gfx9.dcc_pitch_max = dout.pitch - 1; surf->dcc_size = dout.dccRamSize; surf->dcc_alignment = dout.dccRamBaseAlign; surf->num_dcc_levels = in->numMipLevels; @@ -1067,10 +1203,111 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, if (!surf->num_dcc_levels) surf->dcc_size = 0; + + surf->u.gfx9.display_dcc_size = surf->dcc_size; + surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment; + surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1; + + /* Compute displayable DCC. */ + if (in->flags.display && + surf->num_dcc_levels && + info->use_display_dcc_with_retile_blit) { + /* Compute displayable DCC info. */ + din.dccKeyFlags.pipeAligned = 0; + din.dccKeyFlags.rbAligned = 0; + + assert(din.numSlices == 1); + assert(din.numMipLevels == 1); + assert(din.numFrags == 1); + assert(surf->tile_swizzle == 0); + assert(surf->u.gfx9.dcc.pipe_aligned || + surf->u.gfx9.dcc.rb_aligned); + + ret = Addr2ComputeDccInfo(addrlib, &din, &dout); + if (ret != ADDR_OK) + return ret; + + surf->u.gfx9.display_dcc_size = dout.dccRamSize; + surf->u.gfx9.display_dcc_alignment = dout.dccRamBaseAlign; + surf->u.gfx9.display_dcc_pitch_max = dout.pitch - 1; + assert(surf->u.gfx9.display_dcc_size <= surf->dcc_size); + + /* Compute address mapping from non-displayable to displayable DCC. */ + ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT addrin = {}; + addrin.size = sizeof(addrin); + addrin.colorFlags.color = 1; + addrin.swizzleMode = din.swizzleMode; + addrin.resourceType = din.resourceType; + addrin.bpp = din.bpp; + addrin.unalignedWidth = din.unalignedWidth; + addrin.unalignedHeight = din.unalignedHeight; + addrin.numSlices = 1; + addrin.numMipLevels = 1; + addrin.numFrags = 1; + + ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT addrout = {}; + addrout.size = sizeof(addrout); + + surf->u.gfx9.dcc_retile_num_elements = + DIV_ROUND_UP(in->width, dout.compressBlkWidth) * + DIV_ROUND_UP(in->height, dout.compressBlkHeight) * 2; + /* Align the size to 4 (for the compute shader). */ + surf->u.gfx9.dcc_retile_num_elements = + align(surf->u.gfx9.dcc_retile_num_elements, 4); + + surf->u.gfx9.dcc_retile_map = + malloc(surf->u.gfx9.dcc_retile_num_elements * 4); + if (!surf->u.gfx9.dcc_retile_map) + return ADDR_OUTOFMEMORY; + + unsigned index = 0; + surf->u.gfx9.dcc_retile_use_uint16 = true; + + for (unsigned y = 0; y < in->height; y += dout.compressBlkHeight) { + addrin.y = y; + + for (unsigned x = 0; x < in->width; x += dout.compressBlkWidth) { + addrin.x = x; + + /* Compute src DCC address */ + addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned; + addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned; + addrout.addr = 0; + + ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout); + if (ret != ADDR_OK) + return ret; + + surf->u.gfx9.dcc_retile_map[index * 2] = addrout.addr; + if (addrout.addr > UINT16_MAX) + surf->u.gfx9.dcc_retile_use_uint16 = false; + + /* Compute dst DCC address */ + addrin.dccKeyFlags.pipeAligned = 0; + addrin.dccKeyFlags.rbAligned = 0; + addrout.addr = 0; + + ret = Addr2ComputeDccAddrFromCoord(addrlib, &addrin, &addrout); + if (ret != ADDR_OK) + return ret; + + surf->u.gfx9.dcc_retile_map[index * 2 + 1] = addrout.addr; + if (addrout.addr > UINT16_MAX) + surf->u.gfx9.dcc_retile_use_uint16 = false; + + assert(index * 2 + 1 < surf->u.gfx9.dcc_retile_num_elements); + index++; + } + } + /* Fill the remaining pairs with the last one (for the compute shader). */ + for (unsigned i = index * 2; i < surf->u.gfx9.dcc_retile_num_elements; i++) + surf->u.gfx9.dcc_retile_map[i] = surf->u.gfx9.dcc_retile_map[i - 2]; + } } /* FMASK */ - if (in->numSamples > 1) { + if (in->numSamples > 1 && info->has_graphics && + !(surf->flags & RADEON_SURF_NO_FMASK)) { ADDR2_COMPUTE_FMASK_INFO_INPUT fin = {0}; ADDR2_COMPUTE_FMASK_INFO_OUTPUT fout = {0}; @@ -1078,8 +1315,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT); ret = gfx9_get_preferred_swizzle_mode(addrlib, in, - true, surf->flags, - &fin.swizzleMode); + true, &fin.swizzleMode); if (ret != ADDR_OK) return ret; @@ -1095,8 +1331,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode; surf->u.gfx9.fmask.epitch = fout.pitch - 1; - surf->u.gfx9.fmask_size = fout.fmaskBytes; - surf->u.gfx9.fmask_alignment = fout.baseAlign; + surf->fmask_size = fout.fmaskBytes; + surf->fmask_alignment = fout.baseAlign; /* Compute tile swizzle for the FMASK surface. */ if (config->info.fmask_surf_index && @@ -1111,7 +1347,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, /* This counter starts from 1 instead of 0. */ xin.surfIndex = p_atomic_inc_return(config->info.fmask_surf_index); xin.flags = in->flags; - xin.swizzleMode = in->swizzleMode; + xin.swizzleMode = fin.swizzleMode; xin.resourceType = in->resourceType; xin.format = in->format; xin.numSamples = in->numSamples; @@ -1122,20 +1358,23 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, return ret; assert(xout.pipeBankXor <= - u_bit_consecutive(0, sizeof(surf->u.gfx9.fmask_tile_swizzle) * 8)); - surf->u.gfx9.fmask_tile_swizzle = xout.pipeBankXor; + u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8)); + surf->fmask_tile_swizzle = xout.pipeBankXor; } } - /* CMASK */ - if (in->swizzleMode != ADDR_SW_LINEAR) { + /* CMASK -- on GFX10 only for FMASK */ + if (in->swizzleMode != ADDR_SW_LINEAR && + in->resourceType == ADDR_RSRC_TEX_2D && + ((info->chip_class <= GFX9 && in->numSamples == 1) || + (surf->fmask_size && in->numSamples >= 2))) { ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0}; ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0}; cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT); cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT); - if (in->numSamples) { + if (in->numSamples > 1) { /* FMASK is always aligned. */ cin.cMaskFlags.pipeAligned = 1; cin.cMaskFlags.rbAligned = 1; @@ -1160,8 +1399,8 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib, surf->u.gfx9.cmask.rb_aligned = cin.cMaskFlags.rbAligned; surf->u.gfx9.cmask.pipe_aligned = cin.cMaskFlags.pipeAligned; - surf->u.gfx9.cmask_size = cout.cmaskBytes; - surf->u.gfx9.cmask_alignment = cout.baseAlign; + surf->cmask_size = cout.cmaskBytes; + surf->cmask_alignment = cout.baseAlign; } } @@ -1178,8 +1417,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0}; int r; - assert(!(surf->flags & RADEON_SURF_FMASK)); - AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT); compressed = surf->blk_w == 4 && surf->blk_h == 4; @@ -1217,6 +1454,10 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); AddrSurfInfoIn.format = ADDR_FMT_32_32; break; + case 12: + assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); + AddrSurfInfoIn.format = ADDR_FMT_32_32_32; + break; case 16: assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32; @@ -1227,23 +1468,30 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, AddrSurfInfoIn.bpp = surf->bpe * 8; } - AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER); + bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER); + AddrSurfInfoIn.flags.color = is_color_surface && + !(surf->flags & RADEON_SURF_NO_RENDER_TARGET); AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0; AddrSurfInfoIn.flags.display = get_display_flag(config, surf); /* flags.texture currently refers to TC-compatible HTILE */ - AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color || + AddrSurfInfoIn.flags.texture = is_color_surface || surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE; AddrSurfInfoIn.flags.opt4space = 1; AddrSurfInfoIn.numMipLevels = config->info.levels; - AddrSurfInfoIn.numSamples = config->info.samples ? config->info.samples : 1; + AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples); AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples; + if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) + AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples); + /* GFX9 doesn't support 1D depth textures, so allocate all 1D textures * as 2D to avoid having shader variants for 1D vs 2D, so all shaders * must sample 1D textures as 2D. */ if (config->is_3d) AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D; + else if (info->chip_class != GFX9 && config->is_1d) + AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D; else AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D; @@ -1261,6 +1509,19 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, AddrSurfInfoIn.flags.metaPipeUnaligned = 0; AddrSurfInfoIn.flags.metaRbUnaligned = 0; + /* The display hardware can only read DCC with RB_ALIGNED=0 and + * PIPE_ALIGNED=0. PIPE_ALIGNED really means L2CACHE_ALIGNED. + * + * The CB block requires RB_ALIGNED=1 except 1 RB chips. + * PIPE_ALIGNED is optional, but PIPE_ALIGNED=0 requires L2 flushes + * after rendering, so PIPE_ALIGNED=1 is recommended. + */ + if (info->use_display_dcc_unaligned && is_color_surface && + AddrSurfInfoIn.flags.display) { + AddrSurfInfoIn.flags.metaPipeUnaligned = 1; + AddrSurfInfoIn.flags.metaRbUnaligned = 1; + } + switch (mode) { case RADEON_SURF_MODE_LINEAR_ALIGNED: assert(config->info.samples <= 1); @@ -1270,14 +1531,13 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, case RADEON_SURF_MODE_1D: case RADEON_SURF_MODE_2D: - if (surf->flags & RADEON_SURF_IMPORTED) { + if (surf->flags & (RADEON_SURF_IMPORTED | RADEON_SURF_FORCE_SWIZZLE_MODE)) { AddrSurfInfoIn.swizzleMode = surf->u.gfx9.surf.swizzle_mode; break; } r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, - false, surf->flags, - &AddrSurfInfoIn.swizzleMode); + false, &AddrSurfInfoIn.swizzleMode); if (r) return r; break; @@ -1291,19 +1551,22 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, surf->num_dcc_levels = 0; surf->surf_size = 0; + surf->fmask_size = 0; surf->dcc_size = 0; surf->htile_size = 0; surf->htile_slice_size = 0; surf->u.gfx9.surf_offset = 0; surf->u.gfx9.stencil_offset = 0; - surf->u.gfx9.fmask_size = 0; - surf->u.gfx9.cmask_size = 0; + surf->cmask_size = 0; + surf->u.gfx9.dcc_retile_use_uint16 = false; + surf->u.gfx9.dcc_retile_num_elements = 0; + surf->u.gfx9.dcc_retile_map = NULL; /* Calculate texture layout information. */ - r = gfx9_compute_miptree(addrlib, config, surf, compressed, + r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn); if (r) - return r; + goto error; /* Calculate texture layout information for stencil. */ if (surf->flags & RADEON_SURF_SBUFFER) { @@ -1313,27 +1576,35 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, if (!AddrSurfInfoIn.flags.depth) { r = gfx9_get_preferred_swizzle_mode(addrlib, &AddrSurfInfoIn, - false, surf->flags, - &AddrSurfInfoIn.swizzleMode); + false, &AddrSurfInfoIn.swizzleMode); if (r) - return r; + goto error; } else AddrSurfInfoIn.flags.depth = 0; - r = gfx9_compute_miptree(addrlib, config, surf, compressed, + r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn); if (r) - return r; + goto error; } surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR; /* Query whether the surface is displayable. */ bool displayable = false; - r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode, + if (!config->is_3d && !config->is_cube) { + r = Addr2IsValidDisplaySwizzleMode(addrlib, surf->u.gfx9.surf.swizzle_mode, surf->bpe * 8, &displayable); - if (r) - return r; + if (r) + goto error; + + /* Display needs unaligned DCC. */ + if (info->use_display_dcc_unaligned && + surf->num_dcc_levels && + (surf->u.gfx9.dcc.pipe_aligned || + surf->u.gfx9.dcc.rb_aligned)) + displayable = false; + } surf->is_displayable = displayable; switch (surf->u.gfx9.surf.swizzle_mode) { @@ -1341,11 +1612,9 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, case ADDR_SW_256B_S: case ADDR_SW_4KB_S: case ADDR_SW_64KB_S: - case ADDR_SW_VAR_S: case ADDR_SW_64KB_S_T: case ADDR_SW_4KB_S_X: case ADDR_SW_64KB_S_X: - case ADDR_SW_VAR_S_X: surf->micro_tile_mode = RADEON_MICRO_MODE_THIN; break; @@ -1354,30 +1623,32 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, case ADDR_SW_256B_D: case ADDR_SW_4KB_D: case ADDR_SW_64KB_D: - case ADDR_SW_VAR_D: case ADDR_SW_64KB_D_T: case ADDR_SW_4KB_D_X: case ADDR_SW_64KB_D_X: - case ADDR_SW_VAR_D_X: surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY; break; - /* R = rotated. */ + /* R = rotated (gfx9), render target (gfx10). */ case ADDR_SW_256B_R: case ADDR_SW_4KB_R: case ADDR_SW_64KB_R: - case ADDR_SW_VAR_R: case ADDR_SW_64KB_R_T: case ADDR_SW_4KB_R_X: case ADDR_SW_64KB_R_X: case ADDR_SW_VAR_R_X: + /* The rotated micro tile mode doesn't work if both CMASK and RB+ are + * used at the same time. We currently do not use rotated + * in gfx9. + */ + assert(info->chip_class >= GFX10 || + !"rotate micro tile mode is unsupported"); surf->micro_tile_mode = RADEON_MICRO_MODE_ROTATED; break; /* Z = depth. */ case ADDR_SW_4KB_Z: case ADDR_SW_64KB_Z: - case ADDR_SW_VAR_Z: case ADDR_SW_64KB_Z_T: case ADDR_SW_4KB_Z_X: case ADDR_SW_64KB_Z_X: @@ -1389,11 +1660,12 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib, assert(0); } - /* Temporary workaround to prevent VM faults and hangs. */ - if (info->family == CHIP_VEGA12) - surf->u.gfx9.fmask_size *= 8; - return 0; + +error: + free(surf->u.gfx9.dcc_retile_map); + surf->u.gfx9.dcc_retile_map = NULL; + return r; } int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, @@ -1403,12 +1675,66 @@ int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, { int r; - r = surf_config_sanity(config); + r = surf_config_sanity(config, surf->flags); if (r) return r; if (info->chip_class >= GFX9) - return gfx9_compute_surface(addrlib, info, config, mode, surf); + r = gfx9_compute_surface(addrlib, info, config, mode, surf); else - return gfx6_compute_surface(addrlib, info, config, mode, surf); + r = gfx6_compute_surface(addrlib, info, config, mode, surf); + + if (r) + return r; + + /* Determine the memory layout of multiple allocations in one buffer. */ + surf->total_size = surf->surf_size; + + if (surf->htile_size) { + surf->htile_offset = align64(surf->total_size, surf->htile_alignment); + surf->total_size = surf->htile_offset + surf->htile_size; + } + + if (surf->fmask_size) { + assert(config->info.samples >= 2); + surf->fmask_offset = align64(surf->total_size, surf->fmask_alignment); + surf->total_size = surf->fmask_offset + surf->fmask_size; + } + + /* Single-sample CMASK is in a separate buffer. */ + if (surf->cmask_size && config->info.samples >= 2) { + surf->cmask_offset = align64(surf->total_size, surf->cmask_alignment); + surf->total_size = surf->cmask_offset + surf->cmask_size; + } + + if (surf->dcc_size && + (info->use_display_dcc_unaligned || + info->use_display_dcc_with_retile_blit || + !(surf->flags & RADEON_SURF_SCANOUT))) { + surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment); + surf->total_size = surf->dcc_offset + surf->dcc_size; + + if (info->chip_class >= GFX9 && + surf->u.gfx9.dcc_retile_num_elements) { + /* Add space for the displayable DCC buffer. */ + surf->display_dcc_offset = + align64(surf->total_size, surf->u.gfx9.display_dcc_alignment); + surf->total_size = surf->display_dcc_offset + + surf->u.gfx9.display_dcc_size; + + /* Add space for the DCC retile buffer. (16-bit or 32-bit elements) */ + surf->dcc_retile_map_offset = + align64(surf->total_size, info->tcc_cache_line_size); + + if (surf->u.gfx9.dcc_retile_use_uint16) { + surf->total_size = surf->dcc_retile_map_offset + + surf->u.gfx9.dcc_retile_num_elements * 2; + } else { + surf->total_size = surf->dcc_retile_map_offset + + surf->u.gfx9.dcc_retile_num_elements * 4; + } + } + } + + return 0; }