X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fcommon%2Fac_surface.h;h=5dce25365becc2d6564a838295af4676bbe97e14;hb=70375a9afb0800722509d4a09c94b8b959aeb3fc;hp=8143c9f9a0e8523c860a8c69e9c7723b1ea2ba00;hpb=6517d226acc8f07db7d730c727758e3a0f1e7cf8;p=mesa.git diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 8143c9f9a0e..5dce25365be 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -36,7 +36,7 @@ extern "C" { #endif /* Forward declarations. */ -typedef void* ADDR_HANDLE; +struct ac_addrlib; struct amdgpu_gpu_info; struct radeon_info; @@ -49,12 +49,14 @@ enum radeon_surf_mode { RADEON_SURF_MODE_2D = 3, }; -/* These are defined exactly like GB_TILE_MODEn.MICRO_TILE_MODE_NEW. */ +/* This describes D/S/Z/R swizzle modes. + * Defined in the GB_TILE_MODEn.MICRO_TILE_MODE_NEW order. + */ enum radeon_micro_mode { RADEON_MICRO_MODE_DISPLAY = 0, - RADEON_MICRO_MODE_THIN = 1, + RADEON_MICRO_MODE_STANDARD = 1, RADEON_MICRO_MODE_DEPTH = 2, - RADEON_MICRO_MODE_ROTATED = 3, + RADEON_MICRO_MODE_RENDER = 3, /* gfx9 and older: rotated */ }; /* the first 16 bits are reserved for libdrm_radeon, don't use them */ @@ -67,15 +69,22 @@ enum radeon_micro_mode { #define RADEON_SURF_DISABLE_DCC (1 << 22) #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23) #define RADEON_SURF_IMPORTED (1 << 24) -#define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25) +#define RADEON_SURF_CONTIGUOUS_DCC_LAYERS (1 << 25) #define RADEON_SURF_SHAREABLE (1 << 26) #define RADEON_SURF_NO_RENDER_TARGET (1 << 27) +/* Force a swizzle mode (gfx9+) or tile mode (gfx6-8). + * If this is not set, optimize for space. */ +#define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28) +#define RADEON_SURF_NO_FMASK (1 << 29) +#define RADEON_SURF_NO_HTILE (1 << 30) +#define RADEON_SURF_FORCE_MICRO_TILE_MODE (1u << 31) struct legacy_surf_level { uint64_t offset; uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */ uint32_t dcc_offset; /* relative offset within DCC mip tree */ uint32_t dcc_fast_clear_size; + uint32_t dcc_slice_fast_clear_size; unsigned nblk_x:15; unsigned nblk_y:15; enum radeon_surf_mode mode:2; @@ -130,6 +139,9 @@ struct gfx9_surf_flags { struct gfx9_surf_meta_flags { unsigned rb_aligned:1; /* optimal for RBs */ unsigned pipe_aligned:1; /* optimal for TC */ + unsigned independent_64B_blocks:1; + unsigned independent_128B_blocks:1; + unsigned max_compressed_block_size:2; }; struct gfx9_surf_layout { @@ -138,8 +150,6 @@ struct gfx9_surf_layout { struct gfx9_surf_flags stencil; /* added to surf_size, use stencil_offset */ struct gfx9_surf_meta_flags dcc; /* metadata of color */ - struct gfx9_surf_meta_flags htile; /* metadata of depth and stencil */ - struct gfx9_surf_meta_flags cmask; /* metadata of fmask */ enum gfx9_resource_type resource_type; /* 1D, 2D or 3D */ uint16_t surf_pitch; /* in blocks */ @@ -150,9 +160,15 @@ struct gfx9_surf_layout { uint64_t surf_slice_size; /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */ uint32_t offset[RADEON_SURF_MAX_LEVELS]; + /* Mipmap level pitch in elements. Only valid for LINEAR. */ + uint16_t pitch[RADEON_SURF_MAX_LEVELS]; uint64_t stencil_offset; /* separate stencil */ + uint8_t dcc_block_width; + uint8_t dcc_block_height; + uint8_t dcc_block_depth; + /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0. * The 3D engine doesn't support that layout except for chips with 1 RB. * All other chips must set rb_aligned=1. @@ -163,7 +179,7 @@ struct gfx9_surf_layout { uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */ bool dcc_retile_use_uint16; /* if all values fit into uint16_t */ uint32_t dcc_retile_num_elements; - uint32_t *dcc_retile_map; + void *dcc_retile_map; }; struct radeon_surf { @@ -223,6 +239,16 @@ struct radeon_surf { uint32_t cmask_slice_size; uint32_t cmask_alignment; + /* All buffers combined. */ + uint64_t htile_offset; + uint64_t fmask_offset; + uint64_t cmask_offset; + uint64_t dcc_offset; + uint64_t display_dcc_offset; + uint64_t dcc_retile_map_offset; + uint64_t total_size; + uint32_t alignment; + union { /* Return values for GFX8 and older. * @@ -251,18 +277,44 @@ struct ac_surf_info { struct ac_surf_config { struct ac_surf_info info; + unsigned is_1d : 1; unsigned is_3d : 1; unsigned is_cube : 1; }; -ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info, - const struct amdgpu_gpu_info *amdinfo, - uint64_t *max_alignment); +struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info, + const struct amdgpu_gpu_info *amdinfo, + uint64_t *max_alignment); +void ac_addrlib_destroy(struct ac_addrlib *addrlib); -int ac_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, +int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info, const struct ac_surf_config * config, enum radeon_surf_mode mode, struct radeon_surf *surf); +void ac_surface_zero_dcc_fields(struct radeon_surf *surf); + +void ac_surface_set_bo_metadata(const struct radeon_info *info, + struct radeon_surf *surf, uint64_t tiling_flags, + enum radeon_surf_mode *mode); +void ac_surface_get_bo_metadata(const struct radeon_info *info, + struct radeon_surf *surf, uint64_t *tiling_flags); + +bool ac_surface_set_umd_metadata(const struct radeon_info *info, + struct radeon_surf *surf, + unsigned num_storage_samples, + unsigned num_mipmap_levels, + unsigned size_metadata, + uint32_t metadata[64]); +void ac_surface_get_umd_metadata(const struct radeon_info *info, + struct radeon_surf *surf, + unsigned num_mipmap_levels, + uint32_t desc[8], + unsigned *size_metadata, uint32_t metadata[64]); + +void ac_surface_override_offset_stride(const struct radeon_info *info, + struct radeon_surf *surf, + unsigned num_mipmap_levels, + uint64_t offset, unsigned pitch); #ifdef __cplusplus }