X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fcompiler%2Faco_validate.cpp;h=97967aac9c190a1b8cdd2c09b2d0f3ef7d38c143;hb=1b3be07b5faf867f698668080b060a270c5f795e;hp=8d2bf8449db1a6e732d6b64f187ee50a6a537947;hpb=06fc83989c04368f14e004ba5543c6b5daa6c098;p=mesa.git

diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp
index 8d2bf8449db..97967aac9c1 100644
--- a/src/amd/compiler/aco_validate.cpp
+++ b/src/amd/compiler/aco_validate.cpp
@@ -46,11 +46,8 @@ void perfwarn(bool cond, const char *msg, Instruction *instr)
 }
 #endif
 
-void validate(Program* program, FILE * output)
+bool validate(Program* program, FILE *output)
 {
-   if (!(debug_flags & DEBUG_VALIDATE))
-      return;
-
    bool is_valid = true;
    auto check = [&output, &is_valid](bool check, const char * msg, aco::Instruction * instr) -> void {
       if (!check) {
@@ -80,8 +77,19 @@ void validate(Program* program, FILE * output)
             base_format = Format::VOP2;
          else if ((uint32_t)base_format & (uint32_t)Format::VOPC)
             base_format = Format::VOPC;
-         else if ((uint32_t)base_format & (uint32_t)Format::VINTRP)
-            base_format = Format::VINTRP;
+         else if ((uint32_t)base_format & (uint32_t)Format::VINTRP) {
+            if (instr->opcode == aco_opcode::v_interp_p1ll_f16 ||
+                instr->opcode == aco_opcode::v_interp_p1lv_f16 ||
+                instr->opcode == aco_opcode::v_interp_p2_legacy_f16 ||
+                instr->opcode == aco_opcode::v_interp_p2_f16) {
+               /* v_interp_*_fp16 are considered VINTRP by the compiler but
+                * they are emitted as VOP3.
+                */
+               base_format = Format::VOP3;
+            } else {
+               base_format = Format::VINTRP;
+            }
+         }
          check(base_format == instr_info.format[(int)instr->opcode], "Wrong base format for instruction", instr.get());
 
          /* check VOP3 modifiers */
@@ -93,63 +101,181 @@ void validate(Program* program, FILE * output)
                   "Format cannot have VOP3A/VOP3B applied", instr.get());
          }
 
+         /* check SDWA */
+         if (instr->isSDWA()) {
+            check(base_format == Format::VOP2 ||
+                  base_format == Format::VOP1 ||
+                  base_format == Format::VOPC,
+                  "Format cannot have SDWA applied", instr.get());
+
+            check(program->chip_class >= GFX8, "SDWA is GFX8+ only", instr.get());
+
+            SDWA_instruction *sdwa = static_cast<SDWA_instruction*>(instr.get());
+            check(sdwa->omod == 0 || program->chip_class >= GFX9, "SDWA omod only supported on GFX9+", instr.get());
+            if (base_format == Format::VOPC) {
+               check(sdwa->clamp == false || program->chip_class == GFX8, "SDWA VOPC clamp only supported on GFX8", instr.get());
+               check((instr->definitions[0].isFixed() && instr->definitions[0].physReg() == vcc) ||
+                     program->chip_class >= GFX9,
+                     "SDWA+VOPC definition must be fixed to vcc on GFX8", instr.get());
+            }
+
+            if (instr->operands.size() >= 3) {
+               check(instr->operands[2].isFixed() && instr->operands[2].physReg() == vcc,
+                     "3rd operand must be fixed to vcc with SDWA", instr.get());
+            }
+            if (instr->definitions.size() >= 2) {
+               check(instr->definitions[1].isFixed() && instr->definitions[1].physReg() == vcc,
+                     "2nd definition must be fixed to vcc with SDWA", instr.get());
+            }
+
+            check(instr->opcode != aco_opcode::v_madmk_f32 &&
+                  instr->opcode != aco_opcode::v_madak_f32 &&
+                  instr->opcode != aco_opcode::v_madmk_f16 &&
+                  instr->opcode != aco_opcode::v_madak_f16 &&
+                  instr->opcode != aco_opcode::v_readfirstlane_b32 &&
+                  instr->opcode != aco_opcode::v_clrexcp &&
+                  instr->opcode != aco_opcode::v_swap_b32,
+                  "SDWA can't be used with this opcode", instr.get());
+            if (program->chip_class != GFX8) {
+               check(instr->opcode != aco_opcode::v_mac_f32 &&
+                     instr->opcode != aco_opcode::v_mac_f16 &&
+                     instr->opcode != aco_opcode::v_fmac_f32 &&
+                     instr->opcode != aco_opcode::v_fmac_f16,
+                     "SDWA can't be used with this opcode", instr.get());
+            }
+
+            for (unsigned i = 0; i < MIN2(instr->operands.size(), 2); i++) {
+               if (instr->operands[i].hasRegClass() && instr->operands[i].regClass().is_subdword())
+                  check((sdwa->sel[i] & sdwa_asuint) == (sdwa_isra | instr->operands[i].bytes()), "Unexpected SDWA sel for sub-dword operand", instr.get());
+            }
+            if (instr->definitions[0].regClass().is_subdword())
+               check((sdwa->dst_sel & sdwa_asuint) == (sdwa_isra | instr->definitions[0].bytes()), "Unexpected SDWA sel for sub-dword definition", instr.get());
+         }
+
+         /* check opsel */
+         if (instr->isVOP3()) {
+            VOP3A_instruction *vop3 = static_cast<VOP3A_instruction*>(instr.get());
+            check(vop3->opsel == 0 || program->chip_class >= GFX9, "Opsel is only supported on GFX9+", instr.get());
+
+            for (unsigned i = 0; i < 3; i++) {
+               if (i >= instr->operands.size() ||
+                   (instr->operands[i].hasRegClass() && instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed()))
+                  check((vop3->opsel & (1 << i)) == 0, "Unexpected opsel for operand", instr.get());
+            }
+            if (instr->definitions[0].regClass().is_subdword() && !instr->definitions[0].isFixed())
+               check((vop3->opsel & (1 << 3)) == 0, "Unexpected opsel for sub-dword definition", instr.get());
+         }
+
          /* check for undefs */
          for (unsigned i = 0; i < instr->operands.size(); i++) {
             if (instr->operands[i].isUndefined()) {
                bool flat = instr->format == Format::FLAT || instr->format == Format::SCRATCH || instr->format == Format::GLOBAL;
                bool can_be_undef = is_phi(instr) || instr->format == Format::EXP ||
                                    instr->format == Format::PSEUDO_REDUCTION ||
-                                   (flat && i == 1) || (instr->format == Format::MIMG && i == 2) ||
-                                   ((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 0);
+                                   instr->opcode == aco_opcode::p_create_vector ||
+                                   (flat && i == 1) || (instr->format == Format::MIMG && i == 1) ||
+                                   ((instr->format == Format::MUBUF || instr->format == Format::MTBUF) && i == 1);
                check(can_be_undef, "Undefs can only be used in certain operands", instr.get());
+            } else {
+               check(instr->operands[i].isFixed() || instr->operands[i].isTemp() || instr->operands[i].isConstant(), "Uninitialized Operand", instr.get());
             }
          }
 
-         /* check num literals */
+         /* check subdword definitions */
+         for (unsigned i = 0; i < instr->definitions.size(); i++) {
+            if (instr->definitions[i].regClass().is_subdword())
+               check(instr->format == Format::PSEUDO || instr->definitions[i].bytes() <= 4, "Only Pseudo instructions can write subdword registers larger than 4 bytes", instr.get());
+         }
+
          if (instr->isSALU() || instr->isVALU()) {
-            unsigned num_literals = 0;
+            /* check literals */
+            Operand literal(s1);
             for (unsigned i = 0; i < instr->operands.size(); i++)
             {
-               if (instr->operands[i].isLiteral() && instr->isVOP3() && program->chip_class >= GFX10) {
-                  num_literals++;
-               } else if (instr->operands[i].isLiteral()) {
-                  check(instr->format == Format::SOP1 ||
-                        instr->format == Format::SOP2 ||
-                        instr->format == Format::SOPC ||
-                        instr->format == Format::VOP1 ||
-                        instr->format == Format::VOP2 ||
-                        instr->format == Format::VOPC,
-                        "Literal applied on wrong instruction format", instr.get());
-
-                  num_literals++;
-                  check(!instr->isVALU() || i == 0 || i == 2, "Wrong source position for Literal argument", instr.get());
-               }
+               Operand op = instr->operands[i];
+               if (!op.isLiteral())
+                  continue;
+
+               check(instr->format == Format::SOP1 ||
+                     instr->format == Format::SOP2 ||
+                     instr->format == Format::SOPC ||
+                     instr->format == Format::VOP1 ||
+                     instr->format == Format::VOP2 ||
+                     instr->format == Format::VOPC ||
+                     (instr->isVOP3() && program->chip_class >= GFX10),
+                     "Literal applied on wrong instruction format", instr.get());
+
+               check(literal.isUndefined() || (literal.size() == op.size() && literal.constantValue() == op.constantValue()), "Only 1 Literal allowed", instr.get());
+               literal = op;
+               check(!instr->isVALU() || instr->isVOP3() || i == 0 || i == 2, "Wrong source position for Literal argument", instr.get());
             }
-            check(num_literals <= 1, "Only 1 Literal allowed", instr.get());
 
             /* check num sgprs for VALU */
             if (instr->isVALU()) {
-               check(instr->definitions[0].getTemp().type() == RegType::vgpr ||
-                     (int) instr->format & (int) Format::VOPC ||
-                     instr->opcode == aco_opcode::v_readfirstlane_b32 ||
-                     instr->opcode == aco_opcode::v_readlane_b32,
-                     "Wrong Definition type for VALU instruction", instr.get());
-               unsigned num_sgpr = 0;
-               unsigned sgpr_idx = instr->operands.size();
+               bool is_shift64 = instr->opcode == aco_opcode::v_lshlrev_b64 ||
+                                 instr->opcode == aco_opcode::v_lshrrev_b64 ||
+                                 instr->opcode == aco_opcode::v_ashrrev_i64;
+               unsigned const_bus_limit = 1;
+               if (program->chip_class >= GFX10 && !is_shift64)
+                  const_bus_limit = 2;
+
+               uint32_t scalar_mask = instr->isVOP3() ? 0x7 : 0x5;
+               if (instr->isSDWA())
+                  scalar_mask = program->chip_class >= GFX9 ? 0x7 : 0x4;
+
+               if ((int) instr->format & (int) Format::VOPC ||
+                   instr->opcode == aco_opcode::v_readfirstlane_b32 ||
+                   instr->opcode == aco_opcode::v_readlane_b32 ||
+                   instr->opcode == aco_opcode::v_readlane_b32_e64) {
+                  check(instr->definitions[0].getTemp().type() == RegType::sgpr,
+                        "Wrong Definition type for VALU instruction", instr.get());
+               } else {
+                  check(instr->definitions[0].getTemp().type() == RegType::vgpr,
+                        "Wrong Definition type for VALU instruction", instr.get());
+               }
+
+               unsigned num_sgprs = 0;
+               unsigned sgpr[] = {0, 0};
                for (unsigned i = 0; i < instr->operands.size(); i++)
                {
-                  if (instr->operands[i].isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
-                     check(i != 1 || (int) instr->format & (int) Format::VOP3A, "Wrong source position for SGPR argument", instr.get());
+                  Operand op = instr->operands[i];
+                  if (instr->opcode == aco_opcode::v_readfirstlane_b32 ||
+                      instr->opcode == aco_opcode::v_readlane_b32 ||
+                      instr->opcode == aco_opcode::v_readlane_b32_e64) {
+                     check(i != 1 ||
+                           (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
+                           op.isConstant(),
+                           "Must be a SGPR or a constant", instr.get());
+                     check(i == 1 ||
+                           (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4),
+                           "Wrong Operand type for VALU instruction", instr.get());
+                     continue;
+                  }
 
-                     if (sgpr_idx == instr->operands.size() || instr->operands[sgpr_idx].tempId() != instr->operands[i].tempId())
-                        num_sgpr++;
-                     sgpr_idx = i;
+                  if (instr->opcode == aco_opcode::v_writelane_b32 ||
+                      instr->opcode == aco_opcode::v_writelane_b32_e64) {
+                     check(i != 2 ||
+                           (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4),
+                           "Wrong Operand type for VALU instruction", instr.get());
+                     check(i == 2 ||
+                           (op.isTemp() && op.regClass().type() == RegType::sgpr) ||
+                           op.isConstant(),
+                           "Must be a SGPR or a constant", instr.get());
+                     continue;
                   }
+                  if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) {
+                     check(scalar_mask & (1 << i), "Wrong source position for SGPR argument", instr.get());
 
-                  if (instr->operands[i].isConstant() && !instr->operands[i].isLiteral())
-                     check(i == 0 || (int) instr->format & (int) Format::VOP3A, "Wrong source position for constant argument", instr.get());
+                     if (op.tempId() != sgpr[0] && op.tempId() != sgpr[1]) {
+                        if (num_sgprs < 2)
+                           sgpr[num_sgprs++] = op.tempId();
+                     }
+                  }
+
+                  if (op.isConstant() && !op.isLiteral())
+                     check(scalar_mask & (1 << i), "Wrong source position for constant argument", instr.get());
                }
-               check(num_sgpr + num_literals <= 1, "Only 1 Literal OR 1 SGPR allowed", instr.get());
+               check(num_sgprs + (literal.isUndefined() ? 0 : 1) <= const_bus_limit, "Too many SGPRs/literals", instr.get());
             }
 
             if (instr->format == Format::SOP1 || instr->format == Format::SOP2) {
@@ -163,12 +289,30 @@ void validate(Program* program, FILE * output)
 
          switch (instr->format) {
          case Format::PSEUDO: {
+            bool is_subdword = false;
+            bool has_const_sgpr = false;
+            bool has_literal = false;
+            for (Definition def : instr->definitions)
+               is_subdword |= def.regClass().is_subdword();
+            for (unsigned i = 0; i < instr->operands.size(); i++) {
+               if (instr->opcode == aco_opcode::p_extract_vector && i == 1)
+                  continue;
+               Operand op = instr->operands[i];
+               is_subdword |= op.hasRegClass() && op.regClass().is_subdword();
+               has_const_sgpr |= op.isConstant() || (op.hasRegClass() && op.regClass().type() == RegType::sgpr);
+               has_literal |= op.isLiteral();
+            }
+
+            check(!is_subdword || !has_const_sgpr || program->chip_class >= GFX9,
+                  "Sub-dword pseudo instructions can only take constants or SGPRs on GFX9+", instr.get());
+            check(!is_subdword || !has_literal, "Sub-dword pseudo instructions cannot take literals", instr.get());
+
             if (instr->opcode == aco_opcode::p_create_vector) {
                unsigned size = 0;
                for (const Operand& op : instr->operands) {
-                  size += op.size();
+                  size += op.bytes();
                }
-               check(size == instr->definitions[0].size(), "Definition size does not match operand sizes", instr.get());
+               check(size == instr->definitions[0].bytes(), "Definition size does not match operand sizes", instr.get());
                if (instr->definitions[0].getTemp().type() == RegType::sgpr) {
                   for (const Operand& op : instr->operands) {
                      check(op.isConstant() || op.regClass().type() == RegType::sgpr,
@@ -177,7 +321,7 @@ void validate(Program* program, FILE * output)
                }
             } else if (instr->opcode == aco_opcode::p_extract_vector) {
                check((instr->operands[0].isTemp()) && instr->operands[1].isConstant(), "Wrong Operand types", instr.get());
-               check(instr->operands[1].constantValue() < instr->operands[0].size(), "Index out of range", instr.get());
+               check((instr->operands[1].constantValue() + 1) * instr->definitions[0].bytes() <= instr->operands[0].bytes(), "Index out of range", instr.get());
                check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->operands[0].regClass().type() == RegType::sgpr,
                      "Cannot extract SGPR value from VGPR vector", instr.get());
             } else if (instr->opcode == aco_opcode::p_parallelcopy) {
@@ -190,7 +334,7 @@ void validate(Program* program, FILE * output)
                }
             } else if (instr->opcode == aco_opcode::p_phi) {
                check(instr->operands.size() == block.logical_preds.size(), "Number of Operands does not match number of predecessors", instr.get());
-               check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->definitions[0].getTemp().regClass() == s2, "Logical Phi Definition must be vgpr or divergent boolean", instr.get());
+               check(instr->definitions[0].getTemp().type() == RegType::vgpr, "Logical Phi Definition must be vgpr", instr.get());
             } else if (instr->opcode == aco_opcode::p_linear_phi) {
                for (const Operand& op : instr->operands)
                   check(!op.isTemp() || op.getTemp().is_linear(), "Wrong Operand type", instr.get());
@@ -209,15 +353,30 @@ void validate(Program* program, FILE * output)
             break;
          }
          case Format::MTBUF:
-         case Format::MUBUF:
-         case Format::MIMG: {
+         case Format::MUBUF: {
             check(instr->operands.size() > 1, "VMEM instructions must have at least one operand", instr.get());
-            check(instr->operands[0].hasRegClass() && instr->operands[0].regClass().type() == RegType::vgpr,
+            check(instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr,
                   "VADDR must be in vgpr for VMEM instructions", instr.get());
-            check(instr->operands[1].isTemp() && instr->operands[1].regClass().type() == RegType::sgpr, "VMEM resource constant must be sgpr", instr.get());
+            check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "VMEM resource constant must be sgpr", instr.get());
             check(instr->operands.size() < 4 || (instr->operands[3].isTemp() && instr->operands[3].regClass().type() == RegType::vgpr), "VMEM write data must be vgpr", instr.get());
             break;
          }
+         case Format::MIMG: {
+            check(instr->operands.size() == 3, "MIMG instructions must have exactly 3 operands", instr.get());
+            check(instr->operands[0].hasRegClass() && (instr->operands[0].regClass() == s4 || instr->operands[0].regClass() == s8),
+                  "MIMG operands[0] (resource constant) must be in 4 or 8 SGPRs", instr.get());
+            if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::sgpr)
+               check(instr->operands[1].regClass() == s4, "MIMG operands[1] (sampler constant) must be 4 SGPRs", instr.get());
+            else if (instr->operands[1].hasRegClass() && instr->operands[1].regClass().type() == RegType::vgpr)
+               check((instr->definitions.empty() || instr->definitions[0].regClass() == instr->operands[1].regClass() ||
+                     instr->opcode == aco_opcode::image_atomic_cmpswap || instr->opcode == aco_opcode::image_atomic_fcmpswap),
+                     "MIMG operands[1] (VDATA) must be the same as definitions[0] for atomics", instr.get());
+            check(instr->operands[2].hasRegClass() && instr->operands[2].regClass().type() == RegType::vgpr,
+                  "MIMG operands[2] (VADDR) must be VGPR", instr.get());
+            check(instr->definitions.empty() || (instr->definitions[0].isTemp() && instr->definitions[0].regClass().type() == RegType::vgpr),
+                  "MIMG definitions[0] (VDATA) must be VGPR", instr.get());
+            break;
+         }
          case Format::DS: {
             for (const Operand& op : instr->operands) {
                check((op.isTemp() && op.regClass().type() == RegType::vgpr) || op.physReg() == m0,
@@ -277,7 +436,7 @@ void validate(Program* program, FILE * output)
       }
    }
 
-   assert(is_valid);
+   return is_valid;
 }
 
 /* RA validation */
@@ -319,6 +478,136 @@ bool ra_fail(FILE *output, Location loc, Location loc2, const char *fmt, ...) {
    return true;
 }
 
+bool validate_subdword_operand(chip_class chip, const aco_ptr<Instruction>& instr, unsigned index)
+{
+   Operand op = instr->operands[index];
+   unsigned byte = op.physReg().byte();
+
+   if (instr->opcode == aco_opcode::p_as_uniform)
+      return byte == 0;
+   if (instr->format == Format::PSEUDO && chip >= GFX8)
+      return true;
+   if (instr->isSDWA() && (static_cast<SDWA_instruction *>(instr.get())->sel[index] & sdwa_asuint) == (sdwa_isra | op.bytes()))
+      return true;
+   if (byte == 2 && can_use_opsel(chip, instr->opcode, index, 1))
+      return true;
+
+   switch (instr->opcode) {
+   case aco_opcode::v_cvt_f32_ubyte1:
+      if (byte == 1)
+         return true;
+      break;
+   case aco_opcode::v_cvt_f32_ubyte2:
+      if (byte == 2)
+         return true;
+      break;
+   case aco_opcode::v_cvt_f32_ubyte3:
+      if (byte == 3)
+         return true;
+      break;
+   case aco_opcode::ds_write_b8_d16_hi:
+   case aco_opcode::ds_write_b16_d16_hi:
+      if (byte == 2 && index == 1)
+         return true;
+      break;
+   case aco_opcode::buffer_store_byte_d16_hi:
+   case aco_opcode::buffer_store_short_d16_hi:
+      if (byte == 2 && index == 3)
+         return true;
+      break;
+   case aco_opcode::flat_store_byte_d16_hi:
+   case aco_opcode::flat_store_short_d16_hi:
+   case aco_opcode::scratch_store_byte_d16_hi:
+   case aco_opcode::scratch_store_short_d16_hi:
+   case aco_opcode::global_store_byte_d16_hi:
+   case aco_opcode::global_store_short_d16_hi:
+      if (byte == 2 && index == 2)
+         return true;
+   default:
+      break;
+   }
+
+   return byte == 0;
+}
+
+bool validate_subdword_definition(chip_class chip, const aco_ptr<Instruction>& instr)
+{
+   Definition def = instr->definitions[0];
+   unsigned byte = def.physReg().byte();
+
+   if (instr->format == Format::PSEUDO && chip >= GFX8)
+      return true;
+   if (instr->isSDWA() && static_cast<SDWA_instruction *>(instr.get())->dst_sel == (sdwa_isra | def.bytes()))
+      return true;
+   if (byte == 2 && can_use_opsel(chip, instr->opcode, -1, 1))
+      return true;
+
+   switch (instr->opcode) {
+   case aco_opcode::buffer_load_ubyte_d16_hi:
+   case aco_opcode::buffer_load_short_d16_hi:
+   case aco_opcode::flat_load_ubyte_d16_hi:
+   case aco_opcode::flat_load_short_d16_hi:
+   case aco_opcode::scratch_load_ubyte_d16_hi:
+   case aco_opcode::scratch_load_short_d16_hi:
+   case aco_opcode::global_load_ubyte_d16_hi:
+   case aco_opcode::global_load_short_d16_hi:
+   case aco_opcode::ds_read_u8_d16_hi:
+   case aco_opcode::ds_read_u16_d16_hi:
+      return byte == 2;
+   default:
+      break;
+   }
+
+   return byte == 0;
+}
+
+unsigned get_subdword_bytes_written(Program *program, const aco_ptr<Instruction>& instr, unsigned index)
+{
+   chip_class chip = program->chip_class;
+   Definition def = instr->definitions[index];
+
+   if (instr->format == Format::PSEUDO)
+      return chip >= GFX8 ? def.bytes() : def.size() * 4u;
+   if (instr->isSDWA() && static_cast<SDWA_instruction *>(instr.get())->dst_sel == (sdwa_isra | def.bytes()))
+      return def.bytes();
+
+   switch (instr->opcode) {
+   case aco_opcode::buffer_load_ubyte_d16:
+   case aco_opcode::buffer_load_short_d16:
+   case aco_opcode::flat_load_ubyte_d16:
+   case aco_opcode::flat_load_short_d16:
+   case aco_opcode::scratch_load_ubyte_d16:
+   case aco_opcode::scratch_load_short_d16:
+   case aco_opcode::global_load_ubyte_d16:
+   case aco_opcode::global_load_short_d16:
+   case aco_opcode::ds_read_u8_d16:
+   case aco_opcode::ds_read_u16_d16:
+   case aco_opcode::buffer_load_ubyte_d16_hi:
+   case aco_opcode::buffer_load_short_d16_hi:
+   case aco_opcode::flat_load_ubyte_d16_hi:
+   case aco_opcode::flat_load_short_d16_hi:
+   case aco_opcode::scratch_load_ubyte_d16_hi:
+   case aco_opcode::scratch_load_short_d16_hi:
+   case aco_opcode::global_load_ubyte_d16_hi:
+   case aco_opcode::global_load_short_d16_hi:
+   case aco_opcode::ds_read_u8_d16_hi:
+   case aco_opcode::ds_read_u16_d16_hi:
+      return program->sram_ecc_enabled ? 4 : 2;
+   case aco_opcode::v_mad_f16:
+   case aco_opcode::v_mad_u16:
+   case aco_opcode::v_mad_i16:
+   case aco_opcode::v_fma_f16:
+   case aco_opcode::v_div_fixup_f16:
+   case aco_opcode::v_interp_p2_f16:
+      if (chip >= GFX9)
+         return 2;
+   default:
+      break;
+   }
+
+   return MAX2(chip >= GFX10 ? def.bytes() : 4, instr_info.definition_size[(int)instr->opcode] / 8u);
+}
+
 } /* end namespace */
 
 bool validate_ra(Program *program, const struct radv_nir_compiler_options *options, FILE *output) {
@@ -352,9 +641,13 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio
                err |= ra_fail(output, loc, Location(), "Operand %d is not assigned a register", i);
             if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg())
                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an inconsistent register assignment with instruction", i);
-            if ((op.getTemp().type() == RegType::vgpr && op.physReg() + op.size() > 256 + program->config->num_vgprs) ||
+            if ((op.getTemp().type() == RegType::vgpr && op.physReg().reg_b + op.bytes() > (256 + program->config->num_vgprs) * 4) ||
                 (op.getTemp().type() == RegType::sgpr && op.physReg() + op.size() > program->config->num_sgprs && op.physReg() < program->sgpr_limit))
                err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an out-of-bounds register assignment", i);
+            if (op.physReg() == vcc && !program->needs_vcc)
+               err |= ra_fail(output, loc, Location(), "Operand %d fixed to vcc but needs_vcc=false", i);
+            if (op.regClass().is_subdword() && !validate_subdword_operand(program->chip_class, instr, i))
+               err |= ra_fail(output, loc, Location(), "Operand %d not aligned correctly", i);
             if (!assignments[op.tempId()].firstloc.block)
                assignments[op.tempId()].firstloc = loc;
             if (!assignments[op.tempId()].defloc.block)
@@ -369,9 +662,13 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio
                err |= ra_fail(output, loc, Location(), "Definition %d is not assigned a register", i);
             if (assignments[def.tempId()].defloc.block)
                err |= ra_fail(output, loc, assignments.at(def.tempId()).defloc, "Temporary %%%d also defined by instruction", def.tempId());
-            if ((def.getTemp().type() == RegType::vgpr && def.physReg() + def.size() > 256 + program->config->num_vgprs) ||
+            if ((def.getTemp().type() == RegType::vgpr && def.physReg().reg_b + def.bytes() > (256 + program->config->num_vgprs) * 4) ||
                 (def.getTemp().type() == RegType::sgpr && def.physReg() + def.size() > program->config->num_sgprs && def.physReg() < program->sgpr_limit))
                err |= ra_fail(output, loc, assignments.at(def.tempId()).firstloc, "Definition %d has an out-of-bounds register assignment", i);
+            if (def.physReg() == vcc && !program->needs_vcc)
+               err |= ra_fail(output, loc, Location(), "Definition %d fixed to vcc but needs_vcc=false", i);
+            if (def.regClass().is_subdword() && !validate_subdword_definition(program->chip_class, instr))
+               err |= ra_fail(output, loc, Location(), "Definition %d not aligned correctly", i);
             if (!assignments[def.tempId()].firstloc.block)
                assignments[def.tempId()].firstloc = loc;
             assignments[def.tempId()].defloc = loc;
@@ -384,7 +681,7 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio
       Location loc;
       loc.block = &block;
 
-      std::array<unsigned, 512> regs;
+      std::array<unsigned, 2048> regs; /* register file in bytes */
       regs.fill(0);
 
       std::set<Temp> live;
@@ -396,11 +693,11 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio
       /* check live out */
       for (Temp tmp : live) {
          PhysReg reg = assignments.at(tmp.id()).reg;
-         for (unsigned i = 0; i < tmp.size(); i++) {
-            if (regs[reg + i]) {
-               err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg + i]);
+         for (unsigned i = 0; i < tmp.bytes(); i++) {
+            if (regs[reg.reg_b + i]) {
+               err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]);
             }
-            regs[reg + i] = tmp.id();
+            regs[reg.reg_b + i] = tmp.id();
          }
       }
       regs.fill(0);
@@ -412,9 +709,9 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio
          if (instr->opcode == aco_opcode::p_logical_end) {
             for (Temp tmp : phi_sgpr_ops[block.index]) {
                PhysReg reg = assignments.at(tmp.id()).reg;
-               for (unsigned i = 0; i < tmp.size(); i++) {
-                  if (regs[reg + i])
-                     err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg + i]);
+               for (unsigned i = 0; i < tmp.bytes(); i++) {
+                  if (regs[reg.reg_b + i])
+                     err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]);
                }
                live.emplace(tmp);
             }
@@ -439,8 +736,8 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio
 
       for (Temp tmp : live) {
          PhysReg reg = assignments.at(tmp.id()).reg;
-         for (unsigned i = 0; i < tmp.size(); i++)
-            regs[reg + i] = tmp.id();
+         for (unsigned i = 0; i < tmp.bytes(); i++)
+            regs[reg.reg_b + i] = tmp.id();
       }
 
       for (aco_ptr<Instruction>& instr : block.instructions) {
@@ -450,7 +747,8 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio
          if (instr->opcode == aco_opcode::p_logical_end) {
             for (Temp tmp : phi_sgpr_ops[block.index]) {
                PhysReg reg = assignments.at(tmp.id()).reg;
-               regs[reg] = 0;
+               for (unsigned i = 0; i < tmp.bytes(); i++)
+                  regs[reg.reg_b + i] = 0;
             }
          }
 
@@ -458,9 +756,9 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio
             for (const Operand& op : instr->operands) {
                if (!op.isTemp())
                   continue;
-               if (op.isFirstKill()) {
-                  for (unsigned j = 0; j < op.getTemp().size(); j++)
-                     regs[op.physReg() + j] = 0;
+               if (op.isFirstKillBeforeDef()) {
+                  for (unsigned j = 0; j < op.getTemp().bytes(); j++)
+                     regs[op.physReg().reg_b + j] = 0;
                }
             }
          }
@@ -471,10 +769,19 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio
                continue;
             Temp tmp = def.getTemp();
             PhysReg reg = assignments.at(tmp.id()).reg;
-            for (unsigned j = 0; j < tmp.size(); j++) {
-               if (regs[reg + j])
-                  err |= ra_fail(output, loc, assignments.at(regs[reg + i]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg + j]);
-               regs[reg + j] = tmp.id();
+            for (unsigned j = 0; j < tmp.bytes(); j++) {
+               if (regs[reg.reg_b + j])
+                  err |= ra_fail(output, loc, assignments.at(regs[reg.reg_b + j]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg.reg_b + j]);
+               regs[reg.reg_b + j] = tmp.id();
+            }
+            if (def.regClass().is_subdword() && def.bytes() < 4) {
+               unsigned written = get_subdword_bytes_written(program, instr, i);
+               /* If written=4, the instruction still might write the upper half. In that case, it's the lower half that isn't preserved */
+               for (unsigned j = reg.byte() & ~(written - 1); j < written; j++) {
+                  unsigned written_reg = reg.reg() * 4u + j;
+                  if (regs[written_reg] && regs[written_reg] != def.tempId())
+                     err |= ra_fail(output, loc, assignments.at(regs[written_reg]).defloc, "Assignment of element %d of %%%d overwrites the full register taken by %%%d from instruction", i, tmp.id(), regs[written_reg]);
+               }
             }
          }
 
@@ -482,8 +789,19 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio
             if (!def.isTemp())
                continue;
             if (def.isKill()) {
-               for (unsigned j = 0; j < def.getTemp().size(); j++)
-                  regs[def.physReg() + j] = 0;
+               for (unsigned j = 0; j < def.getTemp().bytes(); j++)
+                  regs[def.physReg().reg_b + j] = 0;
+            }
+         }
+
+         if (instr->opcode != aco_opcode::p_phi && instr->opcode != aco_opcode::p_linear_phi) {
+            for (const Operand& op : instr->operands) {
+               if (!op.isTemp())
+                  continue;
+               if (op.isLateKill() && op.isFirstKill()) {
+                  for (unsigned j = 0; j < op.getTemp().bytes(); j++)
+                     regs[op.physReg().reg_b + j] = 0;
+               }
             }
          }
       }