X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fcompiler%2Faco_validate.cpp;h=fce0e1a1189e920b8f017bf77f0b569346711230;hb=6b75262941b55960e2f73d93f85020fa6c9c2d2f;hp=6d7c0c3e7948e92dad550846232167c1bf9cf882;hpb=d9cfb8ad483ed9ef182c62b5fac55f5e356540a2;p=mesa.git diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp index 6d7c0c3e794..fce0e1a1189 100644 --- a/src/amd/compiler/aco_validate.cpp +++ b/src/amd/compiler/aco_validate.cpp @@ -29,40 +29,71 @@ namespace aco { -#ifndef NDEBUG -void perfwarn(bool cond, const char *msg, Instruction *instr) +static void aco_log(Program *program, enum radv_compiler_debug_level level, + const char *prefix, const char *file, unsigned line, + const char *fmt, va_list args) { - if (cond) { - fprintf(stderr, "ACO performance warning: %s\n", msg); - if (instr) { - fprintf(stderr, "instruction: "); - aco_print_instr(instr, stderr); - fprintf(stderr, "\n"); - } + char *msg; - if (debug_flags & DEBUG_PERFWARN) - exit(1); - } + msg = ralloc_strdup(NULL, prefix); + + ralloc_asprintf_append(&msg, " In file %s:%u\n", file, line); + ralloc_asprintf_append(&msg, " "); + ralloc_vasprintf_append(&msg, fmt, args); + + if (program->debug.func) + program->debug.func(program->debug.private_data, level, msg); + + fprintf(stderr, "%s\n", msg); + + ralloc_free(msg); } -#endif -void validate(Program* program, FILE * output) +void _aco_perfwarn(Program *program, const char *file, unsigned line, + const char *fmt, ...) { - if (!(debug_flags & DEBUG_VALIDATE)) - return; + va_list args; + va_start(args, fmt); + aco_log(program, RADV_COMPILER_DEBUG_LEVEL_PERFWARN, + "ACO PERFWARN:\n", file, line, fmt, args); + va_end(args); +} + +void _aco_err(Program *program, const char *file, unsigned line, + const char *fmt, ...) +{ + va_list args; + + va_start(args, fmt); + aco_log(program, RADV_COMPILER_DEBUG_LEVEL_ERROR, + "ACO ERROR:\n", file, line, fmt, args); + va_end(args); +} + +bool validate_ir(Program* program) +{ bool is_valid = true; - auto check = [&output, &is_valid](bool check, const char * msg, aco::Instruction * instr) -> void { + auto check = [&program, &is_valid](bool check, const char * msg, aco::Instruction * instr) -> void { if (!check) { - fprintf(output, "%s: ", msg); - aco_print_instr(instr, output); - fprintf(output, "\n"); + char *out; + size_t outsize; + FILE *memf = open_memstream(&out, &outsize); + + fprintf(memf, "%s: ", msg); + aco_print_instr(instr, memf); + fclose(memf); + + aco_err(program, out); + free(out); + is_valid = false; } }; - auto check_block = [&output, &is_valid](bool check, const char * msg, aco::Block * block) -> void { + + auto check_block = [&program, &is_valid](bool check, const char * msg, aco::Block * block) -> void { if (!check) { - fprintf(output, "%s: BB%u\n", msg, block->index); + aco_err(program, "%s: BB%u", msg, block->index); is_valid = false; } }; @@ -148,7 +179,7 @@ void validate(Program* program, FILE * output) } for (unsigned i = 0; i < MIN2(instr->operands.size(), 2); i++) { - if (instr->operands[i].regClass().is_subdword()) + if (instr->operands[i].hasRegClass() && instr->operands[i].regClass().is_subdword()) check((sdwa->sel[i] & sdwa_asuint) == (sdwa_isra | instr->operands[i].bytes()), "Unexpected SDWA sel for sub-dword operand", instr.get()); } if (instr->definitions[0].regClass().is_subdword()) @@ -159,13 +190,13 @@ void validate(Program* program, FILE * output) if (instr->isVOP3()) { VOP3A_instruction *vop3 = static_cast(instr.get()); check(vop3->opsel == 0 || program->chip_class >= GFX9, "Opsel is only supported on GFX9+", instr.get()); - check((vop3->opsel & ~(0x10 | ((1 << instr->operands.size()) - 1))) == 0, "Unused bits in opsel must be zeroed out", instr.get()); - for (unsigned i = 0; i < instr->operands.size(); i++) { - if (instr->operands[i].regClass().is_subdword()) - check((vop3->opsel & (1 << i)) == 0, "Unexpected opsel for sub-dword operand", instr.get()); + for (unsigned i = 0; i < 3; i++) { + if (i >= instr->operands.size() || + (instr->operands[i].hasRegClass() && instr->operands[i].regClass().is_subdword() && !instr->operands[i].isFixed())) + check((vop3->opsel & (1 << i)) == 0, "Unexpected opsel for operand", instr.get()); } - if (instr->definitions[0].regClass().is_subdword()) + if (instr->definitions[0].regClass().is_subdword() && !instr->definitions[0].isFixed()) check((vop3->opsel & (1 << 3)) == 0, "Unexpected opsel for sub-dword definition", instr.get()); } @@ -226,12 +257,17 @@ void validate(Program* program, FILE * output) if (instr->isSDWA()) scalar_mask = program->chip_class >= GFX9 ? 0x7 : 0x4; - check(instr->definitions[0].getTemp().type() == RegType::vgpr || - (int) instr->format & (int) Format::VOPC || - instr->opcode == aco_opcode::v_readfirstlane_b32 || - instr->opcode == aco_opcode::v_readlane_b32 || - instr->opcode == aco_opcode::v_readlane_b32_e64, - "Wrong Definition type for VALU instruction", instr.get()); + if ((int) instr->format & (int) Format::VOPC || + instr->opcode == aco_opcode::v_readfirstlane_b32 || + instr->opcode == aco_opcode::v_readlane_b32 || + instr->opcode == aco_opcode::v_readlane_b32_e64) { + check(instr->definitions[0].getTemp().type() == RegType::sgpr, + "Wrong Definition type for VALU instruction", instr.get()); + } else { + check(instr->definitions[0].getTemp().type() == RegType::vgpr, + "Wrong Definition type for VALU instruction", instr.get()); + } + unsigned num_sgprs = 0; unsigned sgpr[] = {0, 0}; for (unsigned i = 0; i < instr->operands.size(); i++) @@ -239,11 +275,26 @@ void validate(Program* program, FILE * output) Operand op = instr->operands[i]; if (instr->opcode == aco_opcode::v_readfirstlane_b32 || instr->opcode == aco_opcode::v_readlane_b32 || - instr->opcode == aco_opcode::v_readlane_b32_e64 || - instr->opcode == aco_opcode::v_writelane_b32 || + instr->opcode == aco_opcode::v_readlane_b32_e64) { + check(i != 1 || + (op.isTemp() && op.regClass().type() == RegType::sgpr) || + op.isConstant(), + "Must be a SGPR or a constant", instr.get()); + check(i == 1 || + (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4), + "Wrong Operand type for VALU instruction", instr.get()); + continue; + } + + if (instr->opcode == aco_opcode::v_writelane_b32 || instr->opcode == aco_opcode::v_writelane_b32_e64) { - check(!op.isLiteral(), "No literal allowed on VALU instruction", instr.get()); - check(i == 1 || (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4), "Wrong Operand type for VALU instruction", instr.get()); + check(i != 2 || + (op.isTemp() && op.regClass().type() == RegType::vgpr && op.bytes() <= 4), + "Wrong Operand type for VALU instruction", instr.get()); + check(i == 2 || + (op.isTemp() && op.regClass().type() == RegType::sgpr) || + op.isConstant(), + "Must be a SGPR or a constant", instr.get()); continue; } if (op.isTemp() && instr->operands[i].regClass().type() == RegType::sgpr) { @@ -272,6 +323,24 @@ void validate(Program* program, FILE * output) switch (instr->format) { case Format::PSEUDO: { + bool is_subdword = false; + bool has_const_sgpr = false; + bool has_literal = false; + for (Definition def : instr->definitions) + is_subdword |= def.regClass().is_subdword(); + for (unsigned i = 0; i < instr->operands.size(); i++) { + if (instr->opcode == aco_opcode::p_extract_vector && i == 1) + continue; + Operand op = instr->operands[i]; + is_subdword |= op.hasRegClass() && op.regClass().is_subdword(); + has_const_sgpr |= op.isConstant() || (op.hasRegClass() && op.regClass().type() == RegType::sgpr); + has_literal |= op.isLiteral(); + } + + check(!is_subdword || !has_const_sgpr || program->chip_class >= GFX9, + "Sub-dword pseudo instructions can only take constants or SGPRs on GFX9+", instr.get()); + check(!is_subdword || !has_literal, "Sub-dword pseudo instructions cannot take literals", instr.get()); + if (instr->opcode == aco_opcode::p_create_vector) { unsigned size = 0; for (const Operand& op : instr->operands) { @@ -299,7 +368,7 @@ void validate(Program* program, FILE * output) } } else if (instr->opcode == aco_opcode::p_phi) { check(instr->operands.size() == block.logical_preds.size(), "Number of Operands does not match number of predecessors", instr.get()); - check(instr->definitions[0].getTemp().type() == RegType::vgpr || instr->definitions[0].getTemp().regClass() == program->lane_mask, "Logical Phi Definition must be vgpr or divergent boolean", instr.get()); + check(instr->definitions[0].getTemp().type() == RegType::vgpr, "Logical Phi Definition must be vgpr", instr.get()); } else if (instr->opcode == aco_opcode::p_linear_phi) { for (const Operand& op : instr->operands) check(!op.isTemp() || op.getTemp().is_linear(), "Wrong Operand type", instr.get()); @@ -309,7 +378,8 @@ void validate(Program* program, FILE * output) } case Format::SMEM: { if (instr->operands.size() >= 1) - check(instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr, "SMEM operands must be sgpr", instr.get()); + check((instr->operands[0].isFixed() && !instr->operands[0].isConstant()) || + (instr->operands[0].isTemp() && instr->operands[0].regClass().type() == RegType::sgpr), "SMEM operands must be sgpr", instr.get()); if (instr->operands.size() >= 2) check(instr->operands[1].isConstant() || (instr->operands[1].isTemp() && instr->operands[1].regClass().type() == RegType::sgpr), "SMEM offset must be constant or sgpr", instr.get()); @@ -401,7 +471,7 @@ void validate(Program* program, FILE * output) } } - assert(is_valid); + return is_valid; } /* RA validation */ @@ -420,25 +490,33 @@ struct Assignment { PhysReg reg; }; -bool ra_fail(FILE *output, Location loc, Location loc2, const char *fmt, ...) { +bool ra_fail(Program *program, Location loc, Location loc2, const char *fmt, ...) { va_list args; va_start(args, fmt); char msg[1024]; vsprintf(msg, fmt, args); va_end(args); - fprintf(stderr, "RA error found at instruction in BB%d:\n", loc.block->index); + char *out; + size_t outsize; + FILE *memf = open_memstream(&out, &outsize); + + fprintf(memf, "RA error found at instruction in BB%d:\n", loc.block->index); if (loc.instr) { - aco_print_instr(loc.instr, stderr); - fprintf(stderr, "\n%s", msg); + aco_print_instr(loc.instr, memf); + fprintf(memf, "\n%s", msg); } else { - fprintf(stderr, "%s", msg); + fprintf(memf, "%s", msg); } if (loc2.block) { - fprintf(stderr, " in BB%d:\n", loc2.block->index); - aco_print_instr(loc2.instr, stderr); + fprintf(memf, " in BB%d:\n", loc2.block->index); + aco_print_instr(loc2.instr, memf); } - fprintf(stderr, "\n\n"); + fprintf(memf, "\n\n"); + fclose(memf); + + aco_err(program, out); + free(out); return true; } @@ -448,6 +526,8 @@ bool validate_subdword_operand(chip_class chip, const aco_ptr& inst Operand op = instr->operands[index]; unsigned byte = op.physReg().byte(); + if (instr->opcode == aco_opcode::p_as_uniform) + return byte == 0; if (instr->format == Format::PSEUDO && chip >= GFX8) return true; if (instr->isSDWA() && (static_cast(instr.get())->sel[index] & sdwa_asuint) == (sdwa_isra | op.bytes())) @@ -568,12 +648,12 @@ unsigned get_subdword_bytes_written(Program *program, const aco_ptr break; } - return chip >= GFX10 ? def.bytes() : 4; + return MAX2(chip >= GFX10 ? def.bytes() : 4, instr_info.definition_size[(int)instr->opcode] / 8u); } } /* end namespace */ -bool validate_ra(Program *program, const struct radv_nir_compiler_options *options, FILE *output) { +bool validate_ra(Program *program, const struct radv_nir_compiler_options *options) { if (!(debug_flags & DEBUG_VALIDATE_RA)) return false; @@ -601,16 +681,16 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio if (!op.isTemp()) continue; if (!op.isFixed()) - err |= ra_fail(output, loc, Location(), "Operand %d is not assigned a register", i); + err |= ra_fail(program, loc, Location(), "Operand %d is not assigned a register", i); if (assignments.count(op.tempId()) && assignments[op.tempId()].reg != op.physReg()) - err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an inconsistent register assignment with instruction", i); + err |= ra_fail(program, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an inconsistent register assignment with instruction", i); if ((op.getTemp().type() == RegType::vgpr && op.physReg().reg_b + op.bytes() > (256 + program->config->num_vgprs) * 4) || (op.getTemp().type() == RegType::sgpr && op.physReg() + op.size() > program->config->num_sgprs && op.physReg() < program->sgpr_limit)) - err |= ra_fail(output, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an out-of-bounds register assignment", i); + err |= ra_fail(program, loc, assignments.at(op.tempId()).firstloc, "Operand %d has an out-of-bounds register assignment", i); if (op.physReg() == vcc && !program->needs_vcc) - err |= ra_fail(output, loc, Location(), "Operand %d fixed to vcc but needs_vcc=false", i); + err |= ra_fail(program, loc, Location(), "Operand %d fixed to vcc but needs_vcc=false", i); if (op.regClass().is_subdword() && !validate_subdword_operand(program->chip_class, instr, i)) - err |= ra_fail(output, loc, Location(), "Operand %d not aligned correctly", i); + err |= ra_fail(program, loc, Location(), "Operand %d not aligned correctly", i); if (!assignments[op.tempId()].firstloc.block) assignments[op.tempId()].firstloc = loc; if (!assignments[op.tempId()].defloc.block) @@ -622,16 +702,16 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio if (!def.isTemp()) continue; if (!def.isFixed()) - err |= ra_fail(output, loc, Location(), "Definition %d is not assigned a register", i); + err |= ra_fail(program, loc, Location(), "Definition %d is not assigned a register", i); if (assignments[def.tempId()].defloc.block) - err |= ra_fail(output, loc, assignments.at(def.tempId()).defloc, "Temporary %%%d also defined by instruction", def.tempId()); + err |= ra_fail(program, loc, assignments.at(def.tempId()).defloc, "Temporary %%%d also defined by instruction", def.tempId()); if ((def.getTemp().type() == RegType::vgpr && def.physReg().reg_b + def.bytes() > (256 + program->config->num_vgprs) * 4) || (def.getTemp().type() == RegType::sgpr && def.physReg() + def.size() > program->config->num_sgprs && def.physReg() < program->sgpr_limit)) - err |= ra_fail(output, loc, assignments.at(def.tempId()).firstloc, "Definition %d has an out-of-bounds register assignment", i); + err |= ra_fail(program, loc, assignments.at(def.tempId()).firstloc, "Definition %d has an out-of-bounds register assignment", i); if (def.physReg() == vcc && !program->needs_vcc) - err |= ra_fail(output, loc, Location(), "Definition %d fixed to vcc but needs_vcc=false", i); + err |= ra_fail(program, loc, Location(), "Definition %d fixed to vcc but needs_vcc=false", i); if (def.regClass().is_subdword() && !validate_subdword_definition(program->chip_class, instr)) - err |= ra_fail(output, loc, Location(), "Definition %d not aligned correctly", i); + err |= ra_fail(program, loc, Location(), "Definition %d not aligned correctly", i); if (!assignments[def.tempId()].firstloc.block) assignments[def.tempId()].firstloc = loc; assignments[def.tempId()].defloc = loc; @@ -658,7 +738,7 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio PhysReg reg = assignments.at(tmp.id()).reg; for (unsigned i = 0; i < tmp.bytes(); i++) { if (regs[reg.reg_b + i]) { - err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]); + err |= ra_fail(program, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]); } regs[reg.reg_b + i] = tmp.id(); } @@ -674,7 +754,7 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio PhysReg reg = assignments.at(tmp.id()).reg; for (unsigned i = 0; i < tmp.bytes(); i++) { if (regs[reg.reg_b + i]) - err |= ra_fail(output, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]); + err |= ra_fail(program, loc, Location(), "Assignment of element %d of %%%d already taken by %%%d in live-out", i, tmp.id(), regs[reg.reg_b + i]); } live.emplace(tmp); } @@ -734,7 +814,7 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio PhysReg reg = assignments.at(tmp.id()).reg; for (unsigned j = 0; j < tmp.bytes(); j++) { if (regs[reg.reg_b + j]) - err |= ra_fail(output, loc, assignments.at(regs[reg.reg_b + j]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg.reg_b + j]); + err |= ra_fail(program, loc, assignments.at(regs[reg.reg_b + j]).defloc, "Assignment of element %d of %%%d already taken by %%%d from instruction", i, tmp.id(), regs[reg.reg_b + j]); regs[reg.reg_b + j] = tmp.id(); } if (def.regClass().is_subdword() && def.bytes() < 4) { @@ -743,7 +823,7 @@ bool validate_ra(Program *program, const struct radv_nir_compiler_options *optio for (unsigned j = reg.byte() & ~(written - 1); j < written; j++) { unsigned written_reg = reg.reg() * 4u + j; if (regs[written_reg] && regs[written_reg] != def.tempId()) - err |= ra_fail(output, loc, assignments.at(regs[written_reg]).defloc, "Assignment of element %d of %%%d overwrites the full register taken by %%%d from instruction", i, tmp.id(), regs[written_reg]); + err |= ra_fail(program, loc, assignments.at(regs[written_reg]).defloc, "Assignment of element %d of %%%d overwrites the full register taken by %%%d from instruction", i, tmp.id(), regs[written_reg]); } } }