X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_cmd_buffer.c;h=3646c1ae89e3bff9676a494d5650ed0c0cafea78;hb=4cf8f329edb3ad3482819de8dc091061ae19c5af;hp=168361d8d5e7c638fbde6a693bd187f33c7729ee;hpb=3a16c722cf3e5c41c9228b7021754a085746dc4d;p=mesa.git diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 168361d8d5e..3646c1ae89e 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -305,13 +305,11 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer) if (cmd_buffer->upload.upload_bo) radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, - cmd_buffer->upload.upload_bo, 8); + cmd_buffer->upload.upload_bo); cmd_buffer->upload.offset = 0; cmd_buffer->record_result = VK_SUCCESS; - cmd_buffer->ring_offsets_idx = -1; - for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) { cmd_buffer->descriptors[i].dirty = 0; cmd_buffer->descriptors[i].valid = 0; @@ -319,11 +317,21 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer) } if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends; + unsigned eop_bug_offset; void *fence_ptr; + radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0, &cmd_buffer->gfx9_fence_offset, &fence_ptr); cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo; + + /* Allocate a buffer for the EOP bug on GFX9. */ + radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0, + &eop_bug_offset, &fence_ptr); + cmd_buffer->gfx9_eop_bug_va = + radv_buffer_get_va(cmd_buffer->upload.upload_bo); + cmd_buffer->gfx9_eop_bug_va += eop_bug_offset; } cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL; @@ -355,7 +363,7 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer, return false; } - radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8); + radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo); if (cmd_buffer->upload.upload_bo) { upload = malloc(sizeof(*upload)); @@ -473,7 +481,7 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, cmd_buffer->device->physical_device->rad_info.chip_class, ptr, va, radv_cmd_buffer_uses_mec(cmd_buffer), - flags); + flags, cmd_buffer->gfx9_eop_bug_va); } if (unlikely(cmd_buffer->device->trace_bo)) @@ -520,10 +528,8 @@ void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer, radv_get_descriptors_state(cmd_buffer, bind_point); descriptors_state->sets[idx] = set; - if (set) - descriptors_state->valid |= (1u << idx); - else - descriptors_state->valid &= ~(1u << idx); + + descriptors_state->valid |= (1u << idx); /* active descriptors */ descriptors_state->dirty |= (1u << idx); } @@ -862,12 +868,12 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) continue; radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, - pipeline->shaders[i]->bo, 8); + pipeline->shaders[i]->bo); } if (radv_pipeline_has_gs(pipeline)) radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, - pipeline->gs_copy_shader->bo, 8); + pipeline->gs_copy_shader->bo); if (unlikely(cmd_buffer->device->trace_bo)) radv_save_pipeline(cmd_buffer, pipeline, RING_GFX); @@ -1449,7 +1455,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) struct radv_image *image = att->attachment->image; VkImageLayout layout = subpass->color_attachments[i].layout; - radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8); + radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo); assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT); radv_emit_fb_color_state(cmd_buffer, i, att, image, layout); @@ -1462,7 +1468,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) VkImageLayout layout = subpass->depth_stencil_attachment.layout; struct radv_attachment_info *att = &framebuffer->attachments[idx]; struct radv_image *image = att->attachment->image; - radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8); + radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo); MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index); @@ -1960,8 +1966,15 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags src_flags, struct radv_image *image) { + bool flush_CB_meta = true, flush_DB_meta = true; enum radv_cmd_flush_bits flush_bits = 0; uint32_t b; + + if (image && !radv_image_has_CB_metadata(image)) + flush_CB_meta = false; + if (image && !radv_image_has_htile(image)) + flush_DB_meta = false; + for_each_bit(b, src_flags) { switch ((VkAccessFlagBits)(1 << b)) { case VK_ACCESS_SHADER_WRITE_BIT: @@ -1969,22 +1982,23 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, break; case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT: flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB; - if (!image || (image && radv_image_has_CB_metadata(image))) { + if (flush_CB_meta) flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; - } break; case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT: flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB; - if (!image || (image && radv_image_has_htile(image))) { + if (flush_DB_meta) flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; - } break; case VK_ACCESS_TRANSFER_WRITE_BIT: flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | - RADV_CMD_FLAG_FLUSH_AND_INV_CB_META | RADV_CMD_FLAG_FLUSH_AND_INV_DB | - RADV_CMD_FLAG_FLUSH_AND_INV_DB_META | RADV_CMD_FLAG_INV_GLOBAL_L2; + + if (flush_CB_meta) + flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; + if (flush_DB_meta) + flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; break; default: break; @@ -2239,7 +2253,7 @@ static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer) struct radv_device *device = cmd_buffer->device; if (device->gfx_init) { uint64_t va = radv_buffer_get_va(device->gfx_init); - radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8); + radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init); radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0)); radeon_emit(cmd_buffer->cs, va); radeon_emit(cmd_buffer->cs, va >> 32); @@ -2307,7 +2321,7 @@ VkResult radv_BeginCommandBuffer( struct radv_device *device = cmd_buffer->device; radv_cs_add_buffer(device->ws, cmd_buffer->cs, - device->trace_bo, 8); + device->trace_bo); radv_cmd_buffer_trace_emit(cmd_buffer); } @@ -2345,7 +2359,7 @@ void radv_CmdBindVertexBuffers( vb[idx].offset = pOffsets[i]; radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, - vb[idx].buffer->bo, 8); + vb[idx].buffer->bo); } if (!changed) { @@ -2381,7 +2395,7 @@ void radv_CmdBindIndexBuffer( int index_size_shift = cmd_buffer->state.index_type ? 2 : 1; cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift; cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER; - radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8); + radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo); } @@ -2393,19 +2407,18 @@ radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys *ws = cmd_buffer->device->ws; radv_set_descriptor_set(cmd_buffer, bind_point, set, idx); - if (!set) - return; + assert(set); assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR)); if (!cmd_buffer->device->use_global_bo_list) { for (unsigned j = 0; j < set->layout->buffer_count; ++j) if (set->descriptors[j]) - radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7); + radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]); } if(set->bo) - radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8); + radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo); } void radv_CmdBindDescriptorSets( @@ -2629,7 +2642,7 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer) pipeline->max_waves * pipeline->scratch_bytes_per_wave); radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, - pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8); + pipeline->shaders[MESA_SHADER_COMPUTE]->bo); if (unlikely(cmd_buffer->device->trace_bo)) radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE); @@ -2689,15 +2702,6 @@ void radv_CmdBindPipeline( if (radv_pipeline_has_tess(pipeline)) cmd_buffer->tess_rings_needed = true; - - if (radv_pipeline_has_gs(pipeline)) { - struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY, - AC_UD_SCRATCH_RING_OFFSETS); - if (cmd_buffer->ring_offsets_idx == -1) - cmd_buffer->ring_offsets_idx = loc->sgpr_idx; - else if (loc->sgpr_idx != -1) - assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx); - } break; default: assert(!"invalid bind point"); @@ -2885,12 +2889,6 @@ void radv_CmdExecuteCommands( if (secondary->sample_positions_needed) primary->sample_positions_needed = true; - if (secondary->ring_offsets_idx != -1) { - if (primary->ring_offsets_idx == -1) - primary->ring_offsets_idx = secondary->ring_offsets_idx; - else - assert(secondary->ring_offsets_idx == primary->ring_offsets_idx); - } primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs); @@ -3242,7 +3240,7 @@ radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer, va += info->indirect->offset + info->indirect_offset; - radv_cs_add_buffer(ws, cs, info->indirect->bo, 8); + radv_cs_add_buffer(ws, cs, info->indirect->bo); radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0)); radeon_emit(cs, 1); @@ -3254,7 +3252,7 @@ radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer, count_va += info->count_buffer->offset + info->count_buffer_offset; - radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8); + radv_cs_add_buffer(ws, cs, info->count_buffer->bo); } if (!state->subpass->view_mask) { @@ -3714,7 +3712,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, va += info->indirect->offset + info->indirect_offset; - radv_cs_add_buffer(ws, cs, info->indirect->bo, 8); + radv_cs_add_buffer(ws, cs, info->indirect->bo); if (loc->sgpr_idx != -1) { for (unsigned i = 0; i < 3; ++i) { @@ -4226,7 +4224,7 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]); uint64_t va = radv_buffer_get_va(event->bo); - radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8); + radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo); MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7); @@ -4312,7 +4310,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer, struct radeon_cmdbuf *cs = cmd_buffer->cs; uint64_t va = radv_buffer_get_va(event->bo); - radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8); + radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo); MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18); @@ -4357,7 +4355,8 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer, cmd_buffer->device->physical_device->rad_info.chip_class, radv_cmd_buffer_uses_mec(cmd_buffer), V_028A90_BOTTOM_OF_PIPE_TS, 0, - EOP_DATA_SEL_VALUE_32BIT, va, 2, value); + EOP_DATA_SEL_VALUE_32BIT, va, 2, value, + cmd_buffer->gfx9_eop_bug_va); } assert(cmd_buffer->cs->cdw <= cdw_max);