X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_cmd_buffer.c;h=5ab577b4c5911d387f6b0fe0185f55218cba8064;hb=de06dfa9ea05ab5d06efb20223a858eb42d02683;hp=8fe96b2e50430a4a0d6d4b0b36dc990b5f394b4e;hpb=fde7b90ecf6fe74e977e5676acc9454de5d5d9e4;p=mesa.git diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 8fe96b2e504..5ab577b4c59 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -238,7 +238,7 @@ static VkResult radv_create_cmd_buffer( cmd_buffer->queue_family_index = pool->queue_family_index; } else { - /* Init the pool_link so we can safefly call list_del when we destroy + /* Init the pool_link so we can safely call list_del when we destroy * the command buffer */ list_inithead(&cmd_buffer->pool_link); @@ -347,7 +347,8 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer, new_size, 4096, RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS| - RADEON_FLAG_NO_INTERPROCESS_SHARING); + RADEON_FLAG_NO_INTERPROCESS_SHARING | + RADEON_FLAG_32BIT); if (!bo) { cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY; @@ -585,11 +586,12 @@ radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer, uint32_t base_reg = pipeline->user_data_0[stage]; if (loc->sgpr_idx == -1) return; - assert(loc->num_sgprs == 2); + + assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2)); assert(!loc->indirect); - radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2); - radeon_emit(cmd_buffer->cs, va); - radeon_emit(cmd_buffer->cs, va >> 32); + + radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, + base_reg + loc->sgpr_idx * 4, va, false); } static void @@ -1156,7 +1158,7 @@ radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer, } /* - *with DCC some colors don't require CMASK elimiation before being + * With DCC some colors don't require CMASK elimination before being * used as a texture. This sets a predicate value to determine if the * cmask eliminate is required. */ @@ -1334,6 +1336,7 @@ radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer) void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer) { + bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled; struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; uint32_t pa_sc_mode_cntl_1 = pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0; @@ -1342,11 +1345,12 @@ void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer) if(!cmd_buffer->state.active_occlusion_queries) { if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) { if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) && - pipeline->graphics.disable_out_of_order_rast_for_occlusion) { + pipeline->graphics.disable_out_of_order_rast_for_occlusion && + has_perfect_queries) { /* Re-enable out-of-order rasterization if the * bound pipeline supports it and if it's has - * been disabled before starting occlusion - * queries. + * been disabled before starting any perfect + * occlusion queries. */ radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, @@ -1359,22 +1363,22 @@ void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer) } else { const struct radv_subpass *subpass = cmd_buffer->state.subpass; uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0; - bool perfect = cmd_buffer->state.perfect_occlusion_queries_enabled; if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) { db_count_control = - S_028004_PERFECT_ZPASS_COUNTS(perfect) | + S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) | S_028004_SAMPLE_RATE(sample_rate) | S_028004_ZPASS_ENABLE(1) | S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1); if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) && - pipeline->graphics.disable_out_of_order_rast_for_occlusion) { + pipeline->graphics.disable_out_of_order_rast_for_occlusion && + has_perfect_queries) { /* If the bound pipeline has enabled * out-of-order rasterization, we should - * disable it before starting occlusion - * queries. + * disable it before starting any perfect + * occlusion queries. */ pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE; @@ -1439,11 +1443,10 @@ emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer, return; assert(!desc_set_loc->indirect); - assert(desc_set_loc->num_sgprs == 2); - radeon_set_sh_reg_seq(cmd_buffer->cs, - base_reg + desc_set_loc->sgpr_idx * 4, 2); - radeon_emit(cmd_buffer->cs, va); - radeon_emit(cmd_buffer->cs, va >> 32); + assert(desc_set_loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2)); + + radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, + base_reg + desc_set_loc->sgpr_idx * 4, va, false); } static void @@ -2206,9 +2209,11 @@ radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer, assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR)); - for (unsigned j = 0; j < set->layout->buffer_count; ++j) - if (set->descriptors[j]) - radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7); + if (!cmd_buffer->device->use_global_bo_list) { + for (unsigned j = 0; j < set->layout->buffer_count; ++j) + if (set->descriptors[j]) + radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7); + } if(set->bo) radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8); @@ -2228,6 +2233,8 @@ void radv_CmdBindDescriptorSets( RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout); unsigned dyn_idx = 0; + const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS; + for (unsigned i = 0; i < descriptorSetCount; ++i) { unsigned idx = i + firstSet; RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]); @@ -2242,7 +2249,7 @@ void radv_CmdBindDescriptorSets( uint64_t va = range->va + pDynamicOffsets[dyn_idx]; dst[0] = va; dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32); - dst[2] = range->size; + dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size; dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) | S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) | S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) | @@ -3766,25 +3773,6 @@ static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer, state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; } -static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, - VkImageLayout src_layout, - VkImageLayout dst_layout, - unsigned src_queue_mask, - unsigned dst_queue_mask, - const VkImageSubresourceRange *range) -{ - if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { - if (radv_image_has_fmask(image)) - radv_initialise_cmask(cmd_buffer, image, 0xccccccccu); - else - radv_initialise_cmask(cmd_buffer, image, 0xffffffffu); - } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) && - !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) { - radv_fast_clear_flush_image_inplace(cmd_buffer, image, range); - } -} - void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, uint32_t value) { @@ -3799,26 +3787,36 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer, RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; } -static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, - VkImageLayout src_layout, - VkImageLayout dst_layout, - unsigned src_queue_mask, - unsigned dst_queue_mask, - const VkImageSubresourceRange *range) +/** + * Initialize DCC/FMASK/CMASK metadata for a color image. + */ +static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, + struct radv_image *image, + VkImageLayout src_layout, + VkImageLayout dst_layout, + unsigned src_queue_mask, + unsigned dst_queue_mask) { - if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) { - radv_initialize_dcc(cmd_buffer, image, 0xffffffffu); - } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { - radv_initialize_dcc(cmd_buffer, image, - radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ? - 0x20202020u : 0xffffffffu); - } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) && - !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) { - radv_decompress_dcc(cmd_buffer, image, range); - } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) && - !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) { - radv_fast_clear_flush_image_inplace(cmd_buffer, image, range); + if (radv_image_has_cmask(image)) { + uint32_t value = 0xffffffffu; /* Fully expanded mode. */ + + /* TODO: clarify this. */ + if (radv_image_has_fmask(image)) { + value = 0xccccccccu; + } + + radv_initialise_cmask(cmd_buffer, image, value); + } + + if (radv_image_has_dcc(image)) { + uint32_t value = 0xffffffffu; /* Fully expanded mode. */ + + if (radv_layout_dcc_compressed(image, dst_layout, + dst_queue_mask)) { + value = 0x20202020u; + } + + radv_initialize_dcc(cmd_buffer, image, value); } } @@ -3833,15 +3831,29 @@ static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffe unsigned dst_queue_mask, const VkImageSubresourceRange *range) { - if (radv_image_has_dcc(image)) - radv_handle_dcc_image_transition(cmd_buffer, image, src_layout, - dst_layout, src_queue_mask, - dst_queue_mask, range); + if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) { + radv_init_color_image_metadata(cmd_buffer, image, + src_layout, dst_layout, + src_queue_mask, dst_queue_mask); + return; + } - if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) - radv_handle_cmask_image_transition(cmd_buffer, image, src_layout, - dst_layout, src_queue_mask, - dst_queue_mask, range); + if (radv_image_has_dcc(image)) { + if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) { + radv_initialize_dcc(cmd_buffer, image, 0xffffffffu); + } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) && + !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) { + radv_decompress_dcc(cmd_buffer, image, range); + } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) && + !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) { + radv_fast_clear_flush_image_inplace(cmd_buffer, image, range); + } + } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) { + if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) && + !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) { + radv_fast_clear_flush_image_inplace(cmd_buffer, image, range); + } + } } static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,