X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_cmd_buffer.c;h=6a89d4e568d96219b844faadc6eee16c57be682d;hb=34d23e82ca9dce784e3041488725aa828f847f13;hp=4a048485c865d8b46822dbdd976a9a3feeca6159;hpb=5a761167f53b53569a6d55d9436bdfec071b2b17;p=mesa.git

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4a048485c86..6a89d4e568d 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -593,7 +593,8 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 	radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
 	radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
 
-	if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
+	if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples &&
+	    old_pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions == pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 		return;
 
 	radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
@@ -1753,7 +1754,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
 	uint64_t va;
 
 	stages &= cmd_buffer->push_constant_stages;
-	if (!stages || !layout || (!layout->push_constant_size && !layout->dynamic_offset_count))
+	if (!stages ||
+	    (!layout->push_constant_size && !layout->dynamic_offset_count))
 		return;
 
 	if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +