X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_cmd_buffer.c;h=a5846460455a64840ee4f370f3d83255cd45f1bb;hb=65458528fc169ab80c99cb115bc6f86ae7b43d12;hp=f3e3de8dafd50283b17c9e97e77b5900c57cae47;hpb=8b7586655fbbcc52de47cc110aa145e3703929cc;p=mesa.git diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f3e3de8dafd..a5846460455 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -325,7 +325,7 @@ radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo); cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs); - for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) + for (unsigned i = 0; i < MAX_BIND_POINTS; i++) free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr); vk_free(&cmd_buffer->pool->alloc, cmd_buffer); @@ -364,7 +364,7 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer) memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings)); - for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) { + for (unsigned i = 0; i < MAX_BIND_POINTS; i++) { cmd_buffer->descriptors[i].dirty = 0; cmd_buffer->descriptors[i].valid = 0; cmd_buffer->descriptors[i].push_dirty = false; @@ -700,8 +700,8 @@ radv_convert_user_sample_locs(struct radv_sample_locations_state *state, float shifted_pos_x = user_locs[i].x - 0.5; float shifted_pos_y = user_locs[i].y - 0.5; - int32_t scaled_pos_x = floor(shifted_pos_x * 16); - int32_t scaled_pos_y = floor(shifted_pos_y * 16); + int32_t scaled_pos_x = floorf(shifted_pos_x * 16); + int32_t scaled_pos_y = floorf(shifted_pos_y * 16); sample_locs[i].x = CLAMP(scaled_pos_x, -8, 7); sample_locs[i].y = CLAMP(scaled_pos_y, -8, 7); @@ -778,8 +778,6 @@ radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer, static void radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer) { - struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; - struct radv_multisample_state *ms = &pipeline->graphics.ms; struct radv_sample_locations_state *sample_location = &cmd_buffer->state.dynamic.sample_location; uint32_t num_samples = (uint32_t)sample_location->per_pixel; @@ -810,10 +808,12 @@ radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer) num_samples); /* Compute the maximum sample distance from the specified locations. */ - for (uint32_t i = 0; i < num_samples; i++) { - VkOffset2D offset = sample_locs[0][i]; - max_sample_dist = MAX2(max_sample_dist, - MAX2(abs(offset.x), abs(offset.y))); + for (unsigned i = 0; i < 4; ++i) { + for (uint32_t j = 0; j < num_samples; j++) { + VkOffset2D offset = sample_locs[i][j]; + max_sample_dist = MAX2(max_sample_dist, + MAX2(abs(offset.x), abs(offset.y))); + } } /* Emit the specified user sample locations. */ @@ -840,13 +840,9 @@ radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer) } /* Emit the maximum sample distance and the centroid priority. */ - uint32_t pa_sc_aa_config = ms->pa_sc_aa_config; - - pa_sc_aa_config &= C_028BE0_MAX_SAMPLE_DIST; - pa_sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(max_sample_dist); - - radeon_set_context_reg_seq(cs, R_028BE0_PA_SC_AA_CONFIG, 1); - radeon_emit(cs, pa_sc_aa_config); + radeon_set_context_reg_rmw(cs, R_028BE0_PA_SC_AA_CONFIG, + S_028BE0_MAX_SAMPLE_DIST(max_sample_dist), + ~C_028BE0_MAX_SAMPLE_DIST); radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); radeon_emit(cs, centroid_priority); @@ -1475,10 +1471,10 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer, !radv_image_is_tc_compat_htile(image)) return; - if (!radv_layout_has_htile(image, layout, in_render_loop, - radv_image_queue_family_mask(image, - cmd_buffer->queue_family_index, - cmd_buffer->queue_family_index))) { + if (!radv_layout_is_htile_compressed(image, layout, in_render_loop, + radv_image_queue_family_mask(image, + cmd_buffer->queue_family_index, + cmd_buffer->queue_family_index))) { db_z_info &= C_028040_TILE_SURFACE_ENABLE; } @@ -1518,10 +1514,10 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, uint32_t db_z_info = ds->db_z_info; uint32_t db_stencil_info = ds->db_stencil_info; - if (!radv_layout_has_htile(image, layout, in_render_loop, - radv_image_queue_family_mask(image, - cmd_buffer->queue_family_index, - cmd_buffer->queue_family_index))) { + if (!radv_layout_is_htile_compressed(image, layout, in_render_loop, + radv_image_queue_family_mask(image, + cmd_buffer->queue_family_index, + cmd_buffer->queue_family_index))) { db_z_info &= C_028040_TILE_SURFACE_ENABLE; db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1); } @@ -2053,14 +2049,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) VkImageLayout layout = subpass->depth_stencil_attachment->layout; bool in_render_loop = subpass->depth_stencil_attachment->in_render_loop; struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview; - struct radv_image *image = iview->image; radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->state.attachments[idx].iview->bo); - ASSERTED uint32_t queue_mask = radv_image_queue_family_mask(image, - cmd_buffer->queue_family_index, - cmd_buffer->queue_family_index); - /* We currently don't support writing decompressed HTILE */ - assert(radv_layout_has_htile(image, layout, in_render_loop, queue_mask) == - radv_layout_is_htile_compressed(image, layout, in_render_loop, queue_mask)); radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout, in_render_loop); @@ -3464,19 +3453,22 @@ void radv_CmdBindVertexBuffers( assert(firstBinding + bindingCount <= MAX_VBS); for (uint32_t i = 0; i < bindingCount; i++) { + RADV_FROM_HANDLE(radv_buffer, buffer, pBuffers[i]); uint32_t idx = firstBinding + i; if (!changed && - (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) || + (vb[idx].buffer != buffer || vb[idx].offset != pOffsets[i])) { changed = true; } - vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]); + vb[idx].buffer = buffer; vb[idx].offset = pOffsets[i]; - radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, - vb[idx].buffer->bo); + if (buffer) { + radv_cs_add_buffer(cmd_buffer->device->ws, + cmd_buffer->cs, vb[idx].buffer->bo); + } } if (!changed) { @@ -3559,7 +3551,7 @@ radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer, assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR)); if (!cmd_buffer->device->use_global_bo_list) { - for (unsigned j = 0; j < set->layout->buffer_count; ++j) + for (unsigned j = 0; j < set->buffer_count; ++j) if (set->descriptors[j]) radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]); } @@ -3881,9 +3873,7 @@ void radv_CmdBindPipeline( /* Prefetch all pipeline shaders at first draw time. */ cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS; - if ((cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI10 || - cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI12 || - cmd_buffer->device->physical_device->rad_info.family == CHIP_NAVI14) && + if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10 && cmd_buffer->state.emitted_pipeline && radv_pipeline_has_ngg(cmd_buffer->state.emitted_pipeline) && !radv_pipeline_has_ngg(cmd_buffer->state.pipeline)) { @@ -4266,7 +4256,7 @@ VkResult radv_CreateCommandPool( RADV_FROM_HANDLE(radv_device, device, _device); struct radv_cmd_pool *pool; - pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8, + pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); if (pool == NULL) return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); @@ -4274,7 +4264,7 @@ VkResult radv_CreateCommandPool( if (pAllocator) pool->alloc = *pAllocator; else - pool->alloc = device->alloc; + pool->alloc = device->vk.alloc; list_inithead(&pool->cmd_buffers); list_inithead(&pool->free_cmd_buffers); @@ -4308,7 +4298,7 @@ void radv_DestroyCommandPool( radv_cmd_buffer_destroy(cmd_buffer); } - vk_free2(&device->alloc, pAllocator, pool); + vk_free2(&device->vk.alloc, pAllocator, pool); } VkResult radv_ResetCommandPool(