X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_cmd_buffer.c;h=eae5d40e1986945146dd02727e502c37d717a809;hb=9fdc1437baab9dbb0b1c3473af27b2241954b2de;hp=bd72ba2a878fcf948aa1778471e44c25b1db6264;hpb=1cc00b8e0eb839096c1d6856df9213d6bad474ef;p=mesa.git diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index bd72ba2a878..eae5d40e198 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -292,6 +292,8 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo; } + cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL; + return cmd_buffer->record_result; } @@ -1181,9 +1183,10 @@ radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer) static void radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index, - struct radv_color_buffer_info *cb) + struct radv_attachment_info *att) { bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI; + struct radv_color_buffer_info *cb = &att->cb; if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); @@ -1204,7 +1207,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32); radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4, - cb->gfx9_epitch); + S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch)); } else { radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); radeon_emit(cmd_buffer->cs, cb->cb_color_base); @@ -1297,8 +1300,7 @@ radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer, va += image->offset + image->clear_value_offset; unsigned reg_offset = 0, reg_count = 0; - if (!image->surface.htile_size) - return; + assert(image->surface.htile_size); if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) { ++reg_count; @@ -1375,8 +1377,7 @@ radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer, uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->dcc_pred_offset; - if (!image->surface.dcc_size) - return; + assert(image->surface.dcc_size); radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0)); radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) | @@ -1397,8 +1398,7 @@ radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer, uint64_t va = radv_buffer_get_va(image->bo); va += image->offset + image->clear_value_offset; - if (!image->cmask.size && !image->surface.dcc_size) - return; + assert(image->cmask.size || image->surface.dcc_size); radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0)); radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) | @@ -1464,7 +1464,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8); assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT); - radv_emit_fb_color_state(cmd_buffer, i, &att->cb); + radv_emit_fb_color_state(cmd_buffer, i, att); radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i); } @@ -1514,21 +1514,26 @@ static void radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer) { struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radv_cmd_state *state = &cmd_buffer->state; - if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { - radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE, - 2, cmd_buffer->state.index_type); - } else { - radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0)); - radeon_emit(cs, cmd_buffer->state.index_type); + if (state->index_type != state->last_index_type) { + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE, + 2, state->index_type); + } else { + radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0)); + radeon_emit(cs, state->index_type); + } + + state->last_index_type = state->index_type; } radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0)); - radeon_emit(cs, cmd_buffer->state.index_va); - radeon_emit(cs, cmd_buffer->state.index_va >> 32); + radeon_emit(cs, state->index_va); + radeon_emit(cs, state->index_va >> 32); radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0)); - radeon_emit(cs, cmd_buffer->state.max_index_count); + radeon_emit(cs, state->max_index_count); cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER; } @@ -2139,9 +2144,6 @@ VkResult radv_AllocateCommandBuffers( VkResult result = VK_SUCCESS; uint32_t i; - memset(pCommandBuffers, 0, - sizeof(*pCommandBuffers)*pAllocateInfo->commandBufferCount); - for (i = 0; i < pAllocateInfo->commandBufferCount; i++) { if (!list_empty(&pool->free_cmd_buffers)) { @@ -2163,10 +2165,23 @@ VkResult radv_AllocateCommandBuffers( break; } - if (result != VK_SUCCESS) + if (result != VK_SUCCESS) { radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool, i, pCommandBuffers); + /* From the Vulkan 1.0.66 spec: + * + * "vkAllocateCommandBuffers can be used to create multiple + * command buffers. If the creation of any of those command + * buffers fails, the implementation must destroy all + * successfully created command buffer objects from this + * command, set all entries of the pCommandBuffers array to + * NULL and return the error." + */ + memset(pCommandBuffers, 0, + sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount); + } + return result; } @@ -2217,14 +2232,20 @@ VkResult radv_BeginCommandBuffer( const VkCommandBufferBeginInfo *pBeginInfo) { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); - VkResult result; + VkResult result = VK_SUCCESS; - result = radv_reset_cmd_buffer(cmd_buffer); - if (result != VK_SUCCESS) - return result; + if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) { + /* If the command buffer has already been resetted with + * vkResetCommandBuffer, no need to do it again. + */ + result = radv_reset_cmd_buffer(cmd_buffer); + if (result != VK_SUCCESS) + return result; + } memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state)); cmd_buffer->state.last_primitive_reset_en = -1; + cmd_buffer->state.last_index_type = -1; cmd_buffer->usage_flags = pBeginInfo->flags; /* setup initial configuration into command buffer */ @@ -2260,6 +2281,8 @@ VkResult radv_BeginCommandBuffer( if (unlikely(cmd_buffer->device->trace_bo)) radv_cmd_buffer_trace_emit(cmd_buffer); + cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING; + return result; } @@ -2528,6 +2551,8 @@ VkResult radv_EndCommandBuffer( if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs)) return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY); + cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE; + return cmd_buffer->record_result; } @@ -2838,6 +2863,11 @@ void radv_CmdExecuteCommands( primary->state.last_ia_multi_vgt_param = secondary->state.last_ia_multi_vgt_param; } + + if (secondary->state.last_index_type != -1) { + primary->state.last_index_type = + secondary->state.last_index_type; + } } /* After executing commands from secondary buffers we have to dirty @@ -3222,8 +3252,10 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, * so the state must be re-emitted before the next indexed * draw. */ - if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) + if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) { + cmd_buffer->state.last_index_type = -1; cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER; + } } radv_cmd_buffer_flush_dynamic_state(cmd_buffer); @@ -3451,29 +3483,16 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, { struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE]; + unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator; struct radeon_winsys *ws = cmd_buffer->device->ws; struct radeon_winsys_cs *cs = cmd_buffer->cs; struct ac_userdata_info *loc; - unsigned dispatch_initiator; - uint8_t grid_used; - - grid_used = compute_shader->info.info.cs.grid_components_used; loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE); MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25); - dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) | - S_00B800_FORCE_START_AT_000(1); - - if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) { - /* If the KMD allows it (there is a KMD hw register for it), - * allow launching waves out-of-order. - */ - dispatch_initiator |= S_00B800_ORDER_MODE(1); - } - if (info->indirect) { uint64_t va = radv_buffer_get_va(info->indirect->bo); @@ -3482,7 +3501,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, radv_cs_add_buffer(ws, cs, info->indirect->bo, 8); if (loc->sgpr_idx != -1) { - for (unsigned i = 0; i < grid_used; ++i) { + for (unsigned i = 0; i < 3; ++i) { radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) | COPY_DATA_DST_SEL(COPY_DATA_REG)); @@ -3549,15 +3568,13 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, if (loc->sgpr_idx != -1) { assert(!loc->indirect); - assert(loc->num_sgprs == grid_used); + assert(loc->num_sgprs == 3); radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + - loc->sgpr_idx * 4, grid_used); + loc->sgpr_idx * 4, 3); radeon_emit(cs, blocks[0]); - if (grid_used > 1) - radeon_emit(cs, blocks[1]); - if (grid_used > 2) - radeon_emit(cs, blocks[2]); + radeon_emit(cs, blocks[1]); + radeon_emit(cs, blocks[2]); } radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |