X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_debug.c;h=42296745543704d90bc32bebbe769ecc9d40fb97;hb=c65e880a6555e25c382e806d76795ef48515c983;hp=72c7c39fcb896a96e958195f139ee743642a63e0;hpb=8c406f0b4d904867058deb4e19acd69fd2c38c91;p=mesa.git

diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index 72c7c39fcb8..42296745543 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -31,7 +31,6 @@
 
 #include "util/mesa-sha1.h"
 #include "sid.h"
-#include "gfx9d.h"
 #include "ac_debug.h"
 #include "radv_debug.h"
 #include "radv_shader.h"
@@ -63,7 +62,8 @@ radv_init_trace(struct radv_device *device)
 	device->trace_bo = ws->buffer_create(ws, TRACE_BO_SIZE, 8,
 					     RADEON_DOMAIN_VRAM,
 					     RADEON_FLAG_CPU_ACCESS|
-					     RADEON_FLAG_NO_INTERPROCESS_SHARING);
+					     RADEON_FLAG_NO_INTERPROCESS_SHARING,
+					     RADV_BO_PRIORITY_UPLOAD_BUFFER);
 	if (!device->trace_bo)
 		return false;
 
@@ -80,7 +80,7 @@ radv_init_trace(struct radv_device *device)
 }
 
 static void
-radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs)
+radv_dump_trace(struct radv_device *device, struct radeon_cmdbuf *cs)
 {
 	const char *filename = getenv("RADV_TRACE_FILE");
 	FILE *f = fopen(filename, "w");
@@ -111,14 +111,11 @@ radv_dump_debug_registers(struct radv_device *device, FILE *f)
 {
 	struct radeon_info *info = &device->physical_device->rad_info;
 
-	if (info->drm_major == 2 && info->drm_minor < 42)
-		return; /* no radeon support */
-
 	fprintf(f, "Memory-mapped registers:\n");
 	radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
 
 	/* No other registers can be read on DRM < 3.1.0. */
-	if (info->drm_major < 3 || info->drm_minor < 1) {
+	if (info->drm_minor < 1) {
 		fprintf(f, "\n");
 		return;
 	}
@@ -130,7 +127,7 @@ radv_dump_debug_registers(struct radv_device *device, FILE *f)
 	radv_dump_mmapped_reg(device, f, R_00803C_GRBM_STATUS_SE3);
 	radv_dump_mmapped_reg(device, f, R_00D034_SDMA0_STATUS_REG);
 	radv_dump_mmapped_reg(device, f, R_00D834_SDMA1_STATUS_REG);
-	if (info->chip_class <= VI) {
+	if (info->chip_class <= GFX8) {
 		radv_dump_mmapped_reg(device, f, R_000E50_SRBM_STATUS);
 		radv_dump_mmapped_reg(device, f, R_000E4C_SRBM_STATUS2);
 		radv_dump_mmapped_reg(device, f, R_000E54_SRBM_STATUS3);
@@ -193,14 +190,17 @@ static void
 radv_dump_image_descriptor(enum chip_class chip_class, const uint32_t *desc,
 			   FILE *f)
 {
+	unsigned sq_img_rsrc_word0 = chip_class >= GFX10 ? R_00A000_SQ_IMG_RSRC_WORD0
+							 : R_008F10_SQ_IMG_RSRC_WORD0;
+
 	fprintf(f, COLOR_CYAN "    Image:" COLOR_RESET "\n");
 	for (unsigned j = 0; j < 8; j++)
-		ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
+		ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
 			    desc[j], 0xffffffff);
 
 	fprintf(f, COLOR_CYAN "    FMASK:" COLOR_RESET "\n");
 	for (unsigned j = 0; j < 8; j++)
-		ac_dump_reg(f, chip_class, R_008F10_SQ_IMG_RSRC_WORD0 + j * 4,
+		ac_dump_reg(f, chip_class, sq_img_rsrc_word0 + j * 4,
 			    desc[8 + j], 0xffffffff);
 }
 
@@ -442,28 +442,23 @@ radv_dump_annotated_shader(struct radv_shader_variant *shader,
 
 static void
 radv_dump_annotated_shaders(struct radv_pipeline *pipeline,
-			    struct radv_shader_variant *compute_shader,
-			    FILE *f)
+			    VkShaderStageFlagBits active_stages, FILE *f)
 {
 	struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
-	unsigned num_waves = ac_get_wave_info(waves);
-	unsigned mask;
+	enum chip_class chip_class = pipeline->device->physical_device->rad_info.chip_class;
+	unsigned num_waves = ac_get_wave_info(chip_class, waves);
 
 	fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
 		"\n\n", num_waves);
 
 	/* Dump annotated active graphics shaders. */
-	mask = pipeline->active_stages;
-	while (mask) {
-		int stage = u_bit_scan(&mask);
+	while (active_stages) {
+		int stage = u_bit_scan(&active_stages);
 
 		radv_dump_annotated_shader(pipeline->shaders[stage],
 					   stage, waves, num_waves, f);
 	}
 
-	radv_dump_annotated_shader(compute_shader, MESA_SHADER_COMPUTE, waves,
-				   num_waves, f);
-
 	/* Print waves executing shaders that are not currently bound. */
 	unsigned i;
 	bool found = false;
@@ -521,48 +516,51 @@ radv_dump_shader(struct radv_pipeline *pipeline,
 
 static void
 radv_dump_shaders(struct radv_pipeline *pipeline,
-		  struct radv_shader_variant *compute_shader, FILE *f)
+		  VkShaderStageFlagBits active_stages, FILE *f)
 {
-	unsigned mask;
-
 	/* Dump active graphics shaders. */
-	mask = pipeline->active_stages;
-	while (mask) {
-		int stage = u_bit_scan(&mask);
+	while (active_stages) {
+		int stage = u_bit_scan(&active_stages);
 
 		radv_dump_shader(pipeline, pipeline->shaders[stage], stage, f);
 	}
+}
 
-	radv_dump_shader(pipeline, compute_shader, MESA_SHADER_COMPUTE, f);
+static void
+radv_dump_pipeline_state(struct radv_pipeline *pipeline,
+			 VkShaderStageFlagBits active_stages, FILE *f)
+{
+	radv_dump_shaders(pipeline, active_stages, f);
+	radv_dump_annotated_shaders(pipeline, active_stages, f);
+	radv_dump_descriptors(pipeline, f);
 }
 
 static void
 radv_dump_graphics_state(struct radv_pipeline *graphics_pipeline,
 			 struct radv_pipeline *compute_pipeline, FILE *f)
 {
-	struct radv_shader_variant *compute_shader =
-		compute_pipeline ? compute_pipeline->shaders[MESA_SHADER_COMPUTE] : NULL;
+	VkShaderStageFlagBits active_stages;
 
-	if (!graphics_pipeline)
-		return;
+	if (graphics_pipeline) {
+		active_stages = graphics_pipeline->active_stages;
+		radv_dump_pipeline_state(graphics_pipeline, active_stages, f);
+	}
 
-	radv_dump_shaders(graphics_pipeline, compute_shader, f);
-	radv_dump_annotated_shaders(graphics_pipeline, compute_shader, f);
-	radv_dump_descriptors(graphics_pipeline, f);
+	if (compute_pipeline) {
+		active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
+		radv_dump_pipeline_state(compute_pipeline, active_stages, f);
+	}
 }
 
 static void
 radv_dump_compute_state(struct radv_pipeline *compute_pipeline, FILE *f)
 {
+	VkShaderStageFlagBits active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
+
 	if (!compute_pipeline)
 		return;
 
-	radv_dump_shaders(compute_pipeline,
-			  compute_pipeline->shaders[MESA_SHADER_COMPUTE], f);
-	radv_dump_annotated_shaders(compute_pipeline,
-				    compute_pipeline->shaders[MESA_SHADER_COMPUTE],
-				    f);
-	radv_dump_descriptors(compute_pipeline, f);
+	radv_dump_pipeline_state(compute_pipeline, active_stages, f);
 }
 
 static struct radv_pipeline *
@@ -631,7 +629,7 @@ static void
 radv_dump_device_name(struct radv_device *device, FILE *f)
 {
 	struct radeon_info *info = &device->physical_device->rad_info;
-	char llvm_string[32] = {}, kernel_version[128] = {};
+	char kernel_version[128] = {};
 	struct utsname uname_data;
 	const char *chip_name;
 
@@ -641,14 +639,11 @@ radv_dump_device_name(struct radv_device *device, FILE *f)
 		snprintf(kernel_version, sizeof(kernel_version),
 			 " / %s", uname_data.release);
 
-	snprintf(llvm_string, sizeof(llvm_string),
-		 ", LLVM %i.%i.%i", (HAVE_LLVM >> 8) & 0xff,
-		 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
-
-	fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s%s)\n\n",
+	fprintf(f, "Device name: %s (%s DRM %i.%i.%i%s, LLVM "
+		MESA_LLVM_VERSION_STRING ")\n\n",
 		chip_name, device->physical_device->name,
 		info->drm_major, info->drm_minor, info->drm_patchlevel,
-		kernel_version, llvm_string);
+		kernel_version);
 }
 
 static bool
@@ -663,7 +658,7 @@ radv_gpu_hang_occured(struct radv_queue *queue, enum ring_type ring)
 }
 
 void
-radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
+radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_cmdbuf *cs)
 {
 	struct radv_pipeline *graphics_pipeline, *compute_pipeline;
 	struct radv_device *device = queue->device;