X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_device.c;h=4d43f25aee029ab0a7e3af8b1eb2b4b3329efb4b;hb=e67fc11c26111ae7aa8d140a5f62074b5e0b43c3;hp=5d5bfb1df24b96c58ae6c9640880a6f293434d32;hpb=3844ed8d44677588bc29d470d0b41ef7816591b3;p=mesa.git diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 5d5bfb1df24..4d43f25aee0 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -44,7 +44,6 @@ #include "vk_format.h" #include "sid.h" #include "git_sha1.h" -#include "gfx9d.h" #include "util/build_id.h" #include "util/debug.h" #include "util/mesa-sha1.h" @@ -100,7 +99,6 @@ radv_get_device_name(enum radeon_family family, char *name, size_t name_len) case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break; case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break; case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break; - case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break; case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break; case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break; case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break; @@ -112,6 +110,7 @@ radv_get_device_name(enum radeon_family family, char *name, size_t name_len) case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break; case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break; case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break; + case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break; case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break; case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break; default: chip_string = "AMD RADV unknown"; break; @@ -219,11 +218,11 @@ radv_handle_env_var_force_family(struct radv_physical_device *device) if (i >= CHIP_VEGA10) device->rad_info.chip_class = GFX9; else if (i >= CHIP_TONGA) - device->rad_info.chip_class = VI; + device->rad_info.chip_class = GFX8; else if (i >= CHIP_BONAIRE) - device->rad_info.chip_class = CIK; + device->rad_info.chip_class = GFX7; else - device->rad_info.chip_class = SI; + device->rad_info.chip_class = GFX6; return; } @@ -331,7 +330,7 @@ radv_physical_device_init(struct radv_physical_device *device, disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2); device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags); - if (device->rad_info.chip_class < VI || + if (device->rad_info.chip_class < GFX8 || device->rad_info.chip_class > GFX9) fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n"); @@ -348,18 +347,18 @@ radv_physical_device_init(struct radv_physical_device *device, } /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs - * on SI. + * on GFX6. */ - device->has_clear_state = device->rad_info.chip_class >= CIK; + device->has_clear_state = device->rad_info.chip_class >= GFX7; - device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI; + device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8; /* Vega10/Raven need a special workaround for a hardware bug. */ device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 || device->rad_info.family == CHIP_RAVEN; /* Out-of-order primitive rasterization. */ - device->has_out_of_order_rast = device->rad_info.chip_class >= VI && + device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 && device->rad_info.max_se >= 2; device->out_of_order_rast_allowed = device->has_out_of_order_rast && !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER); @@ -367,11 +366,13 @@ radv_physical_device_init(struct radv_physical_device *device, device->dcc_msaa_allowed = (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA); - /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */ + /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */ device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 || - (device->rad_info.chip_class >= VI && + (device->rad_info.chip_class >= GFX8 && device->rad_info.me_fw_feature >= 41); + device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT; + radv_physical_device_init_mem_types(device); radv_fill_device_extension_table(device, &device->supported_extensions); @@ -463,6 +464,7 @@ static const struct debug_control radv_debug_options[] = { {"checkir", RADV_DEBUG_CHECKIR}, {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM}, {"nobinning", RADV_DEBUG_NOBINNING}, + {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT}, {NULL, 0} }; @@ -479,6 +481,8 @@ static const struct debug_control radv_perftest_options[] = { {"localbos", RADV_PERFTEST_LOCAL_BOS}, {"dccmsaa", RADV_PERFTEST_DCC_MSAA}, {"bolist", RADV_PERFTEST_BO_LIST}, + {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT}, + {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK}, {NULL, 0} }; @@ -509,6 +513,13 @@ radv_handle_per_app_options(struct radv_instance *instance, } else if (!strcmp(name, "DOOM_VFR")) { /* Work around a Doom VFR game bug */ instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS; + } else if (!strcmp(name, "MonsterHunterWorld.exe")) { + /* Workaround for a WaW hazard when LLVM moves/merges + * load/store memory operations. + * See https://reviews.llvm.org/D61313 + */ + if (HAVE_LLVM < 0x900) + instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT; } } @@ -768,7 +779,7 @@ void radv_GetPhysicalDeviceFeatures( .shaderTessellationAndGeometryPointSize = true, .shaderImageGatherExtended = true, .shaderStorageImageExtendedFormats = true, - .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI, + .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8, .shaderUniformBufferArrayDynamicIndexing = true, .shaderSampledImageArrayDynamicIndexing = true, .shaderStorageBufferArrayDynamicIndexing = true, @@ -793,8 +804,8 @@ void radv_GetPhysicalDeviceFeatures2( RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice); vk_foreach_struct(ext, pFeatures->pNext) { switch (ext->sType) { - case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: { - VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext; + case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: { + VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext; features->variablePointersStorageBuffer = true; features->variablePointers = true; break; @@ -806,9 +817,9 @@ void radv_GetPhysicalDeviceFeatures2( features->multiviewTessellationShader = true; break; } - case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: { - VkPhysicalDeviceShaderDrawParameterFeatures *features = - (VkPhysicalDeviceShaderDrawParameterFeatures*)ext; + case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: { + VkPhysicalDeviceShaderDrawParametersFeatures *features = + (VkPhysicalDeviceShaderDrawParametersFeatures*)ext; features->shaderDrawParameters = true; break; } @@ -821,7 +832,7 @@ void radv_GetPhysicalDeviceFeatures2( case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: { VkPhysicalDevice16BitStorageFeatures *features = (VkPhysicalDevice16BitStorageFeatures*)ext; - bool enabled = pdevice->rad_info.chip_class >= VI; + bool enabled = pdevice->rad_info.chip_class >= GFX8; features->storageBuffer16BitAccess = enabled; features->uniformAndStorageBuffer16BitAccess = enabled; features->storagePushConstant16 = enabled; @@ -831,7 +842,7 @@ void radv_GetPhysicalDeviceFeatures2( case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: { VkPhysicalDeviceSamplerYcbcrConversionFeatures *features = (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext; - features->samplerYcbcrConversion = false; + features->samplerYcbcrConversion = true; break; } case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: { @@ -883,7 +894,7 @@ void radv_GetPhysicalDeviceFeatures2( case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: { VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features = (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext; - features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK; + features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7; break; } case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: { @@ -892,9 +903,9 @@ void radv_GetPhysicalDeviceFeatures2( features->memoryPriority = VK_TRUE; break; } - case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT: { - VkPhysicalDeviceBufferAddressFeaturesEXT *features = - (VkPhysicalDeviceBufferAddressFeaturesEXT *)ext; + case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: { + VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features = + (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext; features->bufferDeviceAddress = true; features->bufferDeviceAddressCaptureReplay = false; features->bufferDeviceAddressMultiDevice = false; @@ -915,7 +926,7 @@ void radv_GetPhysicalDeviceFeatures2( case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: { VkPhysicalDevice8BitStorageFeaturesKHR *features = (VkPhysicalDevice8BitStorageFeaturesKHR*)ext; - bool enabled = pdevice->rad_info.chip_class >= VI; + bool enabled = pdevice->rad_info.chip_class >= GFX8; features->storageBuffer8BitAccess = enabled; features->uniformAndStorageBuffer8BitAccess = enabled; features->storagePushConstant8 = enabled; @@ -924,7 +935,7 @@ void radv_GetPhysicalDeviceFeatures2( case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: { VkPhysicalDeviceFloat16Int8FeaturesKHR *features = (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext; - features->shaderFloat16 = pdevice->rad_info.chip_class >= VI && HAVE_LLVM >= 0x0800; + features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800; features->shaderInt8 = true; break; } @@ -953,6 +964,18 @@ void radv_GetPhysicalDeviceFeatures2( features->computeDerivativeGroupLinear = true; break; } + case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: { + VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features = + (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext; + features->ycbcrImageArrays = true; + break; + } + case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: { + VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features = + (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext; + features->uniformBufferStandardLayout = true; + break; + } default: break; } @@ -1074,7 +1097,7 @@ void radv_GetPhysicalDeviceProperties( .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT, .sampledImageDepthSampleCounts = sample_counts, .sampledImageStencilSampleCounts = sample_counts, - .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT, + .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT, .maxSampleMaskWords = 1, .timestampComputeAndGraphics = true, .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq, @@ -1163,7 +1186,7 @@ void radv_GetPhysicalDeviceProperties2( VK_SUBGROUP_FEATURE_BALLOT_BIT | VK_SUBGROUP_FEATURE_QUAD_BIT | VK_SUBGROUP_FEATURE_VOTE_BIT; - if (pdevice->rad_info.chip_class >= VI) { + if (pdevice->rad_info.chip_class >= GFX8) { properties->supportedOperations |= VK_SUBGROUP_FEATURE_ARITHMETIC_BIT | VK_SUBGROUP_FEATURE_SHUFFLE_BIT | @@ -1215,12 +1238,12 @@ void radv_GetPhysicalDeviceProperties2( properties->sgprsPerSimd = ac_get_num_physical_sgprs(pdevice->rad_info.chip_class); properties->minSgprAllocation = - pdevice->rad_info.chip_class >= VI ? 16 : 8; + pdevice->rad_info.chip_class >= GFX8 ? 16 : 8; properties->maxSgprAllocation = pdevice->rad_info.family == CHIP_TONGA || pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104; properties->sgprAllocationGranularity = - pdevice->rad_info.chip_class >= VI ? 16 : 8; + pdevice->rad_info.chip_class >= GFX8 ? 16 : 8; /* VGPR. */ properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS; @@ -1331,7 +1354,7 @@ void radv_GetPhysicalDeviceProperties2( properties->maxTransformFeedbackBufferDataSize = UINT32_MAX; properties->maxTransformFeedbackBufferDataStride = 512; properties->transformFeedbackQueries = true; - properties->transformFeedbackStreamsLinesTriangles = false; + properties->transformFeedbackStreamsLinesTriangles = true; properties->transformFeedbackRasterizationStreamSelect = false; properties->transformFeedbackDraw = true; break; @@ -1347,6 +1370,19 @@ void radv_GetPhysicalDeviceProperties2( props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT; break; } + case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: { + VkPhysicalDeviceSampleLocationsPropertiesEXT *properties = + (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext; + properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT | + VK_SAMPLE_COUNT_4_BIT | + VK_SAMPLE_COUNT_8_BIT; + properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 }; + properties->sampleLocationCoordinateRange[0] = 0.0f; + properties->sampleLocationCoordinateRange[1] = 0.9375f; + properties->sampleLocationSubPixelBits = 4; + properties->variableSampleLocations = VK_FALSE; + break; + } default: break; } @@ -1470,40 +1506,46 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice, * Note that the application heap usages are not really accurate (eg. * in presence of shared buffers). */ - if (vram_size) { - heap_usage = device->ws->query_value(device->ws, - RADEON_ALLOCATED_VRAM); + for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) { + uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex; - heap_budget = vram_size - - device->ws->query_value(device->ws, RADEON_VRAM_USAGE) + - heap_usage; + switch (device->mem_type_indices[i]) { + case RADV_MEM_TYPE_VRAM: + heap_usage = device->ws->query_value(device->ws, + RADEON_ALLOCATED_VRAM); - memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget; - memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage; - } - - if (visible_vram_size) { - heap_usage = device->ws->query_value(device->ws, - RADEON_ALLOCATED_VRAM_VIS); + heap_budget = vram_size - + device->ws->query_value(device->ws, RADEON_VRAM_USAGE) + + heap_usage; - heap_budget = visible_vram_size - - device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) + - heap_usage; + memoryBudget->heapBudget[heap_index] = heap_budget; + memoryBudget->heapUsage[heap_index] = heap_usage; + break; + case RADV_MEM_TYPE_VRAM_CPU_ACCESS: + heap_usage = device->ws->query_value(device->ws, + RADEON_ALLOCATED_VRAM_VIS); - memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget; - memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage; - } + heap_budget = visible_vram_size - + device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) + + heap_usage; - if (gtt_size) { - heap_usage = device->ws->query_value(device->ws, - RADEON_ALLOCATED_GTT); + memoryBudget->heapBudget[heap_index] = heap_budget; + memoryBudget->heapUsage[heap_index] = heap_usage; + break; + case RADV_MEM_TYPE_GTT_WRITE_COMBINE: + heap_usage = device->ws->query_value(device->ws, + RADEON_ALLOCATED_GTT); - heap_budget = gtt_size - - device->ws->query_value(device->ws, RADEON_GTT_USAGE) + - heap_usage; + heap_budget = gtt_size - + device->ws->query_value(device->ws, RADEON_GTT_USAGE) + + heap_usage; - memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget; - memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage; + memoryBudget->heapBudget[heap_index] = heap_budget; + memoryBudget->heapUsage[heap_index] = heap_usage; + break; + default: + break; + } } /* The heapBudget and heapUsage values must be zero for array elements @@ -1855,7 +1897,7 @@ VkResult radv_CreateDevice( device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1); - if (device->physical_device->rad_info.chip_class >= CIK) { + if (device->physical_device->rad_info.chip_class >= GFX7) { /* If the KMD allows it (there is a KMD hw register for it), * allow launching waves out-of-order. */ @@ -1867,7 +1909,7 @@ VkResult radv_CreateDevice( device->tess_offchip_block_dw_size = device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192; device->has_distributed_tess = - device->physical_device->rad_info.chip_class >= VI && + device->physical_device->rad_info.chip_class >= GFX8 && device->physical_device->rad_info.max_se >= 2; if (getenv("RADV_TRACE_FILE")) { @@ -1910,7 +1952,7 @@ VkResult radv_CreateDevice( device->ws->cs_finalize(device->empty_cs[family]); } - if (device->physical_device->rad_info.chip_class >= CIK) + if (device->physical_device->rad_info.chip_class >= GFX7) cik_create_gfx_config(device); VkPipelineCacheCreateInfo ci; @@ -2210,7 +2252,7 @@ fill_geom_tess_rings(struct radv_queue *queue, static unsigned radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p) { - bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK && + bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 && device->physical_device->rad_info.family != CHIP_CARRIZO && device->physical_device->rad_info.family != CHIP_STONEY; unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64; @@ -2221,7 +2263,7 @@ radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buff /* * Per RadeonSI: * This must be one less than the maximum number due to a hw limitation. - * Various hardware bugs in SI, CIK, and GFX9 need this. + * Various hardware bugs need thGFX7 * * Per AMDVLK: * Vega10 should limit max_offchip_buffers to 508 (4 * 127). @@ -2231,8 +2273,8 @@ radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buff * Follow AMDVLK here. */ if (device->physical_device->rad_info.family == CHIP_VEGA10 || - device->physical_device->rad_info.chip_class == CIK || - device->physical_device->rad_info.chip_class == SI) + device->physical_device->rad_info.chip_class == GFX7 || + device->physical_device->rad_info.chip_class == GFX6) --max_offchip_buffers_per_se; max_offchip_buffers = max_offchip_buffers_per_se * @@ -2250,11 +2292,11 @@ radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buff } switch (device->physical_device->rad_info.chip_class) { - case SI: + case GFX6: max_offchip_buffers = MIN2(max_offchip_buffers, 126); break; - case CIK: - case VI: + case GFX7: + case GFX8: case GFX9: default: max_offchip_buffers = MIN2(max_offchip_buffers, 508); @@ -2262,8 +2304,8 @@ radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buff } *max_offchip_buffers_p = max_offchip_buffers; - if (device->physical_device->rad_info.chip_class >= CIK) { - if (device->physical_device->rad_info.chip_class >= VI) + if (device->physical_device->rad_info.chip_class >= GFX7) { + if (device->physical_device->rad_info.chip_class >= GFX8) --max_offchip_buffers; hs_offchip_param = S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) | @@ -2291,7 +2333,7 @@ radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs, if (gsvs_ring_bo) radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo); - if (queue->device->physical_device->rad_info.chip_class >= CIK) { + if (queue->device->physical_device->rad_info.chip_class >= GFX7) { radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2); radeon_emit(cs, esgs_ring_size >> 8); radeon_emit(cs, gsvs_ring_size >> 8); @@ -2316,7 +2358,7 @@ radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs, radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo); - if (queue->device->physical_device->rad_info.chip_class >= CIK) { + if (queue->device->physical_device->rad_info.chip_class >= GFX7) { radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE, S_030938_SIZE(tf_ring_size / 4)); radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, @@ -2636,7 +2678,7 @@ radv_get_preamble_cs(struct radv_queue *queue, queue->device->physical_device->rad_info.chip_class, NULL, 0, queue->queue_family_index == RING_COMPUTE && - queue->device->physical_device->rad_info.chip_class >= CIK, + queue->device->physical_device->rad_info.chip_class >= GFX7, (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) | RADV_CMD_FLAG_INV_ICACHE | RADV_CMD_FLAG_INV_SMEM_L1 | @@ -2648,7 +2690,7 @@ radv_get_preamble_cs(struct radv_queue *queue, queue->device->physical_device->rad_info.chip_class, NULL, 0, queue->queue_family_index == RING_COMPUTE && - queue->device->physical_device->rad_info.chip_class >= CIK, + queue->device->physical_device->rad_info.chip_class >= GFX7, RADV_CMD_FLAG_INV_ICACHE | RADV_CMD_FLAG_INV_SMEM_L1 | RADV_CMD_FLAG_INV_VMEM_L1 | @@ -3024,7 +3066,6 @@ VkResult radv_QueueSubmit( if (result != VK_SUCCESS) return result; } - fence->submitted = true; } return VK_SUCCESS; @@ -3120,6 +3161,23 @@ VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr( return radv_GetInstanceProcAddr(instance, pName); } +PUBLIC +VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr( + VkInstance _instance, + const char* pName); + +PUBLIC +VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr( + VkInstance _instance, + const char* pName) +{ + RADV_FROM_HANDLE(radv_instance, instance, _instance); + + return radv_lookup_physical_device_entrypoint_checked(pName, + instance ? instance->apiVersion : 0, + instance ? &instance->enabled_extensions : NULL); +} + PFN_vkVoidFunction radv_GetDeviceProcAddr( VkDevice _device, const char* pName) @@ -3632,8 +3690,6 @@ radv_sparse_image_opaque_bind_memory(struct radv_device *device, } fence_emitted = true; - if (fence) - fence->submitted = true; } radv_free_sem_info(&sem_info); @@ -3646,7 +3702,6 @@ radv_sparse_image_opaque_bind_memory(struct radv_device *device, if (result != VK_SUCCESS) return result; } - fence->submitted = true; } return VK_SUCCESS; @@ -3672,8 +3727,6 @@ VkResult radv_CreateFence( return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); fence->fence_wsi = NULL; - fence->submitted = false; - fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT); fence->temp_syncobj = 0; if (device->always_use_syncobj || handleTypes) { int ret = device->ws->create_syncobj(device->ws, &fence->syncobj); @@ -3692,6 +3745,8 @@ VkResult radv_CreateFence( return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); } fence->syncobj = 0; + if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) + device->ws->signal_fence(fence->fence); } *pFence = radv_fence_to_handle(fence); @@ -3739,13 +3794,14 @@ static uint64_t radv_get_absolute_timeout(uint64_t timeout) } -static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences) +static bool radv_all_fences_plain_and_submitted(struct radv_device *device, + uint32_t fenceCount, const VkFence *pFences) { for (uint32_t i = 0; i < fenceCount; ++i) { RADV_FROM_HANDLE(radv_fence, fence, pFences[i]); if (fence->fence == NULL || fence->syncobj || - fence->temp_syncobj || - (!fence->signalled && !fence->submitted)) + fence->temp_syncobj || fence->fence_wsi || + (!device->ws->is_fence_waitable(fence->fence))) return false; } return true; @@ -3791,7 +3847,7 @@ VkResult radv_WaitForFences( if (!waitAll && fenceCount > 1) { /* Not doing this by default for waitAll, due to needing to allocate twice. */ - if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) { + if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) { uint32_t wait_count = 0; struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount); if (!fences) @@ -3800,7 +3856,7 @@ VkResult radv_WaitForFences( for (uint32_t i = 0; i < fenceCount; ++i) { RADV_FROM_HANDLE(radv_fence, fence, pFences[i]); - if (fence->signalled) { + if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) { free(fences); return VK_SUCCESS; } @@ -3840,23 +3896,11 @@ VkResult radv_WaitForFences( continue; } - if (fence->signalled) - continue; - if (fence->fence) { - if (!fence->submitted) { - while(radv_get_current_time() <= timeout && - !fence->submitted) + if (!device->ws->is_fence_waitable(fence->fence)) { + while(!device->ws->is_fence_waitable(fence->fence) && + radv_get_current_time() <= timeout) /* Do nothing */; - - if (!fence->submitted) - return VK_TIMEOUT; - - /* Recheck as it may have been set by - * submitting operations. */ - - if (fence->signalled) - continue; } expired = device->ws->fence_wait(device->ws, @@ -3871,8 +3915,6 @@ VkResult radv_WaitForFences( if (result != VK_SUCCESS) return result; } - - fence->signalled = true; } return VK_SUCCESS; @@ -3886,7 +3928,8 @@ VkResult radv_ResetFences(VkDevice _device, for (unsigned i = 0; i < fenceCount; ++i) { RADV_FROM_HANDLE(radv_fence, fence, pFences[i]); - fence->submitted = fence->signalled = false; + if (fence->fence) + device->ws->reset_fence(fence->fence); /* Per spec, we first restore the permanent payload, and then reset, so * having a temp syncobj should not skip resetting the permanent syncobj. */ @@ -3918,10 +3961,6 @@ VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence) return success ? VK_SUCCESS : VK_NOT_READY; } - if (fence->signalled) - return VK_SUCCESS; - if (!fence->submitted) - return VK_NOT_READY; if (fence->fence) { if (!device->ws->fence_wait(device->ws, fence->fence, false, 0)) return VK_NOT_READY; @@ -4142,12 +4181,12 @@ VkDeviceAddress radv_GetBufferDeviceAddressEXT( static inline unsigned -si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil) +si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil) { if (stencil) - return image->surface.u.legacy.stencil_tiling_index[level]; + return plane->surface.u.legacy.stencil_tiling_index[level]; else - return image->surface.u.legacy.tiling_index[level]; + return plane->surface.u.legacy.tiling_index[level]; } static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview) @@ -4164,13 +4203,13 @@ radv_init_dcc_control_reg(struct radv_device *device, unsigned max_compressed_block_size; unsigned independent_64b_blocks; - if (!radv_image_has_dcc(iview->image)) + if (!radv_dcc_enabled(iview->image, iview->base_mip)) return 0; if (iview->image->info.samples > 1) { - if (iview->image->surface.bpe == 1) + if (iview->image->planes[0].surface.bpe == 1) max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B; - else if (iview->image->surface.bpe == 2) + else if (iview->image->planes[0].surface.bpe == 2) max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B; } @@ -4215,7 +4254,8 @@ radv_initialise_color_surface(struct radv_device *device, unsigned ntype, format, swap, endian; unsigned blend_clamp = 0, blend_bypass = 0; uint64_t va; - const struct radeon_surf *surf = &iview->image->surface; + const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id]; + const struct radeon_surf *surf = &plane->surface; desc = vk_format_description(iview->vk_format); @@ -4224,35 +4264,37 @@ radv_initialise_color_surface(struct radv_device *device, /* Intensity is implemented as Red, so treat it that way. */ cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1); - va = radv_buffer_get_va(iview->bo) + iview->image->offset; + va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset; cb->cb_color_base = va >> 8; if (device->physical_device->rad_info.chip_class >= GFX9) { struct gfx9_surf_meta_flags meta; if (iview->image->dcc_offset) - meta = iview->image->surface.u.gfx9.dcc; + meta = surf->u.gfx9.dcc; else - meta = iview->image->surface.u.gfx9.cmask; + meta = surf->u.gfx9.cmask; - cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) | - S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) | + cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) | + S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) | S_028C74_RB_ALIGNED(meta.rb_aligned) | S_028C74_PIPE_ALIGNED(meta.pipe_aligned); - cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8; - cb->cb_color_base |= iview->image->surface.tile_swizzle; + cb->cb_color_base += surf->u.gfx9.surf_offset >> 8; + cb->cb_color_base |= surf->tile_swizzle; + + cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch); } else { const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip]; unsigned pitch_tile_max, slice_tile_max, tile_mode_index; cb->cb_color_base += level_info->offset >> 8; if (level_info->mode == RADEON_SURF_MODE_2D) - cb->cb_color_base |= iview->image->surface.tile_swizzle; + cb->cb_color_base |= surf->tile_swizzle; pitch_tile_max = level_info->nblk_x / 8 - 1; slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1; - tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false); + tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false); cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max); cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max); @@ -4261,13 +4303,13 @@ radv_initialise_color_surface(struct radv_device *device, cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index); if (radv_image_has_fmask(iview->image)) { - if (device->physical_device->rad_info.chip_class >= CIK) + if (device->physical_device->rad_info.chip_class >= GFX7) cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1); cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index); cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max); } else { /* This must be set for fast clear to work without FMASK. */ - if (device->physical_device->rad_info.chip_class >= CIK) + if (device->physical_device->rad_info.chip_class >= GFX7) cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max); cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index); cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max); @@ -4281,8 +4323,13 @@ radv_initialise_color_surface(struct radv_device *device, va = radv_buffer_get_va(iview->bo) + iview->image->offset; va += iview->image->dcc_offset; + + if (radv_dcc_enabled(iview->image, iview->base_mip) && + device->physical_device->rad_info.chip_class <= GFX8) + va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset; + cb->cb_dcc_base = va >> 8; - cb->cb_dcc_base |= iview->image->surface.tile_swizzle; + cb->cb_dcc_base |= surf->tile_swizzle; uint32_t max_slice = radv_surface_max_layer_count(iview) - 1; cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) | @@ -4347,10 +4394,24 @@ radv_initialise_color_surface(struct radv_device *device, S_028C70_ENDIAN(endian); if (radv_image_has_fmask(iview->image)) { cb->cb_color_info |= S_028C70_COMPRESSION(1); - if (device->physical_device->rad_info.chip_class == SI) { + if (device->physical_device->rad_info.chip_class == GFX6) { unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height); cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); } + + if (radv_image_is_tc_compat_cmask(iview->image)) { + /* Allow the texture block to read FMASK directly + * without decompressing it. This bit must be cleared + * when performing FMASK_DECOMPRESS or DCC_COMPRESS, + * otherwise the operation doesn't happen. + */ + cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1); + + /* Set CMASK into a tiling format that allows the + * texture block to read it. + */ + cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2); + } } if (radv_image_has_cmask(iview->image) && @@ -4364,20 +4425,24 @@ radv_initialise_color_surface(struct radv_device *device, /* This must be set for fast clear to work without FMASK. */ if (!radv_image_has_fmask(iview->image) && - device->physical_device->rad_info.chip_class == SI) { - unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh); + device->physical_device->rad_info.chip_class == GFX6) { + unsigned bankh = util_logbase2(surf->u.legacy.bankh); cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh); } if (device->physical_device->rad_info.chip_class >= GFX9) { + const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format); + unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ? (iview->extent.depth - 1) : (iview->image->info.array_size - 1); + unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1); + unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1); cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip); cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) | - S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type); - cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) | - S_028C68_MIP0_HEIGHT(iview->extent.height - 1) | + S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type); + cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) | + S_028C68_MIP0_HEIGHT(height - 1) | S_028C68_MAX_MIP(iview->image->info.levels - 1); } } @@ -4430,6 +4495,11 @@ radv_initialise_ds_surface(struct radv_device *device, unsigned format, stencil_format; uint64_t va, s_offs, z_offs; bool stencil_only = false; + const struct radv_image_plane *plane = &iview->image->planes[0]; + const struct radeon_surf *surf = &plane->surface; + + assert(vk_format_get_plane_count(iview->image->vk_format) == 1); + memset(ds, 0, sizeof(*ds)); switch (iview->image->vk_format) { case VK_FORMAT_D24_UNORM_S8_UINT: @@ -4456,7 +4526,7 @@ radv_initialise_ds_surface(struct radv_device *device, } format = radv_translate_dbformat(iview->image->vk_format); - stencil_format = iview->image->surface.has_stencil ? + stencil_format = surf->has_stencil ? V_028044_STENCIL_8 : V_028044_STENCIL_INVALID; uint32_t max_slice = radv_surface_max_layer_count(iview) - 1; @@ -4470,19 +4540,19 @@ radv_initialise_ds_surface(struct radv_device *device, s_offs = z_offs = va; if (device->physical_device->rad_info.chip_class >= GFX9) { - assert(iview->image->surface.u.gfx9.surf_offset == 0); - s_offs += iview->image->surface.u.gfx9.stencil_offset; + assert(surf->u.gfx9.surf_offset == 0); + s_offs += surf->u.gfx9.stencil_offset; ds->db_z_info = S_028038_FORMAT(format) | S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) | - S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) | + S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) | S_028038_MAXMIP(iview->image->info.levels - 1) | S_028038_ZRANGE_PRECISION(1); ds->db_stencil_info = S_02803C_FORMAT(stencil_format) | - S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode); + S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode); - ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch); - ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch); + ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch); + ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch); ds->db_depth_view |= S_028008_MIPID(level); ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) | @@ -4500,24 +4570,24 @@ radv_initialise_ds_surface(struct radv_device *device, ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1); } - if (!iview->image->surface.has_stencil) + if (!surf->has_stencil) /* Use all of the htile_buffer for depth if there's no stencil. */ ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1); va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->htile_offset; ds->db_htile_data_base = va >> 8; ds->db_htile_surface = S_028ABC_FULL_CACHE(1) | - S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) | - S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned); + S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned) | + S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned); } } else { - const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level]; + const struct legacy_surf_level *level_info = &surf->u.legacy.level[level]; if (stencil_only) - level_info = &iview->image->surface.u.legacy.stencil_level[level]; + level_info = &surf->u.legacy.stencil_level[level]; - z_offs += iview->image->surface.u.legacy.level[level].offset; - s_offs += iview->image->surface.u.legacy.stencil_level[level].offset; + z_offs += surf->u.legacy.level[level].offset; + s_offs += surf->u.legacy.stencil_level[level].offset; ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image)); ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1); @@ -4526,11 +4596,11 @@ radv_initialise_ds_surface(struct radv_device *device, if (iview->image->info.samples > 1) ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples)); - if (device->physical_device->rad_info.chip_class >= CIK) { + if (device->physical_device->rad_info.chip_class >= GFX7) { struct radeon_info *info = &device->physical_device->rad_info; - unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level]; - unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level]; - unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index; + unsigned tiling_index = surf->u.legacy.tiling_index[level]; + unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level]; + unsigned macro_index = surf->u.legacy.macro_tile_index; unsigned tile_mode = info->si_tile_mode_array[tiling_index]; unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index]; unsigned macro_mode = info->cik_macrotile_mode_array[macro_index]; @@ -4548,9 +4618,9 @@ radv_initialise_ds_surface(struct radv_device *device, ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode)); ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode)); } else { - unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false); + unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false); ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); - tile_mode_index = si_tile_mode_index(iview->image, level, true); + tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true); ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); if (stencil_only) ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); @@ -4563,7 +4633,7 @@ radv_initialise_ds_surface(struct radv_device *device, if (radv_htile_enabled(iview->image, level)) { ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1); - if (!iview->image->surface.has_stencil && + if (!surf->has_stencil && !radv_image_is_tc_compat_htile(iview->image)) /* Use all of the htile_buffer for depth if there's no stencil. */ ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1); @@ -4613,10 +4683,10 @@ VkResult radv_CreateFramebuffer( VkImageView _iview = pCreateInfo->pAttachments[i]; struct radv_image_view *iview = radv_image_view_from_handle(_iview); framebuffer->attachments[i].attachment = iview; - if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) { - radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview); - } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) { + if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) { radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview); + } else { + radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview); } framebuffer->width = MIN2(framebuffer->width, iview->extent.width); framebuffer->height = MIN2(framebuffer->height, iview->extent.height); @@ -4785,7 +4855,7 @@ radv_init_sampler(struct radv_device *device, { uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo); uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso); - bool is_vi = (device->physical_device->rad_info.chip_class >= VI); + bool is_vi = (device->physical_device->rad_info.chip_class >= GFX8); unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND; const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction = @@ -4813,7 +4883,7 @@ radv_init_sampler(struct radv_device *device, S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) | S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) | S_008F38_MIP_POINT_PRECLAMP(0) | - S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) | + S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) | S_008F38_FILTER_PREC_FIX(1) | S_008F38_ANISO_OVERRIDE(is_vi)); sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) | @@ -4829,6 +4899,10 @@ VkResult radv_CreateSampler( RADV_FROM_HANDLE(radv_device, device, _device); struct radv_sampler *sampler; + const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion = + vk_find_struct_const(pCreateInfo->pNext, + SAMPLER_YCBCR_CONVERSION_INFO); + assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO); sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8, @@ -4837,6 +4911,8 @@ VkResult radv_CreateSampler( return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); radv_init_sampler(device, sampler, pCreateInfo); + + sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL; *pSampler = radv_sampler_to_handle(sampler); return VK_SUCCESS; @@ -4895,7 +4971,7 @@ vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion) * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR, * because the loader no longer does so. */ - *pSupportedVersion = MIN2(*pSupportedVersion, 3u); + *pSupportedVersion = MIN2(*pSupportedVersion, 4u); return VK_SUCCESS; } @@ -5333,3 +5409,17 @@ VkResult radv_GetCalibratedTimestampsEXT( return VK_SUCCESS; } + +void radv_GetPhysicalDeviceMultisamplePropertiesEXT( + VkPhysicalDevice physicalDevice, + VkSampleCountFlagBits samples, + VkMultisamplePropertiesEXT* pMultisampleProperties) +{ + if (samples & (VK_SAMPLE_COUNT_2_BIT | + VK_SAMPLE_COUNT_4_BIT | + VK_SAMPLE_COUNT_8_BIT)) { + pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 }; + } else { + pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 }; + } +}