X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_image.c;h=dd3189c67d0c669f33312cc2c1f9c3d9502ad8a1;hb=e45fe0ed66af32a36b03d5a5141e68fad0d15e6a;hp=c9e8bb3d430122484ffae2e1de1614eab1ac1d8b;hpb=ad42e2abb8507dd85f07e5aad539154b0d5c78ea;p=mesa.git diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index c9e8bb3d430..dd3189c67d0 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -35,7 +35,7 @@ #include "util/debug.h" #include "util/u_atomic.h" static unsigned -radv_choose_tiling(struct radv_device *Device, +radv_choose_tiling(struct radv_device *device, const struct radv_image_create_info *create_info) { const VkImageCreateInfo *pCreateInfo = create_info->vk_info; @@ -46,14 +46,15 @@ radv_choose_tiling(struct radv_device *Device, } if (!vk_format_is_compressed(pCreateInfo->format) && - !vk_format_is_depth_or_stencil(pCreateInfo->format)) { + !vk_format_is_depth_or_stencil(pCreateInfo->format) + && device->physical_device->rad_info.chip_class <= VI) { + /* this causes hangs in some VK CTS tests on GFX9. */ /* Textures with a very small height are recommended to be linear. */ if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D || /* Only very thin and long 2D textures should benefit from * linear_aligned. */ (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2)) return RADEON_SURF_MODE_LINEAR_ALIGNED; - } /* MSAA resources must be 2D tiled. */ @@ -62,6 +63,46 @@ radv_choose_tiling(struct radv_device *Device, return RADEON_SURF_MODE_2D; } + +static bool +radv_image_is_tc_compat_htile(struct radv_device *device, + const VkImageCreateInfo *pCreateInfo) +{ + /* TC-compat HTILE is only available for GFX8+. */ + if (device->physical_device->rad_info.chip_class < VI) + return false; + + if (pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) + return false; + + if (pCreateInfo->flags & (VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT | + VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR)) + return false; + + if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) + return false; + + if (pCreateInfo->mipLevels > 1) + return false; + + /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts + * tests - disable for now */ + if (pCreateInfo->samples >= 2 && + pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT) + return false; + + /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only + * supports 32-bit. Though, it's possible to enable TC-compat for + * 16-bit depth surfaces if no Z planes are compressed. + */ + if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT && + pCreateInfo->format != VK_FORMAT_D32_SFLOAT && + pCreateInfo->format != VK_FORMAT_D16_UNORM) + return false; + + return true; +} + static int radv_init_surface(struct radv_device *device, struct radeon_surf *surface, @@ -108,6 +149,8 @@ radv_init_surface(struct radv_device *device, if (is_depth) { surface->flags |= RADEON_SURF_ZBUFFER; + if (radv_image_is_tc_compat_htile(device, pCreateInfo)) + surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE; } if (is_stencil) @@ -115,19 +158,41 @@ radv_init_surface(struct radv_device *device, surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE; - if ((pCreateInfo->usage & (VK_IMAGE_USAGE_TRANSFER_SRC_BIT | - VK_IMAGE_USAGE_STORAGE_BIT)) || - (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) || + bool dcc_compatible_formats = radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable); + if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) { + const struct VkImageFormatListCreateInfoKHR *format_list = + (const struct VkImageFormatListCreateInfoKHR *) + vk_find_struct_const(pCreateInfo->pNext, + IMAGE_FORMAT_LIST_CREATE_INFO_KHR); + + /* We have to ignore the existence of the list if viewFormatCount = 0 */ + if (format_list && format_list->viewFormatCount) { + /* compatibility is transitive, so we only need to check + * one format with everything else. */ + for (unsigned i = 0; i < format_list->viewFormatCount; ++i) { + if (!radv_dcc_formats_compatible(pCreateInfo->format, + format_list->pViewFormats[i])) + dcc_compatible_formats = false; + } + } else { + dcc_compatible_formats = false; + } + } + + if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) || + (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT_KHR) || + !dcc_compatible_formats || (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) || + pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 || device->physical_device->rad_info.chip_class < VI || - create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC) || - !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable)) + create_info->scanout || (device->instance->debug_flags & RADV_DEBUG_NO_DCC) || + pCreateInfo->samples >= 2) surface->flags |= RADEON_SURF_DISABLE_DCC; if (create_info->scanout) surface->flags |= RADEON_SURF_SCANOUT; return 0; } -#define ATI_VENDOR_ID 0x1002 + static uint32_t si_get_bo_metadata_word1(struct radv_device *device) { return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id; @@ -170,7 +235,7 @@ radv_make_buffer_descriptor(struct radv_device *device, { const struct vk_format_description *desc; unsigned stride; - uint64_t gpu_address = device->ws->buffer_get_va(buffer->bo); + uint64_t gpu_address = radv_buffer_get_va(buffer->bo); uint64_t va = gpu_address + buffer->offset; unsigned num_format, data_format; int first_non_void; @@ -205,9 +270,9 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, const struct legacy_surf_level *base_level_info, unsigned base_level, unsigned first_level, unsigned block_width, bool is_stencil, - uint32_t *state) + bool is_storage_image, uint32_t *state) { - uint64_t gpu_address = image->bo ? device->ws->buffer_get_va(image->bo) + image->offset : 0; + uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0; uint64_t va = gpu_address; enum chip_class chip_class = device->physical_device->rad_info.chip_class; uint64_t meta_va = 0; @@ -229,10 +294,16 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, if (chip_class >= VI) { state[6] &= C_008F28_COMPRESSION_EN; state[7] = 0; - if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) { + if (!is_storage_image && radv_vi_dcc_enabled(image, first_level)) { meta_va = gpu_address + image->dcc_offset; if (chip_class <= VI) meta_va += base_level_info->dcc_offset; + } else if(!is_storage_image && image->tc_compatible_htile && + image->surface.htile_size) { + meta_va = gpu_address + image->htile_offset; + } + + if (meta_va) { state[6] |= S_008F28_COMPRESSION_EN(1); state[7] = meta_va >> 8; state[7] |= image->surface.tile_swizzle; @@ -279,10 +350,14 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, } static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type, - unsigned nr_layers, unsigned nr_samples, bool is_storage_image) + unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9) { if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE; + + /* GFX9 allocates 1D textures as 2D. */ + if (gfx9 && image_type == VK_IMAGE_TYPE_1D) + image_type = VK_IMAGE_TYPE_2D; switch (image_type) { case VK_IMAGE_TYPE_1D: return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D; @@ -301,7 +376,7 @@ static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type, } } -static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4]) +static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4]) { unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW; @@ -372,8 +447,17 @@ si_make_texture_descriptor(struct radv_device *device, data_format = 0; } + /* S8 with either Z16 or Z32 HTILE need a special format. */ + if (device->physical_device->rad_info.chip_class >= GFX9 && + vk_format == VK_FORMAT_S8_UINT && + image->tc_compatible_htile) { + if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT) + data_format = V_008F14_IMG_DATA_FORMAT_S8_32; + else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT) + data_format = V_008F14_IMG_DATA_FORMAT_S8_16; + } type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples, - is_storage_image); + is_storage_image, device->physical_device->rad_info.chip_class >= GFX9); if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) { height = 1; depth = image->info.array_size; @@ -406,7 +490,7 @@ si_make_texture_descriptor(struct radv_device *device, state[7] = 0; if (device->physical_device->rad_info.chip_class >= GFX9) { - unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle); + unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle); /* Depth is the the last accessible layer on Gfx9. * The hw doesn't need to know the total number of layers. @@ -444,7 +528,7 @@ si_make_texture_descriptor(struct radv_device *device, /* Initialize the sampler view for FMASK. */ if (image->fmask.size) { uint32_t fmask_format, num_format; - uint64_t gpu_address = device->ws->buffer_get_va(image->bo); + uint64_t gpu_address = radv_buffer_get_va(image->bo); uint64_t va; va = gpu_address + image->offset + image->fmask.offset; @@ -493,7 +577,7 @@ si_make_texture_descriptor(struct radv_device *device, S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) | S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) | - S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false)); + S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false, false)); fmask_state[4] = 0; fmask_state[5] = S_008F24_BASE_ARRAY(first_layer); fmask_state[6] = 0; @@ -547,7 +631,7 @@ radv_query_opaque_metadata(struct radv_device *device, desc, NULL); si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0, - image->surface.blk_w, false, desc); + image->surface.blk_w, false, false, desc); /* Clear the base address and set the relative DCC offset. */ desc[0] = 0; @@ -738,8 +822,7 @@ radv_image_alloc_cmask(struct radv_device *device, } static void -radv_image_alloc_dcc(struct radv_device *device, - struct radv_image *image) +radv_image_alloc_dcc(struct radv_image *image) { image->dcc_offset = align64(image->size, image->surface.dcc_alignment); /* + 16 for storing the clear values + dcc pred */ @@ -750,14 +833,8 @@ radv_image_alloc_dcc(struct radv_device *device, } static void -radv_image_alloc_htile(struct radv_device *device, - struct radv_image *image) +radv_image_alloc_htile(struct radv_image *image) { - if ((device->debug_flags & RADV_DEBUG_NO_HIZ) || image->info.levels > 1) { - image->surface.htile_size = 0; - return; - } - image->htile_offset = align64(image->size, image->surface.htile_alignment); /* + 8 for storing the clear values */ @@ -766,6 +843,59 @@ radv_image_alloc_htile(struct radv_device *device, image->alignment = align64(image->alignment, image->surface.htile_alignment); } +static inline bool +radv_image_can_enable_dcc_or_cmask(struct radv_image *image) +{ + if (image->info.samples <= 1 && + image->info.width * image->info.height <= 512 * 512) { + /* Do not enable CMASK or DCC for small surfaces where the cost + * of the eliminate pass can be higher than the benefit of fast + * clear. RadeonSI does this, but the image threshold is + * different. + */ + return false; + } + + return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT && + (image->exclusive || image->queue_family_mask == 1); +} + +static inline bool +radv_image_can_enable_dcc(struct radv_image *image) +{ + return radv_image_can_enable_dcc_or_cmask(image) && + image->surface.dcc_size; +} + +static inline bool +radv_image_can_enable_cmask(struct radv_image *image) +{ + if (image->surface.bpe > 8 && image->info.samples == 1) { + /* Do not enable CMASK for non-MSAA images (fast color clear) + * because 128 bit formats are not supported, but FMASK might + * still be used. + */ + return false; + } + + return radv_image_can_enable_dcc_or_cmask(image) && + image->info.levels == 1 && + image->info.depth == 1 && + !image->surface.is_linear; +} + +static inline bool +radv_image_can_enable_fmask(struct radv_image *image) +{ + return image->info.samples > 1 && vk_format_is_color(image->vk_format); +} + +static inline bool +radv_image_can_enable_htile(struct radv_image *image) +{ + return image->info.levels == 1 && vk_format_is_depth(image->vk_format); +} + VkResult radv_image_create(VkDevice _device, const struct radv_image_create_info *create_info, @@ -775,7 +905,6 @@ radv_image_create(VkDevice _device, RADV_FROM_HANDLE(radv_device, device, _device); const VkImageCreateInfo *pCreateInfo = create_info->vk_info; struct radv_image *image = NULL; - bool can_cmask_dcc = false; assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO); radv_assert(pCreateInfo->mipLevels > 0); @@ -785,12 +914,11 @@ radv_image_create(VkDevice _device, radv_assert(pCreateInfo->extent.height > 0); radv_assert(pCreateInfo->extent.depth > 0); - image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8, - VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); + image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8, + VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); if (!image) return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); - memset(image, 0, sizeof(*image)); image->type = pCreateInfo->imageType; image->info.width = pCreateInfo->extent.width; image->info.height = pCreateInfo->extent.height; @@ -826,24 +954,34 @@ radv_image_create(VkDevice _device, image->size = image->surface.surf_size; image->alignment = image->surface.surf_alignment; - if (image->exclusive || image->queue_family_mask == 1) - can_cmask_dcc = true; + if (!create_info->no_metadata_planes) { + /* Try to enable DCC first. */ + if (radv_image_can_enable_dcc(image)) { + radv_image_alloc_dcc(image); + } else { + /* When DCC cannot be enabled, try CMASK. */ + image->surface.dcc_size = 0; + if (radv_image_can_enable_cmask(image)) { + radv_image_alloc_cmask(device, image); + } + } - if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) && - image->surface.dcc_size && can_cmask_dcc) - radv_image_alloc_dcc(device, image); - else + /* Try to enable FMASK for multisampled images. */ + if (radv_image_can_enable_fmask(image)) { + radv_image_alloc_fmask(device, image); + } else { + /* Otherwise, try to enable HTILE for depth surfaces. */ + if (radv_image_can_enable_htile(image) && + !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) { + radv_image_alloc_htile(image); + image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE; + } else { + image->surface.htile_size = 0; + } + } + } else { image->surface.dcc_size = 0; - - if ((pCreateInfo->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) && - pCreateInfo->mipLevels == 1 && - !image->surface.dcc_size && image->info.depth == 1 && can_cmask_dcc) - radv_image_alloc_cmask(device, image); - if (image->info.samples > 1 && vk_format_is_color(pCreateInfo->format)) { - radv_image_alloc_fmask(device, image); - } else if (vk_format_is_depth(pCreateInfo->format)) { - - radv_image_alloc_htile(device, image); + image->surface.htile_size = 0; } if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) { @@ -874,31 +1012,31 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT; uint32_t blk_w; uint32_t *descriptor; - uint32_t *fmask_descriptor; + uint32_t hw_level = 0; if (is_storage_image) { descriptor = iview->storage_descriptor; - fmask_descriptor = iview->storage_fmask_descriptor; } else { descriptor = iview->descriptor; - fmask_descriptor = iview->fmask_descriptor; } assert(image->surface.blk_w % vk_format_get_blockwidth(image->vk_format) == 0); blk_w = image->surface.blk_w / vk_format_get_blockwidth(image->vk_format) * vk_format_get_blockwidth(iview->vk_format); + if (device->physical_device->rad_info.chip_class >= GFX9) + hw_level = iview->base_mip; si_make_texture_descriptor(device, image, is_storage_image, iview->type, iview->vk_format, components, - 0, iview->level_count - 1, + hw_level, hw_level + iview->level_count - 1, iview->base_layer, iview->base_layer + iview->layer_count - 1, iview->extent.width, iview->extent.height, iview->extent.depth, descriptor, - fmask_descriptor); + descriptor + 8); const struct legacy_surf_level *base_level_info = NULL; if (device->physical_device->rad_info.chip_class <= GFX9) { @@ -911,7 +1049,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, base_level_info, iview->base_mip, iview->base_mip, - blk_w, is_stencil, descriptor); + blk_w, is_stencil, is_storage_image, descriptor); } void @@ -961,10 +1099,55 @@ radv_image_view_init(struct radv_image_view *iview, } if (iview->vk_format != image->vk_format) { - iview->extent.width = round_up_u32(iview->extent.width * vk_format_get_blockwidth(iview->vk_format), - vk_format_get_blockwidth(image->vk_format)); - iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format), - vk_format_get_blockheight(image->vk_format)); + unsigned view_bw = vk_format_get_blockwidth(iview->vk_format); + unsigned view_bh = vk_format_get_blockheight(iview->vk_format); + unsigned img_bw = vk_format_get_blockwidth(image->vk_format); + unsigned img_bh = vk_format_get_blockheight(image->vk_format); + + iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw); + iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh); + + /* Comment ported from amdvlk - + * If we have the following image: + * Uncompressed pixels Compressed block sizes (4x4) + * mip0: 22 x 22 6 x 6 + * mip1: 11 x 11 3 x 3 + * mip2: 5 x 5 2 x 2 + * mip3: 2 x 2 1 x 1 + * mip4: 1 x 1 1 x 1 + * + * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is + * calculating the degradation of the block sizes down the mip-chain as follows (straight-up + * divide-by-two integer math): + * mip0: 6x6 + * mip1: 3x3 + * mip2: 1x1 + * mip3: 1x1 + * + * This means that mip2 will be missing texels. + * + * Fix this by calculating the base mip's width and height, then convert that, and round it + * back up to get the level 0 size. + * Clamp the converted size between the original values, and next power of two, which + * means we don't oversize the image. + */ + if (device->physical_device->rad_info.chip_class >= GFX9 && + vk_format_is_compressed(image->vk_format) && + !vk_format_is_compressed(iview->vk_format)) { + unsigned rounded_img_w = util_next_power_of_two(iview->extent.width); + unsigned rounded_img_h = util_next_power_of_two(iview->extent.height); + unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel); + unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel); + + lvl_width = round_up_u32(lvl_width * view_bw, img_bw); + lvl_height = round_up_u32(lvl_height * view_bh, img_bh); + + lvl_width <<= range->baseMipLevel; + lvl_height <<= range->baseMipLevel; + + iview->extent.width = CLAMP(lvl_width, iview->extent.width, rounded_img_w); + iview->extent.height = CLAMP(lvl_height, iview->extent.height, rounded_img_h); + } } iview->base_layer = range->baseArrayLayer; @@ -980,6 +1163,9 @@ bool radv_layout_has_htile(const struct radv_image *image, VkImageLayout layout, unsigned queue_mask) { + if (image->surface.htile_size && image->tc_compatible_htile) + return layout != VK_IMAGE_LAYOUT_GENERAL; + return image->surface.htile_size && (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL || layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) && @@ -990,6 +1176,9 @@ bool radv_layout_is_htile_compressed(const struct radv_image *image, VkImageLayout layout, unsigned queue_mask) { + if (image->surface.htile_size && image->tc_compatible_htile) + return layout != VK_IMAGE_LAYOUT_GENERAL; + return image->surface.htile_size && (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL || layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) && @@ -1004,6 +1193,18 @@ bool radv_layout_can_fast_clear(const struct radv_image *image, queue_mask == (1u << RADV_QUEUE_GENERAL); } +bool radv_layout_dcc_compressed(const struct radv_image *image, + VkImageLayout layout, + unsigned queue_mask) +{ + /* Don't compress compute transfer dst, as image stores are not supported. */ + if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL && + (queue_mask & (1u << RADV_QUEUE_COMPUTE))) + return false; + + return image->surface.num_dcc_levels > 0 && layout != VK_IMAGE_LAYOUT_GENERAL; +} + unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family) { @@ -1022,11 +1223,24 @@ radv_CreateImage(VkDevice device, const VkAllocationCallbacks *pAllocator, VkImage *pImage) { +#ifdef ANDROID + const VkNativeBufferANDROID *gralloc_info = + vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID); + + if (gralloc_info) + return radv_image_from_gralloc(device, pCreateInfo, gralloc_info, + pAllocator, pImage); +#endif + + const struct wsi_image_create_info *wsi_info = + vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA); + bool scanout = wsi_info && wsi_info->scanout; + return radv_image_create(device, &(struct radv_image_create_info) { .vk_info = pCreateInfo, - .scanout = false, - }, + .scanout = scanout, + }, pAllocator, pImage); } @@ -1044,27 +1258,41 @@ radv_DestroyImage(VkDevice _device, VkImage _image, if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) device->ws->buffer_destroy(image->bo); + if (image->owned_memory != VK_NULL_HANDLE) + radv_FreeMemory(_device, image->owned_memory, pAllocator); + vk_free2(&device->alloc, pAllocator, image); } void radv_GetImageSubresourceLayout( - VkDevice device, + VkDevice _device, VkImage _image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout) { RADV_FROM_HANDLE(radv_image, image, _image); + RADV_FROM_HANDLE(radv_device, device, _device); int level = pSubresource->mipLevel; int layer = pSubresource->arrayLayer; struct radeon_surf *surface = &image->surface; - pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer; - pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe; - pLayout->arrayPitch = surface->u.legacy.level[level].slice_size; - pLayout->depthPitch = surface->u.legacy.level[level].slice_size; - pLayout->size = surface->u.legacy.level[level].slice_size; - if (image->type == VK_IMAGE_TYPE_3D) - pLayout->size *= u_minify(image->info.depth, level); + if (device->physical_device->rad_info.chip_class >= GFX9) { + pLayout->offset = surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer; + pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe; + pLayout->arrayPitch = surface->u.gfx9.surf_slice_size; + pLayout->depthPitch = surface->u.gfx9.surf_slice_size; + pLayout->size = surface->u.gfx9.surf_slice_size; + if (image->type == VK_IMAGE_TYPE_3D) + pLayout->size *= u_minify(image->info.depth, level); + } else { + pLayout->offset = surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer; + pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe; + pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4; + pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4; + pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4; + if (image->type == VK_IMAGE_TYPE_3D) + pLayout->size *= u_minify(image->info.depth, level); + } } @@ -1103,8 +1331,7 @@ radv_DestroyImageView(VkDevice _device, VkImageView _iview, void radv_buffer_view_init(struct radv_buffer_view *view, struct radv_device *device, - const VkBufferViewCreateInfo* pCreateInfo, - struct radv_cmd_buffer *cmd_buffer) + const VkBufferViewCreateInfo* pCreateInfo) { RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer); @@ -1131,7 +1358,7 @@ radv_CreateBufferView(VkDevice _device, if (!view) return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); - radv_buffer_view_init(view, device, pCreateInfo, NULL); + radv_buffer_view_init(view, device, pCreateInfo); *pView = radv_buffer_view_to_handle(view);