X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_meta_buffer.c;h=28343ebd83ab9b7cba822694548c93bfd7154411;hb=cf89bdb9ba9c7a7ba39d142ee3c83e0379c2092a;hp=c8558216bf1ab9d03c87749ea1f07ac04f1ed498;hpb=6248fbe5e42ef2a620b4c3793af2b809fab6f169;p=mesa.git diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c index c8558216bf1..28343ebd83a 100644 --- a/src/amd/vulkan/radv_meta_buffer.c +++ b/src/amd/vulkan/radv_meta_buffer.c @@ -15,8 +15,8 @@ build_buffer_fill_shader(struct radv_device *dev) b.shader->info.cs.local_size[1] = 1; b.shader->info.cs.local_size[2] = 1; - nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0); - nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0); + nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b); + nir_ssa_def *wg_id = nir_load_work_group_id(&b); nir_ssa_def *block_size = nir_imm_ivec4(&b, b.shader->info.cs.local_size[0], b.shader->info.cs.local_size[1], @@ -25,14 +25,15 @@ build_buffer_fill_shader(struct radv_device *dev) nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id); nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16)); - offset = nir_swizzle(&b, offset, (unsigned[]) {0, 0, 0, 0}, 1, false); + offset = nir_channel(&b, offset, 0); nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader, nir_intrinsic_vulkan_resource_index); dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); + dst_buf->num_components = 1; nir_intrinsic_set_desc_set(dst_buf, 0); nir_intrinsic_set_binding(dst_buf, 0); - nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL); + nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, dst_buf->num_components, 32, NULL); nir_builder_instr_insert(&b, &dst_buf->instr); nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); @@ -43,13 +44,15 @@ build_buffer_fill_shader(struct radv_device *dev) nir_ssa_dest_init(&load->instr, &load->dest, 1, 32, "fill_value"); nir_builder_instr_insert(&b, &load->instr); - nir_ssa_def *swizzled_load = nir_swizzle(&b, &load->dest.ssa, (unsigned[]) { 0, 0, 0, 0}, 4, false); + nir_ssa_def *swizzled_load = nir_swizzle(&b, &load->dest.ssa, (unsigned[]) { 0, 0, 0, 0}, 4); nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo); store->src[0] = nir_src_for_ssa(swizzled_load); store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa); store->src[2] = nir_src_for_ssa(offset); nir_intrinsic_set_write_mask(store, 0xf); + nir_intrinsic_set_access(store, ACCESS_NON_READABLE); + nir_intrinsic_set_align(store, 16, 0); store->num_components = 4; nir_builder_instr_insert(&b, &store->instr); @@ -67,8 +70,8 @@ build_buffer_copy_shader(struct radv_device *dev) b.shader->info.cs.local_size[1] = 1; b.shader->info.cs.local_size[2] = 1; - nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0); - nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0); + nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b); + nir_ssa_def *wg_id = nir_load_work_group_id(&b); nir_ssa_def *block_size = nir_imm_ivec4(&b, b.shader->info.cs.local_size[0], b.shader->info.cs.local_size[1], @@ -77,22 +80,24 @@ build_buffer_copy_shader(struct radv_device *dev) nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id); nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16)); - offset = nir_swizzle(&b, offset, (unsigned[]) {0, 0, 0, 0}, 1, false); + offset = nir_channel(&b, offset, 0); nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader, nir_intrinsic_vulkan_resource_index); dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); + dst_buf->num_components = 1; nir_intrinsic_set_desc_set(dst_buf, 0); nir_intrinsic_set_binding(dst_buf, 0); - nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, 1, 32, NULL); + nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, dst_buf->num_components, 32, NULL); nir_builder_instr_insert(&b, &dst_buf->instr); nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader, nir_intrinsic_vulkan_resource_index); src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); + src_buf->num_components = 1; nir_intrinsic_set_desc_set(src_buf, 0); nir_intrinsic_set_binding(src_buf, 1); - nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, 1, 32, NULL); + nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, src_buf->num_components, 32, NULL); nir_builder_instr_insert(&b, &src_buf->instr); nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo); @@ -100,6 +105,7 @@ build_buffer_copy_shader(struct radv_device *dev) load->src[1] = nir_src_for_ssa(offset); nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL); load->num_components = 4; + nir_intrinsic_set_align(load, 16, 0); nir_builder_instr_insert(&b, &load->instr); nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo); @@ -107,6 +113,8 @@ build_buffer_copy_shader(struct radv_device *dev) store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa); store->src[2] = nir_src_for_ssa(offset); nir_intrinsic_set_write_mask(store, 0xf); + nir_intrinsic_set_access(store, ACCESS_NON_READABLE); + nir_intrinsic_set_align(store, 16, 0); store->num_components = 4; nir_builder_instr_insert(&b, &store->instr); @@ -410,8 +418,8 @@ uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, if (size >= RADV_BUFFER_OPS_CS_THRESHOLD) { fill_buffer_shader(cmd_buffer, bo, offset, size, value); flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH | - RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2; + RADV_CMD_FLAG_INV_VCACHE | + RADV_CMD_FLAG_WB_L2; } else if (size) { uint64_t va = radv_buffer_get_va(bo); va += offset; @@ -472,6 +480,13 @@ void radv_CmdCopyBuffer( RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); RADV_FROM_HANDLE(radv_buffer, src_buffer, srcBuffer); RADV_FROM_HANDLE(radv_buffer, dest_buffer, destBuffer); + bool old_predicating; + + /* VK_EXT_conditional_rendering says that copy commands should not be + * affected by conditional rendering. + */ + old_predicating = cmd_buffer->state.predicating; + cmd_buffer->state.predicating = false; for (unsigned r = 0; r < regionCount; r++) { uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset; @@ -481,6 +496,9 @@ void radv_CmdCopyBuffer( radv_copy_buffer(cmd_buffer, src_buffer->bo, dest_buffer->bo, src_offset, dest_offset, copy_size); } + + /* Restore conditional rendering. */ + cmd_buffer->state.predicating = old_predicating; } void radv_CmdUpdateBuffer( @@ -503,7 +521,7 @@ void radv_CmdUpdateBuffer( if (!dataSize) return; - if (dataSize < RADV_BUFFER_OPS_CS_THRESHOLD) { + if (dataSize < RADV_BUFFER_UPDATE_THRESHOLD) { si_emit_cache_flush(cmd_buffer); radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo); @@ -512,7 +530,7 @@ void radv_CmdUpdateBuffer( radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + words, 0)); radeon_emit(cmd_buffer->cs, S_370_DST_SEL(mec ? - V_370_MEM_ASYNC : V_370_MEMORY_SYNC) | + V_370_MEM : V_370_MEM_GRBM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_ME)); radeon_emit(cmd_buffer->cs, va);