X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_meta_bufimage.c;h=69e15d32135807c1519b815599890b7509c11399;hb=f944a59996287de85d4c6d9b7b000d25f41b1d79;hp=91af80c3921b48a1dc047fdcd415e66e8df5532c;hpb=78bef01da2b41fec6fb82d8e6ccacf594d0a6b93;p=mesa.git diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index 91af80c3921..69e15d32135 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -29,11 +29,15 @@ * Compute queue: implementation also of buffer->image, image->image, and image clear. */ +/* GFX9 needs to use a 3D sampler to access 3D resources, so the shader has the options + * for that. + */ static nir_shader * -build_nir_itob_compute_shader(struct radv_device *dev) +build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d) { nir_builder b; - const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D, + enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D; + const struct glsl_type *sampler_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT); @@ -42,7 +46,7 @@ build_nir_itob_compute_shader(struct radv_device *dev) false, GLSL_TYPE_FLOAT); nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL); - b.shader->info.name = ralloc_strdup(b.shader, "meta_itob_cs"); + b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_itob_cs_3d" : "meta_itob_cs"); b.shader->info.cs.local_size[0] = 16; b.shader->info.cs.local_size[1] = 16; b.shader->info.cs.local_size[2] = 1; @@ -69,32 +73,31 @@ build_nir_itob_compute_shader(struct radv_device *dev) nir_intrinsic_instr *offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_set_base(offset, 0); - nir_intrinsic_set_range(offset, 12); + nir_intrinsic_set_range(offset, 16); offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); - offset->num_components = 2; - nir_ssa_dest_init(&offset->instr, &offset->dest, 2, 32, "offset"); + offset->num_components = is_3d ? 3 : 2; + nir_ssa_dest_init(&offset->instr, &offset->dest, is_3d ? 3 : 2, 32, "offset"); nir_builder_instr_insert(&b, &offset->instr); nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_set_base(stride, 0); - nir_intrinsic_set_range(stride, 12); - stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8)); + nir_intrinsic_set_range(stride, 16); + stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12)); stride->num_components = 1; nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride"); nir_builder_instr_insert(&b, &stride->instr); nir_ssa_def *img_coord = nir_iadd(&b, global_id, &offset->dest.ssa); - nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2); - tex->sampler_dim = GLSL_SAMPLER_DIM_2D; + tex->sampler_dim = dim; tex->op = nir_texop_txf; tex->src[0].src_type = nir_tex_src_coord; - tex->src[0].src = nir_src_for_ssa(nir_channels(&b, img_coord, 0x3)); + tex->src[0].src = nir_src_for_ssa(nir_channels(&b, img_coord, is_3d ? 0x7 : 0x3)); tex->src[1].src_type = nir_tex_src_lod; tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0)); tex->dest_type = nir_type_float; tex->is_array = false; - tex->coord_components = 2; + tex->coord_components = is_3d ? 3 : 2; tex->texture = nir_deref_var_create(tex, input_img); tex->sampler = NULL; @@ -110,7 +113,7 @@ build_nir_itob_compute_shader(struct radv_device *dev) nir_ssa_def *coord = nir_vec4(&b, tmp, tmp, tmp, tmp); nir_ssa_def *outval = &tex->dest.ssa; - nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store); + nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_var_store); store->src[0] = nir_src_for_ssa(coord); store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); store->src[2] = nir_src_for_ssa(outval); @@ -126,10 +129,11 @@ radv_device_init_meta_itob_state(struct radv_device *device) { VkResult result; struct radv_shader_module cs = { .nir = NULL }; + struct radv_shader_module cs_3d = { .nir = NULL }; - zero(device->meta_state.itob); - - cs.nir = build_nir_itob_compute_shader(device); + cs.nir = build_nir_itob_compute_shader(device, false); + if (device->physical_device->rad_info.chip_class >= GFX9) + cs_3d.nir = build_nir_itob_compute_shader(device, true); /* * two descriptors one for the image being sampled @@ -170,7 +174,7 @@ radv_device_init_meta_itob_state(struct radv_device *device) .setLayoutCount = 1, .pSetLayouts = &device->meta_state.itob.img_ds_layout, .pushConstantRangeCount = 1, - .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 12}, + .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16}, }; result = radv_CreatePipelineLayout(radv_device_to_handle(device), @@ -204,47 +208,71 @@ radv_device_init_meta_itob_state(struct radv_device *device) if (result != VK_SUCCESS) goto fail; + if (device->physical_device->rad_info.chip_class >= GFX9) { + VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, + .stage = VK_SHADER_STAGE_COMPUTE_BIT, + .module = radv_shader_module_to_handle(&cs_3d), + .pName = "main", + .pSpecializationInfo = NULL, + }; + + VkComputePipelineCreateInfo vk_pipeline_info_3d = { + .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO, + .stage = pipeline_shader_stage_3d, + .flags = 0, + .layout = device->meta_state.itob.img_p_layout, + }; + + result = radv_CreateComputePipelines(radv_device_to_handle(device), + radv_pipeline_cache_to_handle(&device->meta_state.cache), + 1, &vk_pipeline_info_3d, NULL, + &device->meta_state.itob.pipeline_3d); + if (result != VK_SUCCESS) + goto fail; + ralloc_free(cs_3d.nir); + } ralloc_free(cs.nir); + return VK_SUCCESS; fail: ralloc_free(cs.nir); + ralloc_free(cs_3d.nir); return result; } static void radv_device_finish_meta_itob_state(struct radv_device *device) { - if (device->meta_state.itob.img_p_layout) { - radv_DestroyPipelineLayout(radv_device_to_handle(device), - device->meta_state.itob.img_p_layout, - &device->meta_state.alloc); - } - if (device->meta_state.itob.img_ds_layout) { - radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), - device->meta_state.itob.img_ds_layout, - &device->meta_state.alloc); - } - if (device->meta_state.itob.pipeline) { + struct radv_meta_state *state = &device->meta_state; + + radv_DestroyPipelineLayout(radv_device_to_handle(device), + state->itob.img_p_layout, &state->alloc); + radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), + state->itob.img_ds_layout, + &state->alloc); + radv_DestroyPipeline(radv_device_to_handle(device), + state->itob.pipeline, &state->alloc); + if (device->physical_device->rad_info.chip_class >= GFX9) radv_DestroyPipeline(radv_device_to_handle(device), - device->meta_state.itob.pipeline, - &device->meta_state.alloc); - } + state->itob.pipeline_3d, &state->alloc); } static nir_shader * -build_nir_btoi_compute_shader(struct radv_device *dev) +build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d) { nir_builder b; + enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D; const struct glsl_type *buf_type = glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_FLOAT); - const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D, + const struct glsl_type *img_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT); nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL); - b.shader->info.name = ralloc_strdup(b.shader, "meta_btoi_cs"); + b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_btoi_cs_3d" : "meta_btoi_cs"); b.shader->info.cs.local_size[0] = 16; b.shader->info.cs.local_size[1] = 16; b.shader->info.cs.local_size[2] = 1; @@ -269,16 +297,16 @@ build_nir_btoi_compute_shader(struct radv_device *dev) nir_intrinsic_instr *offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_set_base(offset, 0); - nir_intrinsic_set_range(offset, 12); + nir_intrinsic_set_range(offset, 16); offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); - offset->num_components = 2; - nir_ssa_dest_init(&offset->instr, &offset->dest, 2, 32, "offset"); + offset->num_components = is_3d ? 3 : 2; + nir_ssa_dest_init(&offset->instr, &offset->dest, is_3d ? 3 : 2, 32, "offset"); nir_builder_instr_insert(&b, &offset->instr); nir_intrinsic_instr *stride = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_set_base(stride, 0); - nir_intrinsic_set_range(stride, 12); - stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8)); + nir_intrinsic_set_range(stride, 16); + stride->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12)); stride->num_components = 1; nir_ssa_dest_init(&stride->instr, &stride->dest, 1, 32, "stride"); nir_builder_instr_insert(&b, &stride->instr); @@ -310,7 +338,7 @@ build_nir_btoi_compute_shader(struct radv_device *dev) nir_builder_instr_insert(&b, &tex->instr); nir_ssa_def *outval = &tex->dest.ssa; - nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store); + nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_var_store); store->src[0] = nir_src_for_ssa(img_coord); store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); store->src[2] = nir_src_for_ssa(outval); @@ -326,11 +354,10 @@ radv_device_init_meta_btoi_state(struct radv_device *device) { VkResult result; struct radv_shader_module cs = { .nir = NULL }; - - zero(device->meta_state.btoi); - - cs.nir = build_nir_btoi_compute_shader(device); - + struct radv_shader_module cs_3d = { .nir = NULL }; + cs.nir = build_nir_btoi_compute_shader(device, false); + if (device->physical_device->rad_info.chip_class >= GFX9) + cs_3d.nir = build_nir_btoi_compute_shader(device, true); /* * two descriptors one for the image being sampled * one for the buffer being written. @@ -370,7 +397,7 @@ radv_device_init_meta_btoi_state(struct radv_device *device) .setLayoutCount = 1, .pSetLayouts = &device->meta_state.btoi.img_ds_layout, .pushConstantRangeCount = 1, - .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 12}, + .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16}, }; result = radv_CreatePipelineLayout(radv_device_to_handle(device), @@ -404,9 +431,33 @@ radv_device_init_meta_btoi_state(struct radv_device *device) if (result != VK_SUCCESS) goto fail; + if (device->physical_device->rad_info.chip_class >= GFX9) { + VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, + .stage = VK_SHADER_STAGE_COMPUTE_BIT, + .module = radv_shader_module_to_handle(&cs_3d), + .pName = "main", + .pSpecializationInfo = NULL, + }; + + VkComputePipelineCreateInfo vk_pipeline_info_3d = { + .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO, + .stage = pipeline_shader_stage_3d, + .flags = 0, + .layout = device->meta_state.btoi.img_p_layout, + }; + + result = radv_CreateComputePipelines(radv_device_to_handle(device), + radv_pipeline_cache_to_handle(&device->meta_state.cache), + 1, &vk_pipeline_info_3d, NULL, + &device->meta_state.btoi.pipeline_3d); + ralloc_free(cs_3d.nir); + } ralloc_free(cs.nir); + return VK_SUCCESS; fail: + ralloc_free(cs_3d.nir); ralloc_free(cs.nir); return result; } @@ -414,37 +465,34 @@ fail: static void radv_device_finish_meta_btoi_state(struct radv_device *device) { - if (device->meta_state.btoi.img_p_layout) { - radv_DestroyPipelineLayout(radv_device_to_handle(device), - device->meta_state.btoi.img_p_layout, - &device->meta_state.alloc); - } - if (device->meta_state.btoi.img_ds_layout) { - radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), - device->meta_state.btoi.img_ds_layout, - &device->meta_state.alloc); - } - if (device->meta_state.btoi.pipeline) { - radv_DestroyPipeline(radv_device_to_handle(device), - device->meta_state.btoi.pipeline, - &device->meta_state.alloc); - } + struct radv_meta_state *state = &device->meta_state; + + radv_DestroyPipelineLayout(radv_device_to_handle(device), + state->btoi.img_p_layout, &state->alloc); + radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), + state->btoi.img_ds_layout, + &state->alloc); + radv_DestroyPipeline(radv_device_to_handle(device), + state->btoi.pipeline, &state->alloc); + radv_DestroyPipeline(radv_device_to_handle(device), + state->btoi.pipeline_3d, &state->alloc); } static nir_shader * -build_nir_itoi_compute_shader(struct radv_device *dev) +build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d) { nir_builder b; - const struct glsl_type *buf_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D, + enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D; + const struct glsl_type *buf_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT); - const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D, + const struct glsl_type *img_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT); nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL); - b.shader->info.name = ralloc_strdup(b.shader, "meta_itoi_cs"); + b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_itoi_cs_3d" : "meta_itoi_cs"); b.shader->info.cs.local_size[0] = 16; b.shader->info.cs.local_size[1] = 16; b.shader->info.cs.local_size[2] = 1; @@ -469,18 +517,18 @@ build_nir_itoi_compute_shader(struct radv_device *dev) nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_set_base(src_offset, 0); - nir_intrinsic_set_range(src_offset, 16); + nir_intrinsic_set_range(src_offset, 24); src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); - src_offset->num_components = 2; - nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset"); + src_offset->num_components = is_3d ? 3 : 2; + nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, is_3d ? 3 : 2, 32, "src_offset"); nir_builder_instr_insert(&b, &src_offset->instr); nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_set_base(dst_offset, 0); - nir_intrinsic_set_range(dst_offset, 16); - dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8)); - dst_offset->num_components = 2; - nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset"); + nir_intrinsic_set_range(dst_offset, 24); + dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 12)); + dst_offset->num_components = is_3d ? 3 : 2; + nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, is_3d ? 3 : 2, 32, "dst_offset"); nir_builder_instr_insert(&b, &dst_offset->instr); nir_ssa_def *src_coord = nir_iadd(&b, global_id, &src_offset->dest.ssa); @@ -488,15 +536,15 @@ build_nir_itoi_compute_shader(struct radv_device *dev) nir_ssa_def *dst_coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa); nir_tex_instr *tex = nir_tex_instr_create(b.shader, 2); - tex->sampler_dim = GLSL_SAMPLER_DIM_2D; + tex->sampler_dim = dim; tex->op = nir_texop_txf; tex->src[0].src_type = nir_tex_src_coord; - tex->src[0].src = nir_src_for_ssa(nir_channels(&b, src_coord, 3)); + tex->src[0].src = nir_src_for_ssa(nir_channels(&b, src_coord, is_3d ? 0x7 : 0x3)); tex->src[1].src_type = nir_tex_src_lod; tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0)); tex->dest_type = nir_type_float; tex->is_array = false; - tex->coord_components = 2; + tex->coord_components = is_3d ? 3 : 2; tex->texture = nir_deref_var_create(tex, input_img); tex->sampler = NULL; @@ -504,7 +552,7 @@ build_nir_itoi_compute_shader(struct radv_device *dev) nir_builder_instr_insert(&b, &tex->instr); nir_ssa_def *outval = &tex->dest.ssa; - nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store); + nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_var_store); store->src[0] = nir_src_for_ssa(dst_coord); store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); store->src[2] = nir_src_for_ssa(outval); @@ -520,11 +568,10 @@ radv_device_init_meta_itoi_state(struct radv_device *device) { VkResult result; struct radv_shader_module cs = { .nir = NULL }; - - zero(device->meta_state.itoi); - - cs.nir = build_nir_itoi_compute_shader(device); - + struct radv_shader_module cs_3d = { .nir = NULL }; + cs.nir = build_nir_itoi_compute_shader(device, false); + if (device->physical_device->rad_info.chip_class >= GFX9) + cs_3d.nir = build_nir_itoi_compute_shader(device, true); /* * two descriptors one for the image being sampled * one for the buffer being written. @@ -564,7 +611,7 @@ radv_device_init_meta_itoi_state(struct radv_device *device) .setLayoutCount = 1, .pSetLayouts = &device->meta_state.itoi.img_ds_layout, .pushConstantRangeCount = 1, - .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16}, + .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 24}, }; result = radv_CreatePipelineLayout(radv_device_to_handle(device), @@ -598,43 +645,66 @@ radv_device_init_meta_itoi_state(struct radv_device *device) if (result != VK_SUCCESS) goto fail; + if (device->physical_device->rad_info.chip_class >= GFX9) { + VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, +.stage = VK_SHADER_STAGE_COMPUTE_BIT, + .module = radv_shader_module_to_handle(&cs_3d), + .pName = "main", + .pSpecializationInfo = NULL, + }; + + VkComputePipelineCreateInfo vk_pipeline_info_3d = { + .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO, + .stage = pipeline_shader_stage_3d, + .flags = 0, + .layout = device->meta_state.itoi.img_p_layout, + }; + + result = radv_CreateComputePipelines(radv_device_to_handle(device), + radv_pipeline_cache_to_handle(&device->meta_state.cache), + 1, &vk_pipeline_info_3d, NULL, + &device->meta_state.itoi.pipeline_3d); + + ralloc_free(cs_3d.nir); + } ralloc_free(cs.nir); + return VK_SUCCESS; fail: ralloc_free(cs.nir); + ralloc_free(cs_3d.nir); return result; } static void radv_device_finish_meta_itoi_state(struct radv_device *device) { - if (device->meta_state.itoi.img_p_layout) { - radv_DestroyPipelineLayout(radv_device_to_handle(device), - device->meta_state.itoi.img_p_layout, - &device->meta_state.alloc); - } - if (device->meta_state.itoi.img_ds_layout) { - radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), - device->meta_state.itoi.img_ds_layout, - &device->meta_state.alloc); - } - if (device->meta_state.itoi.pipeline) { + struct radv_meta_state *state = &device->meta_state; + + radv_DestroyPipelineLayout(radv_device_to_handle(device), + state->itoi.img_p_layout, &state->alloc); + radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), + state->itoi.img_ds_layout, + &state->alloc); + radv_DestroyPipeline(radv_device_to_handle(device), + state->itoi.pipeline, &state->alloc); + if (device->physical_device->rad_info.chip_class >= GFX9) radv_DestroyPipeline(radv_device_to_handle(device), - device->meta_state.itoi.pipeline, - &device->meta_state.alloc); - } + state->itoi.pipeline_3d, &state->alloc); } static nir_shader * -build_nir_cleari_compute_shader(struct radv_device *dev) +build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d) { nir_builder b; - const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D, + enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D; + const struct glsl_type *img_type = glsl_sampler_type(dim, false, false, GLSL_TYPE_FLOAT); nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL); - b.shader->info.name = ralloc_strdup(b.shader, "meta_cleari_cs"); + b.shader->info.name = ralloc_strdup(b.shader, is_3d ? "meta_cleari_cs_3d" : "meta_cleari_cs"); b.shader->info.cs.local_size[0] = 16; b.shader->info.cs.local_size[1] = 16; b.shader->info.cs.local_size[2] = 1; @@ -655,13 +725,30 @@ build_nir_cleari_compute_shader(struct radv_device *dev) nir_intrinsic_instr *clear_val = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); nir_intrinsic_set_base(clear_val, 0); - nir_intrinsic_set_range(clear_val, 16); + nir_intrinsic_set_range(clear_val, 20); clear_val->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); clear_val->num_components = 4; nir_ssa_dest_init(&clear_val->instr, &clear_val->dest, 4, 32, "clear_value"); nir_builder_instr_insert(&b, &clear_val->instr); - nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store); + nir_intrinsic_instr *layer = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant); + nir_intrinsic_set_base(layer, 0); + nir_intrinsic_set_range(layer, 20); + layer->src[0] = nir_src_for_ssa(nir_imm_int(&b, 16)); + layer->num_components = 1; + nir_ssa_dest_init(&layer->instr, &layer->dest, 1, 32, "layer"); + nir_builder_instr_insert(&b, &layer->instr); + + nir_ssa_def *global_z = nir_iadd(&b, nir_channel(&b, global_id, 2), &layer->dest.ssa); + + nir_ssa_def *comps[4]; + comps[0] = nir_channel(&b, global_id, 0); + comps[1] = nir_channel(&b, global_id, 1); + comps[2] = global_z; + comps[3] = nir_imm_int(&b, 0); + global_id = nir_vec(&b, comps, 4); + + nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_var_store); store->src[0] = nir_src_for_ssa(global_id); store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); store->src[2] = nir_src_for_ssa(&clear_val->dest.ssa); @@ -676,10 +763,10 @@ radv_device_init_meta_cleari_state(struct radv_device *device) { VkResult result; struct radv_shader_module cs = { .nir = NULL }; - - zero(device->meta_state.cleari); - - cs.nir = build_nir_cleari_compute_shader(device); + struct radv_shader_module cs_3d = { .nir = NULL }; + cs.nir = build_nir_cleari_compute_shader(device, false); + if (device->physical_device->rad_info.chip_class >= GFX9) + cs_3d.nir = build_nir_cleari_compute_shader(device, true); /* * two descriptors one for the image being sampled @@ -713,7 +800,7 @@ radv_device_init_meta_cleari_state(struct radv_device *device) .setLayoutCount = 1, .pSetLayouts = &device->meta_state.cleari.img_ds_layout, .pushConstantRangeCount = 1, - .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16}, + .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 20}, }; result = radv_CreatePipelineLayout(radv_device_to_handle(device), @@ -747,31 +834,55 @@ radv_device_init_meta_cleari_state(struct radv_device *device) if (result != VK_SUCCESS) goto fail; + + if (device->physical_device->rad_info.chip_class >= GFX9) { + /* compute shader */ + VkPipelineShaderStageCreateInfo pipeline_shader_stage_3d = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO, + .stage = VK_SHADER_STAGE_COMPUTE_BIT, + .module = radv_shader_module_to_handle(&cs_3d), + .pName = "main", + .pSpecializationInfo = NULL, + }; + + VkComputePipelineCreateInfo vk_pipeline_info_3d = { + .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO, + .stage = pipeline_shader_stage_3d, + .flags = 0, + .layout = device->meta_state.cleari.img_p_layout, + }; + + result = radv_CreateComputePipelines(radv_device_to_handle(device), + radv_pipeline_cache_to_handle(&device->meta_state.cache), + 1, &vk_pipeline_info_3d, NULL, + &device->meta_state.cleari.pipeline_3d); + if (result != VK_SUCCESS) + goto fail; + + ralloc_free(cs_3d.nir); + } ralloc_free(cs.nir); return VK_SUCCESS; fail: ralloc_free(cs.nir); + ralloc_free(cs_3d.nir); return result; } static void radv_device_finish_meta_cleari_state(struct radv_device *device) { - if (device->meta_state.cleari.img_p_layout) { - radv_DestroyPipelineLayout(radv_device_to_handle(device), - device->meta_state.cleari.img_p_layout, - &device->meta_state.alloc); - } - if (device->meta_state.cleari.img_ds_layout) { - radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), - device->meta_state.cleari.img_ds_layout, - &device->meta_state.alloc); - } - if (device->meta_state.cleari.pipeline) { - radv_DestroyPipeline(radv_device_to_handle(device), - device->meta_state.cleari.pipeline, - &device->meta_state.alloc); - } + struct radv_meta_state *state = &device->meta_state; + + radv_DestroyPipelineLayout(radv_device_to_handle(device), + state->cleari.img_p_layout, &state->alloc); + radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), + state->cleari.img_ds_layout, + &state->alloc); + radv_DestroyPipeline(radv_device_to_handle(device), + state->cleari.pipeline, &state->alloc); + radv_DestroyPipeline(radv_device_to_handle(device), + state->cleari.pipeline_3d, &state->alloc); } void @@ -790,21 +901,23 @@ radv_device_init_meta_bufimage_state(struct radv_device *device) result = radv_device_init_meta_itob_state(device); if (result != VK_SUCCESS) - return result; + goto fail_itob; result = radv_device_init_meta_btoi_state(device); if (result != VK_SUCCESS) - goto fail_itob; + goto fail_btoi; result = radv_device_init_meta_itoi_state(device); if (result != VK_SUCCESS) - goto fail_btoi; + goto fail_itoi; result = radv_device_init_meta_cleari_state(device); if (result != VK_SUCCESS) - goto fail_itoi; + goto fail_cleari; return VK_SUCCESS; +fail_cleari: + radv_device_finish_meta_cleari_state(device); fail_itoi: radv_device_finish_meta_itoi_state(device); fail_btoi: @@ -814,59 +927,18 @@ fail_itob: return result; } -void -radv_meta_begin_itoi(struct radv_cmd_buffer *cmd_buffer, - struct radv_meta_saved_compute_state *save) -{ - radv_meta_save_compute(save, cmd_buffer, 16); -} - -void -radv_meta_end_itoi(struct radv_cmd_buffer *cmd_buffer, - struct radv_meta_saved_compute_state *save) -{ - radv_meta_restore_compute(save, cmd_buffer, 16); -} - -void -radv_meta_begin_bufimage(struct radv_cmd_buffer *cmd_buffer, - struct radv_meta_saved_compute_state *save) -{ - radv_meta_save_compute(save, cmd_buffer, 12); -} - -void -radv_meta_end_bufimage(struct radv_cmd_buffer *cmd_buffer, - struct radv_meta_saved_compute_state *save) -{ - radv_meta_restore_compute(save, cmd_buffer, 12); -} - -void -radv_meta_begin_cleari(struct radv_cmd_buffer *cmd_buffer, - struct radv_meta_saved_compute_state *save) -{ - radv_meta_save_compute(save, cmd_buffer, 16); -} - -void -radv_meta_end_cleari(struct radv_cmd_buffer *cmd_buffer, - struct radv_meta_saved_compute_state *save) -{ - radv_meta_restore_compute(save, cmd_buffer, 16); -} - static void create_iview(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *surf, struct radv_image_view *iview) { - + VkImageViewType view_type = cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 ? VK_IMAGE_VIEW_TYPE_2D : + radv_meta_get_view_type(surf->image); radv_image_view_init(iview, cmd_buffer->device, &(VkImageViewCreateInfo) { .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO, .image = radv_image_to_handle(surf->image), - .viewType = VK_IMAGE_VIEW_TYPE_2D, + .viewType = view_type, .format = surf->format, .subresourceRange = { .aspectMask = surf->aspect_mask, @@ -893,18 +965,14 @@ create_bview(struct radv_cmd_buffer *cmd_buffer, .format = format, .offset = offset, .range = VK_WHOLE_SIZE, - }, cmd_buffer); + }); } -struct itob_temps { - struct radv_image_view src_iview; - struct radv_buffer_view dst_bview; -}; - static void itob_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, - struct itob_temps *tmp) + struct radv_image_view *src, + struct radv_buffer_view *dst) { struct radv_device *device = cmd_buffer->device; @@ -923,7 +991,7 @@ itob_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, .pImageInfo = (VkDescriptorImageInfo[]) { { .sampler = VK_NULL_HANDLE, - .imageView = radv_image_view_to_handle(&tmp->src_iview), + .imageView = radv_image_view_to_handle(src), .imageLayout = VK_IMAGE_LAYOUT_GENERAL, }, } @@ -934,23 +1002,11 @@ itob_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, .dstArrayElement = 0, .descriptorCount = 1, .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER, - .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(&tmp->dst_bview) }, + .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(dst) }, } }); } -static void -itob_bind_pipeline(struct radv_cmd_buffer *cmd_buffer) -{ - VkPipeline pipeline = - cmd_buffer->device->meta_state.itob.pipeline; - - if (cmd_buffer->state.compute_pipeline != radv_pipeline_from_handle(pipeline)) { - radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), - VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); - } -} - void radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src, @@ -958,38 +1014,42 @@ radv_meta_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, unsigned num_rects, struct radv_meta_blit2d_rect *rects) { + VkPipeline pipeline = cmd_buffer->device->meta_state.itob.pipeline; struct radv_device *device = cmd_buffer->device; - struct itob_temps temps; + struct radv_image_view src_view; + struct radv_buffer_view dst_view; + + create_iview(cmd_buffer, src, &src_view); + create_bview(cmd_buffer, dst->buffer, dst->offset, dst->format, &dst_view); + itob_bind_descriptors(cmd_buffer, &src_view, &dst_view); - create_iview(cmd_buffer, src, &temps.src_iview); - create_bview(cmd_buffer, dst->buffer, dst->offset, dst->format, &temps.dst_bview); - itob_bind_descriptors(cmd_buffer, &temps); + if (device->physical_device->rad_info.chip_class >= GFX9 && + src->image->type == VK_IMAGE_TYPE_3D) + pipeline = cmd_buffer->device->meta_state.itob.pipeline_3d; - itob_bind_pipeline(cmd_buffer); + radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), + VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); for (unsigned r = 0; r < num_rects; ++r) { - unsigned push_constants[3] = { + unsigned push_constants[4] = { rects[r].src_x, rects[r].src_y, + src->layer, dst->pitch }; radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itob.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 12, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); } } -struct btoi_temps { - struct radv_buffer_view src_bview; - struct radv_image_view dst_iview; -}; - static void btoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, - struct btoi_temps *tmp) + struct radv_buffer_view *src, + struct radv_image_view *dst) { struct radv_device *device = cmd_buffer->device; @@ -1005,7 +1065,7 @@ btoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, .dstArrayElement = 0, .descriptorCount = 1, .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER, - .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(&tmp->src_bview) }, + .pTexelBufferView = (VkBufferView[]) { radv_buffer_view_to_handle(src) }, }, { .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET, @@ -1016,7 +1076,7 @@ btoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, .pImageInfo = (VkDescriptorImageInfo[]) { { .sampler = VK_NULL_HANDLE, - .imageView = radv_image_view_to_handle(&tmp->dst_iview), + .imageView = radv_image_view_to_handle(dst), .imageLayout = VK_IMAGE_LAYOUT_GENERAL, }, } @@ -1024,18 +1084,6 @@ btoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, }); } -static void -btoi_bind_pipeline(struct radv_cmd_buffer *cmd_buffer) -{ - VkPipeline pipeline = - cmd_buffer->device->meta_state.btoi.pipeline; - - if (cmd_buffer->state.compute_pipeline != radv_pipeline_from_handle(pipeline)) { - radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), - VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); - } -} - void radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_buffer *src, @@ -1043,38 +1091,41 @@ radv_meta_buffer_to_image_cs(struct radv_cmd_buffer *cmd_buffer, unsigned num_rects, struct radv_meta_blit2d_rect *rects) { + VkPipeline pipeline = cmd_buffer->device->meta_state.btoi.pipeline; struct radv_device *device = cmd_buffer->device; - struct btoi_temps temps; + struct radv_buffer_view src_view; + struct radv_image_view dst_view; - create_bview(cmd_buffer, src->buffer, src->offset, src->format, &temps.src_bview); - create_iview(cmd_buffer, dst, &temps.dst_iview); - btoi_bind_descriptors(cmd_buffer, &temps); + create_bview(cmd_buffer, src->buffer, src->offset, src->format, &src_view); + create_iview(cmd_buffer, dst, &dst_view); + btoi_bind_descriptors(cmd_buffer, &src_view, &dst_view); - btoi_bind_pipeline(cmd_buffer); + if (device->physical_device->rad_info.chip_class >= GFX9 && + dst->image->type == VK_IMAGE_TYPE_3D) + pipeline = cmd_buffer->device->meta_state.btoi.pipeline_3d; + radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), + VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); for (unsigned r = 0; r < num_rects; ++r) { - unsigned push_constants[3] = { + unsigned push_constants[4] = { rects[r].dst_x, rects[r].dst_y, - src->pitch + dst->layer, + src->pitch, }; radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.btoi.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 12, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, push_constants); radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); } } -struct itoi_temps { - struct radv_image_view src_iview; - struct radv_image_view dst_iview; -}; - static void itoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, - struct itoi_temps *tmp) + struct radv_image_view *src, + struct radv_image_view *dst) { struct radv_device *device = cmd_buffer->device; @@ -1093,7 +1144,7 @@ itoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, .pImageInfo = (VkDescriptorImageInfo[]) { { .sampler = VK_NULL_HANDLE, - .imageView = radv_image_view_to_handle(&tmp->src_iview), + .imageView = radv_image_view_to_handle(src), .imageLayout = VK_IMAGE_LAYOUT_GENERAL, }, } @@ -1107,7 +1158,7 @@ itoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, .pImageInfo = (VkDescriptorImageInfo[]) { { .sampler = VK_NULL_HANDLE, - .imageView = radv_image_view_to_handle(&tmp->dst_iview), + .imageView = radv_image_view_to_handle(dst), .imageLayout = VK_IMAGE_LAYOUT_GENERAL, }, } @@ -1115,18 +1166,6 @@ itoi_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, }); } -static void -itoi_bind_pipeline(struct radv_cmd_buffer *cmd_buffer) -{ - VkPipeline pipeline = - cmd_buffer->device->meta_state.itoi.pipeline; - - if (cmd_buffer->state.compute_pipeline != radv_pipeline_from_handle(pipeline)) { - radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), - VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); - } -} - void radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *src, @@ -1134,26 +1173,33 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer, unsigned num_rects, struct radv_meta_blit2d_rect *rects) { + VkPipeline pipeline = cmd_buffer->device->meta_state.itoi.pipeline; struct radv_device *device = cmd_buffer->device; - struct itoi_temps temps; + struct radv_image_view src_view, dst_view; - create_iview(cmd_buffer, src, &temps.src_iview); - create_iview(cmd_buffer, dst, &temps.dst_iview); + create_iview(cmd_buffer, src, &src_view); + create_iview(cmd_buffer, dst, &dst_view); - itoi_bind_descriptors(cmd_buffer, &temps); + itoi_bind_descriptors(cmd_buffer, &src_view, &dst_view); - itoi_bind_pipeline(cmd_buffer); + if (device->physical_device->rad_info.chip_class >= GFX9 && + src->image->type == VK_IMAGE_TYPE_3D) + pipeline = cmd_buffer->device->meta_state.itoi.pipeline_3d; + radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), + VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); for (unsigned r = 0; r < num_rects; ++r) { - unsigned push_constants[4] = { + unsigned push_constants[6] = { rects[r].src_x, rects[r].src_y, + src->layer, rects[r].dst_x, rects[r].dst_y, + dst->layer, }; radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.itoi.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 24, push_constants); radv_unaligned_dispatch(cmd_buffer, rects[r].width, rects[r].height, 1); @@ -1189,41 +1235,36 @@ cleari_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, }); } -static void -cleari_bind_pipeline(struct radv_cmd_buffer *cmd_buffer) -{ - VkPipeline pipeline = - cmd_buffer->device->meta_state.cleari.pipeline; - - if (cmd_buffer->state.compute_pipeline != radv_pipeline_from_handle(pipeline)) { - radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), - VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); - } -} - void radv_meta_clear_image_cs(struct radv_cmd_buffer *cmd_buffer, struct radv_meta_blit2d_surf *dst, const VkClearColorValue *clear_color) { + VkPipeline pipeline = cmd_buffer->device->meta_state.cleari.pipeline; struct radv_device *device = cmd_buffer->device; struct radv_image_view dst_iview; create_iview(cmd_buffer, dst, &dst_iview); cleari_bind_descriptors(cmd_buffer, &dst_iview); - cleari_bind_pipeline(cmd_buffer); + if (device->physical_device->rad_info.chip_class >= GFX9 && + dst->image->type == VK_IMAGE_TYPE_3D) + pipeline = cmd_buffer->device->meta_state.cleari.pipeline_3d; + + radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), + VK_PIPELINE_BIND_POINT_COMPUTE, pipeline); - unsigned push_constants[4] = { + unsigned push_constants[5] = { clear_color->uint32[0], clear_color->uint32[1], clear_color->uint32[2], clear_color->uint32[3], + dst->layer, }; radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), device->meta_state.cleari.img_p_layout, - VK_SHADER_STAGE_COMPUTE_BIT, 0, 16, + VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, push_constants); radv_unaligned_dispatch(cmd_buffer, dst->image->info.width, dst->image->info.height, 1);