X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_meta_clear.c;h=bfeda8e3fa9369391b638f2da761f786b6959e5b;hb=f18fc34c4d56d6e7d511002b39a257e18d8b3af3;hp=8cacea034ece2bd1e07ce07c168c18e5d7a7414f;hpb=7971697efe77545229184fd70188b9415ee0653d;p=mesa.git diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 8cacea034ec..bfeda8e3fa9 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -235,7 +235,27 @@ create_color_renderpass(struct radv_device *device, .preserveAttachmentCount = 0, .pPreserveAttachments = NULL, }, - .dependencyCount = 0, + .dependencyCount = 2, + .pDependencies = (VkSubpassDependency[]) { + { + .srcSubpass = VK_SUBPASS_EXTERNAL, + .dstSubpass = 0, + .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, + .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, + .srcAccessMask = 0, + .dstAccessMask = 0, + .dependencyFlags = 0 + }, + { + .srcSubpass = 0, + .dstSubpass = VK_SUBPASS_EXTERNAL, + .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, + .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, + .srcAccessMask = 0, + .dstAccessMask = 0, + .dependencyFlags = 0 + } + }, }, &device->meta_state.alloc, pass); mtx_unlock(&device->meta_state.mtx); return result; @@ -344,6 +364,16 @@ radv_device_finish_meta_clear_state(struct radv_device *device) radv_DestroyPipeline(radv_device_to_handle(device), state->clear[i].depthstencil_pipeline[j], &state->alloc); + + radv_DestroyPipeline(radv_device_to_handle(device), + state->clear[i].depth_only_unrestricted_pipeline[j], + &state->alloc); + radv_DestroyPipeline(radv_device_to_handle(device), + state->clear[i].stencil_only_unrestricted_pipeline[j], + &state->alloc); + radv_DestroyPipeline(radv_device_to_handle(device), + state->clear[i].depthstencil_unrestricted_pipeline[j], + &state->alloc); } radv_DestroyRenderPass(radv_device_to_handle(device), state->clear[i].depthstencil_rp, @@ -355,6 +385,9 @@ radv_device_finish_meta_clear_state(struct radv_device *device) radv_DestroyPipelineLayout(radv_device_to_handle(device), state->clear_depth_p_layout, &state->alloc); + radv_DestroyPipelineLayout(radv_device_to_handle(device), + state->clear_depth_unrestricted_p_layout, + &state->alloc); finish_meta_clear_htile_mask_state(device); } @@ -367,10 +400,10 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer, { struct radv_device *device = cmd_buffer->device; const struct radv_subpass *subpass = cmd_buffer->state.subpass; - const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer; const uint32_t subpass_att = clear_att->colorAttachment; const uint32_t pass_att = subpass->color_attachments[subpass_att].attachment; - const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL; + const struct radv_image_view *iview = cmd_buffer->state.attachments ? + cmd_buffer->state.attachments[pass_att].iview : NULL; uint32_t samples, samples_log2; VkFormat format; unsigned fs_key; @@ -470,15 +503,21 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer, static void -build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs) +build_depthstencil_shader(struct nir_shader **out_vs, + struct nir_shader **out_fs, + bool unrestricted) { nir_builder vs_b, fs_b; nir_builder_init_simple_shader(&vs_b, NULL, MESA_SHADER_VERTEX, NULL); nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL); - vs_b.shader->info.name = ralloc_strdup(vs_b.shader, "meta_clear_depthstencil_vs"); - fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "meta_clear_depthstencil_fs"); + vs_b.shader->info.name = ralloc_strdup(vs_b.shader, + unrestricted ? "meta_clear_depthstencil_unrestricted_vs" + : "meta_clear_depthstencil_vs"); + fs_b.shader->info.name = ralloc_strdup(fs_b.shader, + unrestricted ? "meta_clear_depthstencil_unrestricted_fs" + : "meta_clear_depthstencil_fs"); const struct glsl_type *position_out_type = glsl_vec4_type(); nir_variable *vs_out_pos = @@ -486,15 +525,36 @@ build_depthstencil_shader(struct nir_shader **out_vs, struct nir_shader **out_fs "gl_Position"); vs_out_pos->data.location = VARYING_SLOT_POS; - nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant); - nir_intrinsic_set_base(in_color_load, 0); - nir_intrinsic_set_range(in_color_load, 4); - in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0)); - in_color_load->num_components = 1; - nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value"); - nir_builder_instr_insert(&vs_b, &in_color_load->instr); + nir_ssa_def *z; + if (unrestricted) { + nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(fs_b.shader, nir_intrinsic_load_push_constant); + nir_intrinsic_set_base(in_color_load, 0); + nir_intrinsic_set_range(in_color_load, 4); + in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&fs_b, 0)); + in_color_load->num_components = 1; + nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value"); + nir_builder_instr_insert(&fs_b, &in_color_load->instr); + + nir_variable *fs_out_depth = + nir_variable_create(fs_b.shader, nir_var_shader_out, + glsl_int_type(), "f_depth"); + fs_out_depth->data.location = FRAG_RESULT_DEPTH; + nir_store_var(&fs_b, fs_out_depth, &in_color_load->dest.ssa, 0x1); + + z = nir_imm_float(&vs_b, 0.0); + } else { + nir_intrinsic_instr *in_color_load = nir_intrinsic_instr_create(vs_b.shader, nir_intrinsic_load_push_constant); + nir_intrinsic_set_base(in_color_load, 0); + nir_intrinsic_set_range(in_color_load, 4); + in_color_load->src[0] = nir_src_for_ssa(nir_imm_int(&vs_b, 0)); + in_color_load->num_components = 1; + nir_ssa_dest_init(&in_color_load->instr, &in_color_load->dest, 1, 32, "depth value"); + nir_builder_instr_insert(&vs_b, &in_color_load->instr); + + z = &in_color_load->dest.ssa; + } - nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, &in_color_load->dest.ssa); + nir_ssa_def *outvec = radv_meta_gen_rect_vertices_comp2(&vs_b, z); nir_store_var(&vs_b, vs_out_pos, outvec, 0xf); const struct glsl_type *layer_type = glsl_int_type(); @@ -550,7 +610,27 @@ create_depthstencil_renderpass(struct radv_device *device, .preserveAttachmentCount = 0, .pPreserveAttachments = NULL, }, - .dependencyCount = 0, + .dependencyCount = 2, + .pDependencies = (VkSubpassDependency[]) { + { + .srcSubpass = VK_SUBPASS_EXTERNAL, + .dstSubpass = 0, + .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, + .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, + .srcAccessMask = 0, + .dstAccessMask = 0, + .dependencyFlags = 0 + }, + { + .srcSubpass = 0, + .dstSubpass = VK_SUBPASS_EXTERNAL, + .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, + .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, + .srcAccessMask = 0, + .dstAccessMask = 0, + .dependencyFlags = 0 + } + } }, &device->meta_state.alloc, render_pass); mtx_unlock(&device->meta_state.mtx); return result; @@ -561,6 +641,7 @@ create_depthstencil_pipeline(struct radv_device *device, VkImageAspectFlags aspects, uint32_t samples, int index, + bool unrestricted, VkPipeline *pipeline, VkRenderPass render_pass) { @@ -573,7 +654,7 @@ create_depthstencil_pipeline(struct radv_device *device, return VK_SUCCESS; } - build_depthstencil_shader(&vs_nir, &fs_nir); + build_depthstencil_shader(&vs_nir, &fs_nir, unrestricted); const VkPipelineVertexInputStateCreateInfo vi_state = { .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO, @@ -583,11 +664,11 @@ create_depthstencil_pipeline(struct radv_device *device, const VkPipelineDepthStencilStateCreateInfo ds_state = { .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO, - .depthTestEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT), + .depthTestEnable = !!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT), .depthCompareOp = VK_COMPARE_OP_ALWAYS, - .depthWriteEnable = (aspects & VK_IMAGE_ASPECT_DEPTH_BIT), + .depthWriteEnable = !!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT), .depthBoundsTestEnable = false, - .stencilTestEnable = (aspects & VK_IMAGE_ASPECT_STENCIL_BIT), + .stencilTestEnable = !!(aspects & VK_IMAGE_ASPECT_STENCIL_BIT), .front = { .passOp = VK_STENCIL_OP_REPLACE, .compareOp = VK_COMPARE_OP_ALWAYS, @@ -629,6 +710,7 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer, const struct radv_image_view *iview, VkImageAspectFlags aspects, VkImageLayout layout, + bool in_render_loop, const VkClearRect *clear_rect, VkClearDepthStencilValue clear_value) { @@ -651,7 +733,7 @@ static bool depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer, iview->base_mip == 0 && iview->base_layer == 0 && iview->layer_count == iview->image->info.array_size && - radv_layout_is_htile_compressed(iview->image, layout, queue_mask) && + radv_layout_is_htile_compressed(iview->image, layout, in_render_loop, queue_mask) && radv_image_extent_compare(iview->image, &iview->extent)) return true; return false; @@ -664,10 +746,13 @@ pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer, int samples_log2, VkImageAspectFlags aspects, VkImageLayout layout, + bool in_render_loop, const VkClearRect *clear_rect, VkClearDepthStencilValue clear_value) { - bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, clear_rect, clear_value); + bool fast = depth_view_can_fast_clear(cmd_buffer, iview, aspects, layout, + in_render_loop, clear_rect, clear_value); + bool unrestricted = cmd_buffer->device->enabled_extensions.EXT_depth_range_unrestricted; int index = DEPTH_CLEAR_SLOW; VkPipeline *pipeline; @@ -679,13 +764,19 @@ pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer, switch (aspects) { case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT: - pipeline = &meta_state->clear[samples_log2].depthstencil_pipeline[index]; + pipeline = unrestricted ? + &meta_state->clear[samples_log2].depthstencil_unrestricted_pipeline[index] : + &meta_state->clear[samples_log2].depthstencil_pipeline[index]; break; case VK_IMAGE_ASPECT_DEPTH_BIT: - pipeline = &meta_state->clear[samples_log2].depth_only_pipeline[index]; + pipeline = unrestricted ? + &meta_state->clear[samples_log2].depth_only_unrestricted_pipeline[index] : + &meta_state->clear[samples_log2].depth_only_pipeline[index]; break; case VK_IMAGE_ASPECT_STENCIL_BIT: - pipeline = &meta_state->clear[samples_log2].stencil_only_pipeline[index]; + pipeline = unrestricted ? + &meta_state->clear[samples_log2].stencil_only_unrestricted_pipeline[index] : + &meta_state->clear[samples_log2].stencil_only_pipeline[index]; break; default: unreachable("expected depth or stencil aspect"); @@ -701,7 +792,7 @@ pick_depthstencil_pipeline(struct radv_cmd_buffer *cmd_buffer, } if (*pipeline == VK_NULL_HANDLE) { - VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index, + VkResult ret = create_depthstencil_pipeline(cmd_buffer->device, aspects, 1u << samples_log2, index, unrestricted, pipeline, cmd_buffer->device->meta_state.clear[samples_log2].depthstencil_rp); if (ret != VK_SUCCESS) { cmd_buffer->record_result = ret; @@ -715,16 +806,17 @@ static void emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachment *clear_att, const VkClearRect *clear_rect, + struct radv_subpass_attachment *ds_att, uint32_t view_mask) { struct radv_device *device = cmd_buffer->device; struct radv_meta_state *meta_state = &device->meta_state; const struct radv_subpass *subpass = cmd_buffer->state.subpass; - const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer; - const uint32_t pass_att = subpass->depth_stencil_attachment->attachment; + const uint32_t pass_att = ds_att->attachment; VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil; VkImageAspectFlags aspects = clear_att->aspectMask; - const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL; + const struct radv_image_view *iview = cmd_buffer->state.attachments ? + cmd_buffer->state.attachments[pass_att].iview : NULL; uint32_t samples, samples_log2; VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer); @@ -745,10 +837,17 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, if (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) clear_value.depth = 1.0f; - radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), - device->meta_state.clear_depth_p_layout, - VK_SHADER_STAGE_VERTEX_BIT, 0, 4, - &clear_value.depth); + if (cmd_buffer->device->enabled_extensions.EXT_depth_range_unrestricted) { + radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + device->meta_state.clear_depth_unrestricted_p_layout, + VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4, + &clear_value.depth); + } else { + radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), + device->meta_state.clear_depth_p_layout, + VK_SHADER_STAGE_VERTEX_BIT, 0, 4, + &clear_value.depth); + } uint32_t prev_reference = cmd_buffer->state.dynamic.stencil_reference.front; if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) { @@ -761,19 +860,28 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, iview, samples_log2, aspects, - subpass->depth_stencil_attachment->layout, + ds_att->layout, + ds_att->in_render_loop, clear_rect, clear_value); if (!pipeline) return; + struct radv_subpass clear_subpass = { + .color_count = 0, + .color_attachments = NULL, + .depth_stencil_attachment = ds_att, + }; + + radv_cmd_buffer_set_subpass(cmd_buffer, &clear_subpass); + radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline); if (depth_view_can_fast_clear(cmd_buffer, iview, aspects, - subpass->depth_stencil_attachment->layout, + ds_att->layout, ds_att->in_render_loop, clear_rect, clear_value)) - radv_update_ds_clear_metadata(cmd_buffer, iview->image, + radv_update_ds_clear_metadata(cmd_buffer, iview, clear_value, aspects); radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) { @@ -799,6 +907,8 @@ emit_depthstencil_clear(struct radv_cmd_buffer *cmd_buffer, radv_CmdSetStencilReference(cmd_buffer_h, VK_STENCIL_FACE_FRONT_BIT, prev_reference); } + + radv_cmd_buffer_set_subpass(cmd_buffer, subpass); } static uint32_t @@ -860,8 +970,8 @@ clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, radv_meta_restore(&saved_state, cmd_buffer); return RADV_CMD_FLAG_CS_PARTIAL_FLUSH | - RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2; + RADV_CMD_FLAG_INV_VCACHE | + RADV_CMD_FLAG_WB_L2; } static uint32_t @@ -971,6 +1081,7 @@ static bool radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_image_view *iview, VkImageLayout image_layout, + bool in_render_loop, VkImageAspectFlags aspects, const VkClearRect *clear_rect, const VkClearDepthStencilValue clear_value, @@ -979,7 +1090,10 @@ radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview)) return false; - if (!radv_layout_is_htile_compressed(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index))) + if (!radv_layout_is_htile_compressed(iview->image, image_layout, in_render_loop, + radv_image_queue_family_mask(iview->image, + cmd_buffer->queue_family_index, + cmd_buffer->queue_family_index))) return false; if (clear_rect->rect.offset.x || clear_rect->rect.offset.y || @@ -995,12 +1109,6 @@ radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, if (!view_mask && clear_rect->layerCount != iview->image->info.array_size) return false; - if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 && - (!(aspects & VK_IMAGE_ASPECT_DEPTH_BIT) || - ((vk_format_aspects(iview->image->vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT) && - !(aspects & VK_IMAGE_ASPECT_STENCIL_BIT)))) - return false; - if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && !radv_is_fast_clear_depth_allowed(clear_value)) || ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && @@ -1020,10 +1128,8 @@ radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil; VkImageAspectFlags aspects = clear_att->aspectMask; uint32_t clear_word, flush_bits; - uint32_t htile_mask; clear_word = radv_get_htile_fast_clear_value(iview->image, clear_value); - htile_mask = radv_get_htile_mask(iview->image, aspects); if (pre_flush) { cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_DB | @@ -1031,21 +1137,27 @@ radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, *pre_flush |= cmd_buffer->state.flush_bits; } - if (htile_mask == UINT_MAX) { - /* Clear the whole HTILE buffer. */ - flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo, - iview->image->offset + iview->image->htile_offset, - iview->image->planes[0].surface.htile_size, clear_word); - } else { - /* Only clear depth or stencil bytes in the HTILE buffer. */ - assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9); - flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo, - iview->image->offset + iview->image->htile_offset, - iview->image->planes[0].surface.htile_size, clear_word, - htile_mask); + struct VkImageSubresourceRange range = { + .aspectMask = aspects, + .baseMipLevel = 0, + .levelCount = VK_REMAINING_MIP_LEVELS, + .baseArrayLayer = 0, + .layerCount = VK_REMAINING_ARRAY_LAYERS, + }; + + flush_bits = radv_clear_htile(cmd_buffer, iview->image, &range, clear_word); + + if (iview->image->planes[0].surface.has_stencil && + !(aspects == (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT))) { + /* Synchronize after performing a depth-only or a stencil-only + * fast clear because the driver uses an optimized path which + * performs a read-modify-write operation, and the two separate + * aspects might use the same HTILE memory. + */ + cmd_buffer->state.flush_bits |= flush_bits; } - radv_update_ds_clear_metadata(cmd_buffer, iview->image, clear_value, aspects); + radv_update_ds_clear_metadata(cmd_buffer, iview, clear_value, aspects); if (post_flush) { *post_flush |= flush_bits; } @@ -1063,7 +1175,7 @@ build_clear_htile_mask_shader() b.shader->info.cs.local_size[2] = 1; nir_ssa_def *invoc_id = nir_load_local_invocation_id(&b); - nir_ssa_def *wg_id = nir_load_work_group_id(&b); + nir_ssa_def *wg_id = nir_load_work_group_id(&b, 32); nir_ssa_def *block_size = nir_imm_ivec4(&b, b.shader->info.cs.local_size[0], b.shader->info.cs.local_size[1], @@ -1101,6 +1213,7 @@ build_clear_htile_mask_shader() load->src[1] = nir_src_for_ssa(offset); nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL); load->num_components = 4; + nir_intrinsic_set_align(load, 16, 0); nir_builder_instr_insert(&b, &load->instr); /* data = (data & ~htile_mask) | (htile_value & htile_mask) */ @@ -1116,6 +1229,7 @@ build_clear_htile_mask_shader() store->src[2] = nir_src_for_ssa(offset); nir_intrinsic_set_write_mask(store, 0xf); nir_intrinsic_set_access(store, ACCESS_NON_READABLE); + nir_intrinsic_set_align(store, 16, 0); store->num_components = 4; nir_builder_instr_insert(&b, &store->instr); @@ -1229,6 +1343,20 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand) if (res != VK_SUCCESS) goto fail; + VkPipelineLayoutCreateInfo pl_depth_unrestricted_create_info = { + .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO, + .setLayoutCount = 0, + .pushConstantRangeCount = 1, + .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_FRAGMENT_BIT, 0, 4}, + }; + + res = radv_CreatePipelineLayout(radv_device_to_handle(device), + &pl_depth_unrestricted_create_info, + &device->meta_state.alloc, + &device->meta_state.clear_depth_unrestricted_p_layout); + if (res != VK_SUCCESS) + goto fail; + res = init_meta_clear_htile_mask_state(device); if (res != VK_SUCCESS) goto fail; @@ -1266,6 +1394,7 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand) VK_IMAGE_ASPECT_DEPTH_BIT, samples, j, + false, &state->clear[i].depth_only_pipeline[j], state->clear[i].depthstencil_rp); if (res != VK_SUCCESS) @@ -1275,6 +1404,7 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand) VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, + false, &state->clear[i].stencil_only_pipeline[j], state->clear[i].depthstencil_rp); if (res != VK_SUCCESS) @@ -1285,10 +1415,42 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand) VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, + false, &state->clear[i].depthstencil_pipeline[j], state->clear[i].depthstencil_rp); if (res != VK_SUCCESS) goto fail; + + res = create_depthstencil_pipeline(device, + VK_IMAGE_ASPECT_DEPTH_BIT, + samples, + j, + true, + &state->clear[i].depth_only_unrestricted_pipeline[j], + state->clear[i].depthstencil_rp); + if (res != VK_SUCCESS) + goto fail; + + res = create_depthstencil_pipeline(device, + VK_IMAGE_ASPECT_STENCIL_BIT, + samples, + j, + true, + &state->clear[i].stencil_only_unrestricted_pipeline[j], + state->clear[i].depthstencil_rp); + if (res != VK_SUCCESS) + goto fail; + + res = create_depthstencil_pipeline(device, + VK_IMAGE_ASPECT_DEPTH_BIT | + VK_IMAGE_ASPECT_STENCIL_BIT, + samples, + j, + true, + &state->clear[i].depthstencil_unrestricted_pipeline[j], + state->clear[i].depthstencil_rp); + if (res != VK_SUCCESS) + goto fail; } } return VK_SUCCESS; @@ -1316,21 +1478,52 @@ radv_get_cmask_fast_clear_value(const struct radv_image *image) uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, uint32_t value) + struct radv_image *image, + const VkImageSubresourceRange *range, uint32_t value) { - return radv_fill_buffer(cmd_buffer, image->bo, - image->offset + image->cmask.offset, - image->cmask.size, value); + uint64_t offset = image->offset + image->planes[0].surface.cmask_offset; + uint64_t size; + + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + /* TODO: clear layers. */ + size = image->planes[0].surface.cmask_size; + } else { + unsigned cmask_slice_size = + image->planes[0].surface.cmask_slice_size; + + offset += cmask_slice_size * range->baseArrayLayer; + size = cmask_slice_size * radv_get_layerCount(image, range); + } + + return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value); } uint32_t radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, - struct radv_image *image, uint32_t value) + struct radv_image *image, + const VkImageSubresourceRange *range, uint32_t value) { - return radv_fill_buffer(cmd_buffer, image->bo, - image->offset + image->fmask.offset, - image->fmask.size, value); + uint64_t offset = image->offset + image->planes[0].surface.fmask_offset; + uint64_t size; + + /* MSAA images do not support mipmap levels. */ + assert(range->baseMipLevel == 0 && + radv_get_levelCount(image, range) == 1); + + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + /* TODO: clear layers. */ + size = image->planes[0].surface.fmask_size; + } else { + unsigned fmask_slice_size = + image->planes[0].surface.u.legacy.fmask.slice_size; + + + offset += fmask_slice_size * range->baseArrayLayer; + size = fmask_slice_size * radv_get_layerCount(image, range); + } + + return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value); } uint32_t @@ -1338,27 +1531,79 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, const VkImageSubresourceRange *range, uint32_t value) { + uint32_t level_count = radv_get_levelCount(image, range); + uint32_t flush_bits = 0; + /* Mark the image as being compressed. */ radv_update_dcc_metadata(cmd_buffer, image, range, true); - return radv_fill_buffer(cmd_buffer, image->bo, - image->offset + image->dcc_offset, - image->planes[0].surface.dcc_size, value); + for (uint32_t l = 0; l < level_count; l++) { + uint64_t offset = image->offset + image->planes[0].surface.dcc_offset; + uint32_t level = range->baseMipLevel + l; + uint64_t size; + + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + /* Mipmap levels aren't implemented. */ + assert(level == 0); + size = image->planes[0].surface.dcc_size; + } else { + const struct legacy_surf_level *surf_level = + &image->planes[0].surface.u.legacy.level[level]; + + /* If dcc_fast_clear_size is 0 (which might happens for + * mipmaps) the fill buffer operation below is a no-op. + * This can only happen during initialization as the + * fast clear path fallbacks to slow clears if one + * level can't be fast cleared. + */ + offset += surf_level->dcc_offset + + surf_level->dcc_slice_fast_clear_size * range->baseArrayLayer; + size = surf_level->dcc_slice_fast_clear_size * radv_get_layerCount(image, range); + } + + flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset, + size, value); + } + + return flush_bits; } uint32_t -radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, - const VkImageSubresourceRange *range, uint32_t value) +radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, + const struct radv_image *image, + const VkImageSubresourceRange *range, + uint32_t value) { unsigned layer_count = radv_get_layerCount(image, range); uint64_t size = image->planes[0].surface.htile_slice_size * layer_count; - uint64_t offset = image->offset + image->htile_offset + + uint64_t offset = image->offset + image->planes[0].surface.htile_offset + image->planes[0].surface.htile_slice_size * range->baseArrayLayer; + uint32_t htile_mask, flush_bits; - return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value); + htile_mask = radv_get_htile_mask(image, range->aspectMask); + + if (htile_mask == UINT_MAX) { + /* Clear the whole HTILE buffer. */ + flush_bits = radv_fill_buffer(cmd_buffer, image->bo, offset, + size, value); + } else { + /* Only clear depth or stencil bytes in the HTILE buffer. */ + flush_bits = clear_htile_mask(cmd_buffer, image->bo, offset, + size, value, htile_mask); + } + + return flush_bits; } -static void vi_get_fast_clear_parameters(VkFormat format, +enum { + RADV_DCC_CLEAR_REG = 0x20202020U, + RADV_DCC_CLEAR_MAIN_1 = 0x80808080U, + RADV_DCC_CLEAR_SECONDARY_1 = 0x40404040U +}; + +static void vi_get_fast_clear_parameters(struct radv_device *device, + VkFormat image_format, + VkFormat view_format, const VkClearColorValue *clear_value, uint32_t* reset_value, bool *can_avoid_fast_clear_elim) @@ -1367,18 +1612,20 @@ static void vi_get_fast_clear_parameters(VkFormat format, int extra_channel; bool main_value = false; bool extra_value = false; + bool has_color = false; + bool has_alpha = false; int i; *can_avoid_fast_clear_elim = false; - *reset_value = 0x20202020U; + *reset_value = RADV_DCC_CLEAR_REG; - const struct vk_format_description *desc = vk_format_description(format); - if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 || - format == VK_FORMAT_R5G6B5_UNORM_PACK16 || - format == VK_FORMAT_B5G6R5_UNORM_PACK16) + const struct vk_format_description *desc = vk_format_description(view_format); + if (view_format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 || + view_format == VK_FORMAT_R5G6B5_UNORM_PACK16 || + view_format == VK_FORMAT_B5G6R5_UNORM_PACK16) extra_channel = -1; else if (desc->layout == VK_FORMAT_LAYOUT_PLAIN) { - if (radv_translate_colorswap(format, false) <= 1) + if (vi_alpha_is_on_msb(device, view_format)) extra_channel = desc->nr_channels - 1; else extra_channel = 0; @@ -1413,12 +1660,21 @@ static void vi_get_fast_clear_parameters(VkFormat format, return; } - if (index == extra_channel) + if (index == extra_channel) { extra_value = values[i]; - else + has_alpha = true; + } else { main_value = values[i]; + has_color = true; + } } + /* If alpha isn't present, make it the same as color, and vice versa. */ + if (!has_alpha) + extra_value = main_value; + else if (!has_color) + main_value = extra_value; + for (int i = 0; i < 4; ++i) if (values[i] != main_value && desc->swizzle[i] - VK_SWIZZLE_X != extra_channel && @@ -1427,11 +1683,12 @@ static void vi_get_fast_clear_parameters(VkFormat format, return; *can_avoid_fast_clear_elim = true; + *reset_value = 0; if (main_value) - *reset_value |= 0x80808080U; + *reset_value |= RADV_DCC_CLEAR_MAIN_1; if (extra_value) - *reset_value |= 0x40404040U; + *reset_value |= RADV_DCC_CLEAR_SECONDARY_1; return; } @@ -1439,6 +1696,7 @@ static bool radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_image_view *iview, VkImageLayout image_layout, + bool in_render_loop, const VkClearRect *clear_rect, VkClearColorValue clear_value, uint32_t view_mask) @@ -1448,7 +1706,10 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, if (!radv_image_view_can_fast_clear(cmd_buffer->device, iview)) return false; - if (!radv_layout_can_fast_clear(iview->image, image_layout, radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, cmd_buffer->queue_family_index))) + if (!radv_layout_can_fast_clear(iview->image, image_layout, in_render_loop, + radv_image_queue_family_mask(iview->image, + cmd_buffer->queue_family_index, + cmd_buffer->queue_family_index))) return false; if (clear_rect->rect.offset.x || clear_rect->rect.offset.y || @@ -1469,11 +1730,13 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, clear_color, &clear_value)) return false; - if (radv_image_has_dcc(iview->image)) { + if (radv_dcc_enabled(iview->image, iview->base_mip)) { bool can_avoid_fast_clear_elim; uint32_t reset_value; - vi_get_fast_clear_parameters(iview->vk_format, + vi_get_fast_clear_parameters(cmd_buffer->device, + iview->image->vk_format, + iview->vk_format, &clear_value, &reset_value, &can_avoid_fast_clear_elim); @@ -1488,6 +1751,21 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, if (!can_avoid_fast_clear_elim) return false; } + + if (iview->image->info.levels > 1 && + cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) { + for (uint32_t l = 0; l < iview->level_count; l++) { + uint32_t level = iview->base_mip + l; + struct legacy_surf_level *surf_level = + &iview->image->planes[0].surface.u.legacy.level[level]; + + /* Do not fast clears if one level can't be + * fast cleared. + */ + if (!surf_level->dcc_fast_clear_size) + return false; + } + } } return true; @@ -1505,6 +1783,13 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, VkClearColorValue clear_value = clear_att->clearValue.color; uint32_t clear_color[2], flush_bits = 0; uint32_t cmask_clear_value; + VkImageSubresourceRange range = { + .aspectMask = iview->aspect_mask, + .baseMipLevel = iview->base_mip, + .levelCount = iview->level_count, + .baseArrayLayer = iview->base_layer, + .layerCount = iview->layer_count, + }; if (pre_flush) { cmd_buffer->state.flush_bits |= (RADV_CMD_FLAG_FLUSH_AND_INV_CB | @@ -1518,25 +1803,20 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image); /* clear cmask buffer */ - if (radv_image_has_dcc(iview->image)) { + if (radv_dcc_enabled(iview->image, iview->base_mip)) { uint32_t reset_value; bool can_avoid_fast_clear_elim; bool need_decompress_pass = false; - VkImageSubresourceRange range = { - .aspectMask = iview->aspect_mask, - .baseMipLevel = iview->base_mip, - .levelCount = iview->level_count, - .baseArrayLayer = iview->base_layer, - .layerCount = iview->layer_count, - }; - vi_get_fast_clear_parameters(iview->vk_format, + vi_get_fast_clear_parameters(cmd_buffer->device, + iview->image->vk_format, + iview->vk_format, &clear_value, &reset_value, &can_avoid_fast_clear_elim); if (radv_image_has_cmask(iview->image)) { flush_bits = radv_clear_cmask(cmd_buffer, iview->image, - cmask_clear_value); + &range, cmask_clear_value); need_decompress_pass = true; } @@ -1551,7 +1831,7 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, need_decompress_pass); } else { flush_bits = radv_clear_cmask(cmd_buffer, iview->image, - cmask_clear_value); + &range, cmask_clear_value); } if (post_flush) { @@ -1571,7 +1851,8 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearRect *clear_rect, enum radv_cmd_flush_bits *pre_flush, enum radv_cmd_flush_bits *post_flush, - uint32_t view_mask) + uint32_t view_mask, + bool ds_resolve_clear) { const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer; const struct radv_subpass *subpass = cmd_buffer->state.subpass; @@ -1585,10 +1866,11 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer, return; VkImageLayout image_layout = subpass->color_attachments[subpass_att].layout; - const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL; + bool in_render_loop = subpass->color_attachments[subpass_att].in_render_loop; + const struct radv_image_view *iview = fb ? cmd_buffer->state.attachments[pass_att].iview : NULL; VkClearColorValue clear_value = clear_att->clearValue.color; - if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout, + if (radv_can_fast_clear_color(cmd_buffer, iview, image_layout, in_render_loop, clear_rect, clear_value, view_mask)) { radv_fast_clear_color(cmd_buffer, iview, clear_att, subpass_att, pre_flush, @@ -1597,25 +1879,30 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer, emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask); } } else { - const uint32_t pass_att = subpass->depth_stencil_attachment->attachment; - if (pass_att == VK_ATTACHMENT_UNUSED) + struct radv_subpass_attachment *ds_att = subpass->depth_stencil_attachment; + + if (ds_resolve_clear) + ds_att = subpass->ds_resolve_attachment; + + if (!ds_att || ds_att->attachment == VK_ATTACHMENT_UNUSED) return; - VkImageLayout image_layout = subpass->depth_stencil_attachment->layout; - const struct radv_image_view *iview = fb ? fb->attachments[pass_att].attachment : NULL; + VkImageLayout image_layout = ds_att->layout; + bool in_render_loop = ds_att->in_render_loop; + const struct radv_image_view *iview = fb ? cmd_buffer->state.attachments[ds_att->attachment].iview : NULL; VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil; assert(aspects & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)); if (radv_can_fast_clear_depth(cmd_buffer, iview, image_layout, - aspects, clear_rect, clear_value, - view_mask)) { + in_render_loop, aspects, clear_rect, + clear_value, view_mask)) { radv_fast_clear_depth(cmd_buffer, iview, clear_att, pre_flush, post_flush); } else { emit_depthstencil_clear(cmd_buffer, clear_att, clear_rect, - view_mask); + ds_att, view_mask); } } } @@ -1644,10 +1931,16 @@ radv_subpass_needs_clear(struct radv_cmd_buffer *cmd_buffer) return true; } - if (!cmd_state->subpass->depth_stencil_attachment) + if (cmd_state->subpass->depth_stencil_attachment) { + a = cmd_state->subpass->depth_stencil_attachment->attachment; + if (radv_attachment_needs_clear(cmd_state, a)) + return true; + } + + if (!cmd_state->subpass->ds_resolve_attachment) return false; - a = cmd_state->subpass->depth_stencil_attachment->attachment; + a = cmd_state->subpass->ds_resolve_attachment->attachment; return radv_attachment_needs_clear(cmd_state, a); } @@ -1656,7 +1949,8 @@ radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer, struct radv_attachment_state *attachment, const VkClearAttachment *clear_att, enum radv_cmd_flush_bits *pre_flush, - enum radv_cmd_flush_bits *post_flush) + enum radv_cmd_flush_bits *post_flush, + bool ds_resolve_clear) { struct radv_cmd_state *cmd_state = &cmd_buffer->state; uint32_t view_mask = cmd_state->subpass->view_mask; @@ -1667,12 +1961,16 @@ radv_subpass_clear_attachment(struct radv_cmd_buffer *cmd_buffer, .layerCount = cmd_state->framebuffer->layers, }; + radv_describe_begin_render_pass_clear(cmd_buffer, clear_att->aspectMask); + emit_clear(cmd_buffer, clear_att, &clear_rect, pre_flush, post_flush, - view_mask & ~attachment->cleared_views); + view_mask & ~attachment->cleared_views, ds_resolve_clear); if (view_mask) attachment->cleared_views |= view_mask; else attachment->pending_clear_aspects = 0; + + radv_describe_end_render_pass_clear(cmd_buffer); } /** @@ -1713,7 +2011,7 @@ radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer) radv_subpass_clear_attachment(cmd_buffer, &cmd_state->attachments[a], &clear_att, &pre_flush, - &post_flush); + &post_flush, false); } if (cmd_state->subpass->depth_stencil_attachment) { @@ -1727,7 +2025,22 @@ radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer) radv_subpass_clear_attachment(cmd_buffer, &cmd_state->attachments[ds], &clear_att, &pre_flush, - &post_flush); + &post_flush, false); + } + } + + if (cmd_state->subpass->ds_resolve_attachment) { + uint32_t ds_resolve = cmd_state->subpass->ds_resolve_attachment->attachment; + if (radv_attachment_needs_clear(cmd_state, ds_resolve)) { + VkClearAttachment clear_att = { + .aspectMask = cmd_state->attachments[ds_resolve].pending_clear_aspects, + .clearValue = cmd_state->attachments[ds_resolve].clear_value, + }; + + radv_subpass_clear_attachment(cmd_buffer, + &cmd_state->attachments[ds_resolve], + &clear_att, &pre_flush, + &post_flush, true); } } @@ -1761,7 +2074,7 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, .baseArrayLayer = range->baseArrayLayer + layer, .layerCount = 1 }, - }); + }, NULL); VkFramebuffer fb; radv_CreateFramebuffer(device_h, @@ -1819,26 +2132,49 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, .pAttachments = &att_desc, .subpassCount = 1, .pSubpasses = &subpass_desc, - }, + .dependencyCount = 2, + .pDependencies = (VkSubpassDependency[]) { + { + .srcSubpass = VK_SUBPASS_EXTERNAL, + .dstSubpass = 0, + .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, + .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, + .srcAccessMask = 0, + .dstAccessMask = 0, + .dependencyFlags = 0 + }, + { + .srcSubpass = 0, + .dstSubpass = VK_SUBPASS_EXTERNAL, + .srcStageMask = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, + .dstStageMask = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT, + .srcAccessMask = 0, + .dstAccessMask = 0, + .dependencyFlags = 0 + } + } + }, &cmd_buffer->pool->alloc, &pass); - radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer), - &(VkRenderPassBeginInfo) { - .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, + radv_cmd_buffer_begin_render_pass(cmd_buffer, + &(VkRenderPassBeginInfo) { + .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO, .renderArea = { .offset = { 0, 0, }, .extent = { .width = width, .height = height, + }, }, - }, .renderPass = pass, .framebuffer = fb, .clearValueCount = 0, .pClearValues = NULL, - }, - VK_SUBPASS_CONTENTS_INLINE); + }); + + radv_cmd_buffer_set_subpass(cmd_buffer, + &cmd_buffer->state.pass->subpasses[0]); VkClearAttachment clear_att = { .aspectMask = range->aspectMask, @@ -1855,9 +2191,9 @@ radv_clear_image_layer(struct radv_cmd_buffer *cmd_buffer, .layerCount = 1, /* FINISHME: clear multi-layer framebuffer */ }; - emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0); + emit_clear(cmd_buffer, &clear_att, &clear_rect, NULL, NULL, 0, false); - radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer)); + radv_cmd_buffer_end_render_pass(cmd_buffer); radv_DestroyRenderPass(device_h, pass, &cmd_buffer->pool->alloc); radv_DestroyFramebuffer(device_h, fb, @@ -1872,6 +2208,7 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, VkFormat format, VkImageLayout image_layout, + bool in_render_loop, const VkImageSubresourceRange *range, const VkClearValue *clear_val) { @@ -1890,7 +2227,7 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, .baseArrayLayer = range->baseArrayLayer, .layerCount = range->layerCount, }, - }); + }, NULL); VkClearRect clear_rect = { .rect = { @@ -1911,8 +2248,8 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, }; if (vk_format_is_color(format)) { - if (radv_can_fast_clear_color(cmd_buffer, &iview, - image_layout, &clear_rect, + if (radv_can_fast_clear_color(cmd_buffer, &iview, image_layout, + in_render_loop, &clear_rect, clear_att.clearValue.color, 0)) { radv_fast_clear_color(cmd_buffer, &iview, &clear_att, clear_att.colorAttachment, @@ -1921,8 +2258,9 @@ radv_fast_clear_range(struct radv_cmd_buffer *cmd_buffer, } } else { if (radv_can_fast_clear_depth(cmd_buffer, &iview, image_layout, - range->aspectMask, &clear_rect, - clear_att.clearValue.depthStencil, 0)) { + in_render_loop,range->aspectMask, + &clear_rect, clear_att.clearValue.depthStencil, + 0)) { radv_fast_clear_depth(cmd_buffer, &iview, &clear_att, NULL, NULL); return true; @@ -1972,7 +2310,7 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, */ if (!cs && radv_fast_clear_range(cmd_buffer, image, format, - image_layout, range, + image_layout, false, range, &internal_clear_value)) { continue; } @@ -2080,7 +2418,7 @@ void radv_CmdClearAttachments( for (uint32_t a = 0; a < attachmentCount; ++a) { for (uint32_t r = 0; r < rectCount; ++r) { emit_clear(cmd_buffer, &pAttachments[a], &pRects[r], &pre_flush, &post_flush, - cmd_buffer->state.subpass->view_mask); + cmd_buffer->state.subpass->view_mask, false); } }