X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_pipeline.c;h=b239f024cbeebc8f440c88ddd2a59abf1fb62e0a;hb=08dd70465e601a85be31982d6e9054e23ad7aad8;hp=9b68650fd36bab859edea100ccacb5d69962bf15;hpb=a7b7e940856c406ab4bdb3b94c7598d8db031451;p=mesa.git diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 9b68650fd36..62fd14d2cc9 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -25,6 +25,7 @@ * IN THE SOFTWARE. */ +#include "util/disk_cache.h" #include "util/mesa-sha1.h" #include "util/u_atomic.h" #include "radv_debug.h" @@ -33,12 +34,10 @@ #include "radv_shader.h" #include "nir/nir.h" #include "nir/nir_builder.h" +#include "nir/nir_xfb_info.h" #include "spirv/nir_spirv.h" #include "vk_util.h" -#include -#include - #include "sid.h" #include "ac_binary.h" #include "ac_llvm_util.h" @@ -47,7 +46,6 @@ #include "util/debug.h" #include "ac_exp_param.h" #include "ac_shader_util.h" -#include "main/menums.h" struct radv_blend_state { uint32_t blend_enable_4bit; @@ -60,6 +58,8 @@ struct radv_blend_state { uint32_t cb_blend_control[8]; uint32_t spi_shader_col_format; + uint32_t col_format_is_int8; + uint32_t col_format_is_int10; uint32_t cb_shader_mask; uint32_t db_alpha_to_mask; @@ -82,29 +82,49 @@ struct radv_dsa_order_invariance { bool pass_set; }; -struct radv_tessellation_state { - uint32_t ls_hs_config; - unsigned num_patches; - unsigned lds_size; - uint32_t tf_param; -}; +static const VkPipelineMultisampleStateCreateInfo * +radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo) +{ + if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) + return pCreateInfo->pMultisampleState; + return NULL; +} -struct radv_gs_state { - uint32_t vgt_gs_onchip_cntl; - uint32_t vgt_gs_max_prims_per_subgroup; - uint32_t vgt_esgs_ring_itemsize; - uint32_t lds_size; -}; +static const VkPipelineTessellationStateCreateInfo * +radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo) +{ + for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) { + if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT || + pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) { + return pCreateInfo->pTessellationState; + } + } + return NULL; +} -struct radv_ngg_state { - uint16_t ngg_emit_size; /* in dwords */ - uint32_t hw_max_esverts; - uint32_t max_gsprims; - uint32_t max_out_verts; - uint32_t prim_amp_factor; - uint32_t vgt_esgs_ring_itemsize; - bool max_vert_out_per_gs_instance; -}; +static const VkPipelineDepthStencilStateCreateInfo * +radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo) +{ + RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); + struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; + + if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable && + subpass->depth_stencil_attachment) + return pCreateInfo->pDepthStencilState; + return NULL; +} + +static const VkPipelineColorBlendStateCreateInfo * +radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo) +{ + RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); + struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; + + if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable && + subpass->has_color_att) + return pCreateInfo->pColorBlendState; + return NULL; +} bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline) { @@ -120,6 +140,38 @@ bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline) return variant->info.is_ngg; } +bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline) +{ + assert(radv_pipeline_has_ngg(pipeline)); + + struct radv_shader_variant *variant = NULL; + if (pipeline->shaders[MESA_SHADER_GEOMETRY]) + variant = pipeline->shaders[MESA_SHADER_GEOMETRY]; + else if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) + variant = pipeline->shaders[MESA_SHADER_TESS_EVAL]; + else if (pipeline->shaders[MESA_SHADER_VERTEX]) + variant = pipeline->shaders[MESA_SHADER_VERTEX]; + else + return false; + return variant->info.is_ngg_passthrough; +} + +bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline) +{ + if (!radv_pipeline_has_gs(pipeline)) + return false; + + /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9. + * On GFX10, it might be required in rare cases if it's not possible to + * enable NGG. + */ + if (radv_pipeline_has_ngg(pipeline)) + return false; + + assert(pipeline->gs_copy_shader); + return true; +} + static void radv_pipeline_destroy(struct radv_device *device, struct radv_pipeline *pipeline, @@ -134,7 +186,9 @@ radv_pipeline_destroy(struct radv_device *device, if(pipeline->cs.buf) free(pipeline->cs.buf); - vk_free2(&device->alloc, allocator, pipeline); + + vk_object_base_finish(&pipeline->base); + vk_free2(&device->vk.alloc, allocator, pipeline); } void radv_DestroyPipeline( @@ -155,10 +209,16 @@ static uint32_t get_hash_flags(struct radv_device *device) { uint32_t hash_flags = 0; - if (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH) - hash_flags |= RADV_HASH_SHADER_UNSAFE_MATH; - if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED) - hash_flags |= RADV_HASH_SHADER_SISCHED; + if (device->instance->debug_flags & RADV_DEBUG_NO_NGG) + hash_flags |= RADV_HASH_SHADER_NO_NGG; + if (device->physical_device->cs_wave_size == 32) + hash_flags |= RADV_HASH_SHADER_CS_WAVE32; + if (device->physical_device->ps_wave_size == 32) + hash_flags |= RADV_HASH_SHADER_PS_WAVE32; + if (device->physical_device->ge_wave_size == 32) + hash_flags |= RADV_HASH_SHADER_GE_WAVE32; + if (device->physical_device->use_llvm) + hash_flags |= RADV_HASH_SHADER_LLVM; return hash_flags; } @@ -171,7 +231,8 @@ radv_pipeline_scratch_init(struct radv_device *device, unsigned min_waves = 1; for (int i = 0; i < MESA_SHADER_STAGES; ++i) { - if (pipeline->shaders[i]) { + if (pipeline->shaders[i] && + pipeline->shaders[i]->config.scratch_bytes_per_wave) { unsigned max_stage_waves = device->scratch_waves; scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave, @@ -191,14 +252,6 @@ radv_pipeline_scratch_init(struct radv_device *device, min_waves = MAX2(min_waves, round_up_u32(group_size, 64)); } - if (scratch_bytes_per_wave) - max_waves = MIN2(max_waves, 0xffffffffu / scratch_bytes_per_wave); - - if (scratch_bytes_per_wave && max_waves < min_waves) { - /* Not really true at this moment, but will be true on first - * execution. Avoid having hanging shaders. */ - return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY); - } pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave; pipeline->max_waves = max_waves; return VK_SUCCESS; @@ -395,128 +448,53 @@ static bool is_dual_src(VkBlendFactor factor) } } -static unsigned si_choose_spi_color_format(VkFormat vk_format, - bool blend_enable, - bool blend_need_alpha) +static unsigned radv_choose_spi_color_format(VkFormat vk_format, + bool blend_enable, + bool blend_need_alpha) { const struct vk_format_description *desc = vk_format_description(vk_format); + struct ac_spi_color_formats formats = {}; unsigned format, ntype, swap; - /* Alpha is needed for alpha-to-coverage. - * Blending may be with or without alpha. - */ - unsigned normal = 0; /* most optimal, may not support blending or export alpha */ - unsigned alpha = 0; /* exports alpha, but may not support blending */ - unsigned blend = 0; /* supports blending, but may not export alpha */ - unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */ - format = radv_translate_colorformat(vk_format); ntype = radv_translate_color_numformat(vk_format, desc, vk_format_get_first_non_void_channel(vk_format)); swap = radv_translate_colorswap(vk_format, false); - /* Choose the SPI color formats. These are required values for Stoney/RB+. - * Other chips have multiple choices, though they are not necessarily better. - */ - switch (format) { - case V_028C70_COLOR_5_6_5: - case V_028C70_COLOR_1_5_5_5: - case V_028C70_COLOR_5_5_5_1: - case V_028C70_COLOR_4_4_4_4: - case V_028C70_COLOR_10_11_11: - case V_028C70_COLOR_11_11_10: - case V_028C70_COLOR_8: - case V_028C70_COLOR_8_8: - case V_028C70_COLOR_8_8_8_8: - case V_028C70_COLOR_10_10_10_2: - case V_028C70_COLOR_2_10_10_10: - if (ntype == V_028C70_NUMBER_UINT) - alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; - else if (ntype == V_028C70_NUMBER_SINT) - alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; - else - alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; - break; + ac_choose_spi_color_formats(format, swap, ntype, false, &formats); - case V_028C70_COLOR_16: - case V_028C70_COLOR_16_16: - case V_028C70_COLOR_16_16_16_16: - if (ntype == V_028C70_NUMBER_UNORM || - ntype == V_028C70_NUMBER_SNORM) { - /* UNORM16 and SNORM16 don't support blending */ - if (ntype == V_028C70_NUMBER_UNORM) - normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR; - else - normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR; - - /* Use 32 bits per channel for blending. */ - if (format == V_028C70_COLOR_16) { - if (swap == V_028C70_SWAP_STD) { /* R */ - blend = V_028714_SPI_SHADER_32_R; - blend_alpha = V_028714_SPI_SHADER_32_AR; - } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ - blend = blend_alpha = V_028714_SPI_SHADER_32_AR; - else - assert(0); - } else if (format == V_028C70_COLOR_16_16) { - if (swap == V_028C70_SWAP_STD) { /* RG */ - blend = V_028714_SPI_SHADER_32_GR; - blend_alpha = V_028714_SPI_SHADER_32_ABGR; - } else if (swap == V_028C70_SWAP_ALT) /* RA */ - blend = blend_alpha = V_028714_SPI_SHADER_32_AR; - else - assert(0); - } else /* 16_16_16_16 */ - blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR; - } else if (ntype == V_028C70_NUMBER_UINT) - alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; - else if (ntype == V_028C70_NUMBER_SINT) - alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; - else if (ntype == V_028C70_NUMBER_FLOAT) - alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; - else - assert(0); - break; + if (blend_enable && blend_need_alpha) + return formats.blend_alpha; + else if(blend_need_alpha) + return formats.alpha; + else if(blend_enable) + return formats.blend; + else + return formats.normal; +} - case V_028C70_COLOR_32: - if (swap == V_028C70_SWAP_STD) { /* R */ - blend = normal = V_028714_SPI_SHADER_32_R; - alpha = blend_alpha = V_028714_SPI_SHADER_32_AR; - } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ - alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; - else - assert(0); - break; +static bool +format_is_int8(VkFormat format) +{ + const struct vk_format_description *desc = vk_format_description(format); + int channel = vk_format_get_first_non_void_channel(format); - case V_028C70_COLOR_32_32: - if (swap == V_028C70_SWAP_STD) { /* RG */ - blend = normal = V_028714_SPI_SHADER_32_GR; - alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR; - } else if (swap == V_028C70_SWAP_ALT) /* RA */ - alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; - else - assert(0); - break; + return channel >= 0 && desc->channel[channel].pure_integer && + desc->channel[channel].size == 8; +} - case V_028C70_COLOR_32_32_32_32: - case V_028C70_COLOR_8_24: - case V_028C70_COLOR_24_8: - case V_028C70_COLOR_X24_8_32_FLOAT: - alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR; - break; +static bool +format_is_int10(VkFormat format) +{ + const struct vk_format_description *desc = vk_format_description(format); - default: - unreachable("unhandled blend format"); + if (desc->nr_channels != 4) + return false; + for (unsigned i = 0; i < 4; i++) { + if (desc->channel[i].pure_integer && desc->channel[i].size == 10) + return true; } - - if (blend_enable && blend_need_alpha) - return blend_alpha; - else if(blend_need_alpha) - return alpha; - else if(blend_enable) - return blend; - else - return normal; + return false; } static void @@ -526,22 +504,28 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline, { RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; - unsigned col_format = 0; + unsigned col_format = 0, is_int8 = 0, is_int10 = 0; unsigned num_targets; for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) { unsigned cf; - if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) { + if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED || + !(blend->cb_target_mask & (0xfu << (i * 4)))) { cf = V_028714_SPI_SHADER_ZERO; } else { struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment; bool blend_enable = blend->blend_enable_4bit & (0xfu << (i * 4)); - cf = si_choose_spi_color_format(attachment->format, - blend_enable, - blend->need_src_alpha & (1 << i)); + cf = radv_choose_spi_color_format(attachment->format, + blend_enable, + blend->need_src_alpha & (1 << i)); + + if (format_is_int8(attachment->format)) + is_int8 |= 1 << i; + if (format_is_int10(attachment->format)) + is_int10 |= 1 << i; } col_format |= cf << (4 * i); @@ -571,32 +555,9 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline, if (blend->mrt0_is_dual_src) col_format |= (col_format & 0xf) << 4; - blend->cb_shader_mask = ac_get_cb_shader_mask(col_format); blend->spi_shader_col_format = col_format; -} - -static bool -format_is_int8(VkFormat format) -{ - const struct vk_format_description *desc = vk_format_description(format); - int channel = vk_format_get_first_non_void_channel(format); - - return channel >= 0 && desc->channel[channel].pure_integer && - desc->channel[channel].size == 8; -} - -static bool -format_is_int10(VkFormat format) -{ - const struct vk_format_description *desc = vk_format_description(format); - - if (desc->nr_channels != 4) - return false; - for (unsigned i = 0; i < 4; i++) { - if (desc->channel[i].pure_integer && desc->channel[i].size == 10) - return true; - } - return false; + blend->col_format_is_int8 = is_int8; + blend->col_format_is_int10 = is_int10; } /* @@ -620,7 +581,7 @@ const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = { unsigned radv_format_meta_fs_key(VkFormat format) { - unsigned col_format = si_choose_spi_color_format(format, false, false); + unsigned col_format = radv_choose_spi_color_format(format, false, false); assert(col_format != V_028714_SPI_SHADER_32_AR); if (col_format >= V_028714_SPI_SHADER_32_AR) @@ -633,30 +594,6 @@ unsigned radv_format_meta_fs_key(VkFormat format) return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0); } -static void -radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo, - unsigned *is_int8, unsigned *is_int10) -{ - RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); - struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; - *is_int8 = 0; - *is_int10 = 0; - - for (unsigned i = 0; i < subpass->color_count; ++i) { - struct radv_render_pass_attachment *attachment; - - if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) - continue; - - attachment = pass->attachments + subpass->color_attachments[i].attachment; - - if (format_is_int8(attachment->format)) - *is_int8 |= 1 << i; - if (format_is_int10(attachment->format)) - *is_int10 |= 1 << i; - } -} - static void radv_blend_check_commutativity(struct radv_blend_state *blend, VkBlendOp op, VkBlendFactor src, @@ -696,24 +633,24 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo, const struct radv_graphics_pipeline_create_info *extra) { - const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState; - const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState; + const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo); + const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo); struct radv_blend_state blend = {0}; unsigned mode = V_028808_CB_NORMAL; int i; - if (!vkblend) - return blend; - if (extra && extra->custom_blend_mode) { blend.single_cb_enable = true; mode = extra->custom_blend_mode; } + blend.cb_color_control = 0; - if (vkblend->logicOpEnable) - blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp)); - else - blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY); + if (vkblend) { + if (vkblend->logicOpEnable) + blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp)); + else + blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY); + } blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) | @@ -727,120 +664,122 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, } blend.cb_target_mask = 0; - for (i = 0; i < vkblend->attachmentCount; i++) { - const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i]; - unsigned blend_cntl = 0; - unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt; - VkBlendOp eqRGB = att->colorBlendOp; - VkBlendFactor srcRGB = att->srcColorBlendFactor; - VkBlendFactor dstRGB = att->dstColorBlendFactor; - VkBlendOp eqA = att->alphaBlendOp; - VkBlendFactor srcA = att->srcAlphaBlendFactor; - VkBlendFactor dstA = att->dstAlphaBlendFactor; - - blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); - - if (!att->colorWriteMask) - continue; - - blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i); - blend.cb_target_enabled_4bit |= 0xf << (4 * i); - if (!att->blendEnable) { - blend.cb_blend_control[i] = blend_cntl; - continue; - } + if (vkblend) { + for (i = 0; i < vkblend->attachmentCount; i++) { + const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i]; + unsigned blend_cntl = 0; + unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt; + VkBlendOp eqRGB = att->colorBlendOp; + VkBlendFactor srcRGB = att->srcColorBlendFactor; + VkBlendFactor dstRGB = att->dstColorBlendFactor; + VkBlendOp eqA = att->alphaBlendOp; + VkBlendFactor srcA = att->srcAlphaBlendFactor; + VkBlendFactor dstA = att->dstAlphaBlendFactor; + + blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); + + if (!att->colorWriteMask) + continue; - if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA)) - if (i == 0) - blend.mrt0_is_dual_src = true; + blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i); + blend.cb_target_enabled_4bit |= 0xf << (4 * i); + if (!att->blendEnable) { + blend.cb_blend_control[i] = blend_cntl; + continue; + } - if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) { - srcRGB = VK_BLEND_FACTOR_ONE; - dstRGB = VK_BLEND_FACTOR_ONE; - } - if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) { - srcA = VK_BLEND_FACTOR_ONE; - dstA = VK_BLEND_FACTOR_ONE; - } + if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA)) + if (i == 0) + blend.mrt0_is_dual_src = true; - radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB, - 0x7 << (4 * i)); - radv_blend_check_commutativity(&blend, eqA, srcA, dstA, - 0x8 << (4 * i)); + if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) { + srcRGB = VK_BLEND_FACTOR_ONE; + dstRGB = VK_BLEND_FACTOR_ONE; + } + if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) { + srcA = VK_BLEND_FACTOR_ONE; + dstA = VK_BLEND_FACTOR_ONE; + } - /* Blending optimizations for RB+. - * These transformations don't change the behavior. - * - * First, get rid of DST in the blend factors: - * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC) - */ - si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB, - VK_BLEND_FACTOR_DST_COLOR, - VK_BLEND_FACTOR_SRC_COLOR); - - si_blend_remove_dst(&eqA, &srcA, &dstA, - VK_BLEND_FACTOR_DST_COLOR, - VK_BLEND_FACTOR_SRC_COLOR); - - si_blend_remove_dst(&eqA, &srcA, &dstA, - VK_BLEND_FACTOR_DST_ALPHA, - VK_BLEND_FACTOR_SRC_ALPHA); - - /* Look up the ideal settings from tables. */ - srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false); - dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false); - srcA_opt = si_translate_blend_opt_factor(srcA, true); - dstA_opt = si_translate_blend_opt_factor(dstA, true); - - /* Handle interdependencies. */ - if (si_blend_factor_uses_dst(srcRGB)) - dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; - if (si_blend_factor_uses_dst(srcA)) - dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; - - if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE && - (dstRGB == VK_BLEND_FACTOR_ZERO || - dstRGB == VK_BLEND_FACTOR_SRC_ALPHA || - dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE)) - dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0; - - /* Set the final value. */ - blend.sx_mrt_blend_opt[i] = - S_028760_COLOR_SRC_OPT(srcRGB_opt) | - S_028760_COLOR_DST_OPT(dstRGB_opt) | - S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) | - S_028760_ALPHA_SRC_OPT(srcA_opt) | - S_028760_ALPHA_DST_OPT(dstA_opt) | - S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA)); - blend_cntl |= S_028780_ENABLE(1); - - blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); - blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); - blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); - if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { - blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); - blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); - blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); - blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); - } - blend.cb_blend_control[i] = blend_cntl; + radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB, + 0x7 << (4 * i)); + radv_blend_check_commutativity(&blend, eqA, srcA, dstA, + 0x8 << (4 * i)); + + /* Blending optimizations for RB+. + * These transformations don't change the behavior. + * + * First, get rid of DST in the blend factors: + * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC) + */ + si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB, + VK_BLEND_FACTOR_DST_COLOR, + VK_BLEND_FACTOR_SRC_COLOR); + + si_blend_remove_dst(&eqA, &srcA, &dstA, + VK_BLEND_FACTOR_DST_COLOR, + VK_BLEND_FACTOR_SRC_COLOR); + + si_blend_remove_dst(&eqA, &srcA, &dstA, + VK_BLEND_FACTOR_DST_ALPHA, + VK_BLEND_FACTOR_SRC_ALPHA); + + /* Look up the ideal settings from tables. */ + srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false); + dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false); + srcA_opt = si_translate_blend_opt_factor(srcA, true); + dstA_opt = si_translate_blend_opt_factor(dstA, true); + + /* Handle interdependencies. */ + if (si_blend_factor_uses_dst(srcRGB)) + dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; + if (si_blend_factor_uses_dst(srcA)) + dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; + + if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE && + (dstRGB == VK_BLEND_FACTOR_ZERO || + dstRGB == VK_BLEND_FACTOR_SRC_ALPHA || + dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE)) + dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0; + + /* Set the final value. */ + blend.sx_mrt_blend_opt[i] = + S_028760_COLOR_SRC_OPT(srcRGB_opt) | + S_028760_COLOR_DST_OPT(dstRGB_opt) | + S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) | + S_028760_ALPHA_SRC_OPT(srcA_opt) | + S_028760_ALPHA_DST_OPT(dstA_opt) | + S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA)); + blend_cntl |= S_028780_ENABLE(1); + + blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); + blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); + blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); + if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { + blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); + blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); + blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); + blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); + } + blend.cb_blend_control[i] = blend_cntl; - blend.blend_enable_4bit |= 0xfu << (i * 4); + blend.blend_enable_4bit |= 0xfu << (i * 4); - if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA || - dstRGB == VK_BLEND_FACTOR_SRC_ALPHA || - srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || - dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || - srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA || - dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) - blend.need_src_alpha |= 1 << i; - } - for (i = vkblend->attachmentCount; i < 8; i++) { - blend.cb_blend_control[i] = 0; - blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); + if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA || + dstRGB == VK_BLEND_FACTOR_SRC_ALPHA || + srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || + dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE || + srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA || + dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) + blend.need_src_alpha |= 1 << i; + } + for (i = vkblend->attachmentCount; i < 8; i++) { + blend.cb_blend_control[i] = 0; + blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); + } } - if (pipeline->device->physical_device->has_rbplus) { + if (pipeline->device->physical_device->rad_info.has_rbplus) { /* Disable RB+ blend optimizations for dual source blending. */ if (blend.mrt0_is_dual_src) { for (i = 0; i < 8; i++) { @@ -853,7 +792,8 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, /* RB+ doesn't work with dual source blending, logic op and * RESOLVE. */ - if (blend.mrt0_is_dual_src || vkblend->logicOpEnable || + if (blend.mrt0_is_dual_src || + (vkblend && vkblend->logicOpEnable) || mode == V_028808_CB_RESOLVE) blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1); } @@ -867,30 +807,6 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline, return blend; } -static uint32_t si_translate_stencil_op(enum VkStencilOp op) -{ - switch (op) { - case VK_STENCIL_OP_KEEP: - return V_02842C_STENCIL_KEEP; - case VK_STENCIL_OP_ZERO: - return V_02842C_STENCIL_ZERO; - case VK_STENCIL_OP_REPLACE: - return V_02842C_STENCIL_REPLACE_TEST; - case VK_STENCIL_OP_INCREMENT_AND_CLAMP: - return V_02842C_STENCIL_ADD_CLAMP; - case VK_STENCIL_OP_DECREMENT_AND_CLAMP: - return V_02842C_STENCIL_SUB_CLAMP; - case VK_STENCIL_OP_INVERT: - return V_02842C_STENCIL_INVERT; - case VK_STENCIL_OP_INCREMENT_AND_WRAP: - return V_02842C_STENCIL_ADD_WRAP; - case VK_STENCIL_OP_DECREMENT_AND_WRAP: - return V_02842C_STENCIL_SUB_WRAP; - default: - return 0; - } -} - static uint32_t si_translate_fill(VkPolygonMode func) { switch(func) { @@ -906,13 +822,30 @@ static uint32_t si_translate_fill(VkPolygonMode func) } } -static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms) +static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo) { - uint32_t num_samples = vkms->rasterizationSamples; + const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState; + RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); + struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass]; uint32_t ps_iter_samples = 1; + uint32_t num_samples; + + /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading: + * + * "If the VK_AMD_mixed_attachment_samples extension is enabled and the + * subpass uses color attachments, totalSamples is the number of + * samples of the color attachments. Otherwise, totalSamples is the + * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples + * specified at pipeline creation time." + */ + if (subpass->has_color_att) { + num_samples = subpass->color_sample_count; + } else { + num_samples = vkms->rasterizationSamples; + } if (vkms->sampleShadingEnable) { - ps_iter_samples = ceil(vkms->minSampleShading * num_samples); + ps_iter_samples = ceilf(vkms->minSampleShading * num_samples); ps_iter_samples = util_next_power_of_two(ps_iter_samples); } return ps_iter_samples; @@ -979,6 +912,30 @@ radv_order_invariant_stencil_state(const VkStencilOpState *state) radv_order_invariant_stencil_op(state->failOp)); } +static bool +radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo *pCreateInfo) +{ + VkDynamicState ds_states[] = { + VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT, + VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT, + VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT, + VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT, + VK_DYNAMIC_STATE_STENCIL_OP_EXT, + }; + + if (pCreateInfo->pDynamicState) { + uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount; + for (uint32_t i = 0; i < count; i++) { + for (uint32_t j = 0; j < ARRAY_SIZE(ds_states); j++) { + if (pCreateInfo->pDynamicState->pDynamicStates[i] == ds_states[j]) + return true; + } + } + } + + return false; +} + static bool radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline, struct radv_blend_state *blend, @@ -986,13 +943,22 @@ radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline, { RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; + const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo); + const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo); unsigned colormask = blend->cb_target_enabled_4bit; if (!pipeline->device->physical_device->out_of_order_rast_allowed) return false; /* Be conservative if a logic operation is enabled with color buffers. */ - if (colormask && pCreateInfo->pColorBlendState->logicOpEnable) + if (colormask && vkblend && vkblend->logicOpEnable) + return false; + + /* Be conservative if an extended dynamic depth/stencil state is + * enabled because the driver can't update out-of-order rasterization + * dynamically. + */ + if (radv_pipeline_has_dynamic_ds_states(pCreateInfo)) return false; /* Default depth/stencil invariance when no attachment is bound. */ @@ -1000,10 +966,7 @@ radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline, .zs = true, .pass_set = true }; - if (pCreateInfo->pDepthStencilState && - subpass->depth_stencil_attachment) { - const VkPipelineDepthStencilStateCreateInfo *vkds = - pCreateInfo->pDepthStencilState; + if (vkds) { struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment; bool has_stencil = vk_format_is_stencil(attachment->format); @@ -1052,8 +1015,8 @@ radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline, * except when early Z/S tests are requested. */ if (ps && - ps->info.info.ps.writes_memory && - ps->info.fs.early_fragment_test && + ps->info.ps.writes_memory && + ps->info.ps.early_fragment_test && !dsa_order_invariant.pass_set) return false; @@ -1085,27 +1048,57 @@ radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline, return true; } +static const VkConservativeRasterizationModeEXT +radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo) +{ + const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster = + vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT); + + if (!conservative_raster) + return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT; + return conservative_raster->conservativeRasterizationMode; +} + static void radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, struct radv_blend_state *blend, const VkGraphicsPipelineCreateInfo *pCreateInfo) { - const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState; + const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo); struct radv_multisample_state *ms = &pipeline->graphics.ms; unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes; + const VkConservativeRasterizationModeEXT mode = + radv_get_conservative_raster_mode(pCreateInfo->pRasterizationState); bool out_of_order_rast = false; int ps_iter_samples = 1; uint32_t mask = 0xffff; - if (vkms) + if (vkms) { ms->num_samples = vkms->rasterizationSamples; - else - ms->num_samples = 1; - if (vkms) - ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms); - if (vkms && !vkms->sampleShadingEnable && pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.force_persample) { - ps_iter_samples = ms->num_samples; + /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading: + * + * "Sample shading is enabled for a graphics pipeline: + * + * - If the interface of the fragment shader entry point of the + * graphics pipeline includes an input variable decorated + * with SampleId or SamplePosition. In this case + * minSampleShadingFactor takes the value 1.0. + * - Else if the sampleShadingEnable member of the + * VkPipelineMultisampleStateCreateInfo structure specified + * when creating the graphics pipeline is set to VK_TRUE. In + * this case minSampleShadingFactor takes the value of + * VkPipelineMultisampleStateCreateInfo::minSampleShading. + * + * Otherwise, sample shading is considered disabled." + */ + if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) { + ps_iter_samples = ms->num_samples; + } else { + ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo); + } + } else { + ms->num_samples = 1; } const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order = @@ -1123,12 +1116,20 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo); } - ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1); ms->pa_sc_aa_config = 0; ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_INCOHERENT_EQAA_READS(1) | S_028804_INTERPOLATE_COMP_Z(1) | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1); + + /* Adjust MSAA state if conservative rasterization is enabled. */ + if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) { + ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1); + + ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) | + S_028804_OVERRASTERIZATION_AMOUNT(4); + } + ms->pa_sc_mode_cntl_1 = S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) | @@ -1144,18 +1145,39 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) | S_028A48_VPORT_SCISSOR_ENABLE(1); + const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line = + vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, + PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT); + if (rast_line) { + ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable); + if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) { + /* From the Vulkan spec 1.1.129: + * + * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines + * are being rasterized, sample locations may all be + * treated as being at the pixel center (this may + * affect attribute and depth interpolation)." + */ + ms->num_samples = 1; + } + } + if (ms->num_samples > 1) { + RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); + struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass]; + uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples; unsigned log_samples = util_logbase2(ms->num_samples); + unsigned log_z_samples = util_logbase2(z_samples); unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples); ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1); - ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */ - ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) | + ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) | S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) | S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) | S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples); ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) | S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) | - S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */ + S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */ + S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3); ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); if (ps_iter_samples > 1) pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2); @@ -1191,38 +1213,6 @@ radv_prim_can_use_guardband(enum VkPrimitiveTopology topology) } } -static uint32_t -si_translate_prim(enum VkPrimitiveTopology topology) -{ - switch (topology) { - case VK_PRIMITIVE_TOPOLOGY_POINT_LIST: - return V_008958_DI_PT_POINTLIST; - case VK_PRIMITIVE_TOPOLOGY_LINE_LIST: - return V_008958_DI_PT_LINELIST; - case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP: - return V_008958_DI_PT_LINESTRIP; - case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST: - return V_008958_DI_PT_TRILIST; - case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP: - return V_008958_DI_PT_TRISTRIP; - case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN: - return V_008958_DI_PT_TRIFAN; - case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: - return V_008958_DI_PT_LINELIST_ADJ; - case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: - return V_008958_DI_PT_LINESTRIP_ADJ; - case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: - return V_008958_DI_PT_TRILIST_ADJ; - case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY: - return V_008958_DI_PT_TRISTRIP_ADJ; - case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST: - return V_008958_DI_PT_PATCH; - default: - assert(0); - return 0; - } -} - static uint32_t si_conv_gl_prim_to_gs_out(unsigned gl_prim) { @@ -1274,8 +1264,10 @@ static unsigned radv_dynamic_state_mask(VkDynamicState state) { switch(state) { case VK_DYNAMIC_STATE_VIEWPORT: + case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT: return RADV_DYNAMIC_VIEWPORT; case VK_DYNAMIC_STATE_SCISSOR: + case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT: return RADV_DYNAMIC_SCISSOR; case VK_DYNAMIC_STATE_LINE_WIDTH: return RADV_DYNAMIC_LINE_WIDTH; @@ -1295,6 +1287,28 @@ static unsigned radv_dynamic_state_mask(VkDynamicState state) return RADV_DYNAMIC_DISCARD_RECTANGLE; case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT: return RADV_DYNAMIC_SAMPLE_LOCATIONS; + case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT: + return RADV_DYNAMIC_LINE_STIPPLE; + case VK_DYNAMIC_STATE_CULL_MODE_EXT: + return RADV_DYNAMIC_CULL_MODE; + case VK_DYNAMIC_STATE_FRONT_FACE_EXT: + return RADV_DYNAMIC_FRONT_FACE; + case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT: + return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY; + case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT: + return RADV_DYNAMIC_DEPTH_TEST_ENABLE; + case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT: + return RADV_DYNAMIC_DEPTH_WRITE_ENABLE; + case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT: + return RADV_DYNAMIC_DEPTH_COMPARE_OP; + case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT: + return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE; + case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT: + return RADV_DYNAMIC_STENCIL_TEST_ENABLE; + case VK_DYNAMIC_STATE_STENCIL_OP_EXT: + return RADV_DYNAMIC_STENCIL_OP; + case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT: + return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE; default: unreachable("Unhandled dynamic state"); } @@ -1304,10 +1318,13 @@ static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreat { uint32_t states = RADV_DYNAMIC_ALL; - /* If rasterization is disabled we do not care about any of the dynamic states, - * since they are all rasterization related only. */ + /* If rasterization is disabled we do not care about any of the + * dynamic states, since they are all rasterization related only, + * except primitive topology and vertex binding stride. + */ if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable) - return 0; + return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY | + RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE; if (!pCreateInfo->pRasterizationState->depthBiasEnable) states &= ~RADV_DYNAMIC_DEPTH_BIAS; @@ -1330,20 +1347,51 @@ static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreat PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT)) states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS; + if (!pCreateInfo->pRasterizationState || + !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, + PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT)) + states &= ~RADV_DYNAMIC_LINE_STIPPLE; + /* TODO: blend constants & line width. */ return states; } - static void -radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, - const VkGraphicsPipelineCreateInfo *pCreateInfo) +radv_pipeline_init_input_assembly_state(struct radv_pipeline *pipeline, + const VkGraphicsPipelineCreateInfo *pCreateInfo, + const struct radv_graphics_pipeline_create_info *extra) { - uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo); - uint32_t states = needed_states; - RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); - struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass]; + const VkPipelineInputAssemblyStateCreateInfo *ia_state = pCreateInfo->pInputAssemblyState; + struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL]; + struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY]; + + pipeline->graphics.prim_restart_enable = !!ia_state->primitiveRestartEnable; + pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(ia_state->topology); + + if (radv_pipeline_has_gs(pipeline)) { + if (si_conv_gl_prim_to_gs_out(gs->info.gs.output_prim) == V_028A6C_OUTPRIM_TYPE_TRISTRIP) + pipeline->graphics.can_use_guardband = true; + } else if (radv_pipeline_has_tess(pipeline)) { + if (!tes->info.tes.point_mode && + si_conv_gl_prim_to_gs_out(tes->info.tes.primitive_mode) == V_028A6C_OUTPRIM_TYPE_TRISTRIP) + pipeline->graphics.can_use_guardband = true; + } + + if (extra && extra->use_rectlist) { + pipeline->graphics.can_use_guardband = true; + } +} + +static void +radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, + const VkGraphicsPipelineCreateInfo *pCreateInfo, + const struct radv_graphics_pipeline_create_info *extra) +{ + uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo); + uint32_t states = needed_states; + RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); + struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass]; pipeline->dynamic_state = default_dynamic_state; pipeline->graphics.needed_dynamic_state = needed_states; @@ -1404,6 +1452,24 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, pCreateInfo->pColorBlendState->blendConstants, 4); } + if (states & RADV_DYNAMIC_CULL_MODE) { + dynamic->cull_mode = + pCreateInfo->pRasterizationState->cullMode; + } + + if (states & RADV_DYNAMIC_FRONT_FACE) { + dynamic->front_face = + pCreateInfo->pRasterizationState->frontFace; + } + + if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) { + dynamic->primitive_topology = + si_translate_prim(pCreateInfo->pInputAssemblyState->topology); + if (extra && extra->use_rectlist) { + dynamic->primitive_topology = V_008958_DI_PT_RECTLIST; + } + } + /* If there is no depthstencil attachment, then don't read * pDepthStencilState. The Vulkan spec states that pDepthStencilState may * be NULL in this case. Even if pDepthStencilState is non-NULL, there is @@ -1446,6 +1512,51 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, dynamic->stencil_reference.back = pCreateInfo->pDepthStencilState->back.reference; } + + if (states & RADV_DYNAMIC_DEPTH_TEST_ENABLE) { + dynamic->depth_test_enable = + pCreateInfo->pDepthStencilState->depthTestEnable; + } + + if (states & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) { + dynamic->depth_write_enable = + pCreateInfo->pDepthStencilState->depthWriteEnable; + } + + if (states & RADV_DYNAMIC_DEPTH_COMPARE_OP) { + dynamic->depth_compare_op = + pCreateInfo->pDepthStencilState->depthCompareOp; + } + + if (states & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) { + dynamic->depth_bounds_test_enable = + pCreateInfo->pDepthStencilState->depthBoundsTestEnable; + } + + if (states & RADV_DYNAMIC_STENCIL_TEST_ENABLE) { + dynamic->stencil_test_enable = + pCreateInfo->pDepthStencilState->stencilTestEnable; + } + + if (states & RADV_DYNAMIC_STENCIL_OP) { + dynamic->stencil_op.front.compare_op = + pCreateInfo->pDepthStencilState->front.compareOp; + dynamic->stencil_op.front.fail_op = + pCreateInfo->pDepthStencilState->front.failOp; + dynamic->stencil_op.front.pass_op = + pCreateInfo->pDepthStencilState->front.passOp; + dynamic->stencil_op.front.depth_fail_op = + pCreateInfo->pDepthStencilState->front.depthFailOp; + + dynamic->stencil_op.back.compare_op = + pCreateInfo->pDepthStencilState->back.compareOp; + dynamic->stencil_op.back.fail_op = + pCreateInfo->pDepthStencilState->back.failOp; + dynamic->stencil_op.back.pass_op = + pCreateInfo->pDepthStencilState->back.passOp; + dynamic->stencil_op.back.depth_fail_op = + pCreateInfo->pDepthStencilState->back.depthFailOp; + } } const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info = @@ -1482,26 +1593,39 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, } } + const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info = + vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, + PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT); + if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) { + dynamic->line_stipple.factor = rast_line_info->lineStippleFactor; + dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern; + } + + if (!(states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE)) + pipeline->graphics.uses_dynamic_stride = true; + pipeline->dynamic_state.mask = states; } -static struct radv_gs_state -calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo, - const struct radv_pipeline *pipeline) +static void +gfx9_get_gs_info(const struct radv_pipeline_key *key, + const struct radv_pipeline *pipeline, + nir_shader **nir, + struct radv_shader_info *infos, + struct gfx9_gs_info *out) { - struct radv_gs_state gs = {0}; - struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info; + struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY]; struct radv_es_output_info *es_info; if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) - es_info = radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info; + es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info; else - es_info = radv_pipeline_has_tess(pipeline) ? - &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.es_info : - &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.es_info; + es_info = nir[MESA_SHADER_TESS_CTRL] ? + &infos[MESA_SHADER_TESS_EVAL].tes.es_info : + &infos[MESA_SHADER_VERTEX].vs.es_info; unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1); bool uses_adjacency; - switch(pCreateInfo->pInputAssemblyState->topology) { + switch(key->topology) { case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: @@ -1596,15 +1720,13 @@ calculate_gs_info(const VkGraphicsPipelineCreateInfo *pCreateInfo, uint32_t gs_prims_per_subgroup = gs_prims; uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations; uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out; - gs.lds_size = align(esgs_lds_size, 128) / 128; - gs.vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) | + out->lds_size = align(esgs_lds_size, 128) / 128; + out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) | S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) | S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup); - gs.vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup); - gs.vgt_esgs_ring_itemsize = esgs_itemsize; + out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup); + out->vgt_esgs_ring_itemsize = esgs_itemsize; assert(max_prims_per_subgroup <= max_out_prims); - - return gs; } static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts, @@ -1617,21 +1739,20 @@ static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts } static unsigned -radv_get_num_input_vertices(struct radv_pipeline *pipeline) +radv_get_num_input_vertices(nir_shader **nir) { - if (radv_pipeline_has_gs(pipeline)) { - struct radv_shader_variant *gs = - radv_get_shader(pipeline, MESA_SHADER_GEOMETRY); + if (nir[MESA_SHADER_GEOMETRY]) { + nir_shader *gs = nir[MESA_SHADER_GEOMETRY]; return gs->info.gs.vertices_in; } - if (radv_pipeline_has_tess(pipeline)) { - struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL); + if (nir[MESA_SHADER_TESS_CTRL]) { + nir_shader *tes = nir[MESA_SHADER_TESS_EVAL]; - if (tes->info.tes.point_mode) + if (tes->info.tess.point_mode) return 1; - if (tes->info.tes.primitive_mode == GL_ISOLINES) + if (tes->info.tess.primitive_mode == GL_ISOLINES) return 2; return 3; } @@ -1639,21 +1760,23 @@ radv_get_num_input_vertices(struct radv_pipeline *pipeline) return 3; } -static struct radv_ngg_state -calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo, - struct radv_pipeline *pipeline) +static void +gfx10_get_ngg_info(const struct radv_pipeline_key *key, + struct radv_pipeline *pipeline, + nir_shader **nir, + struct radv_shader_info *infos, + struct gfx10_ngg_info *ngg) { - struct radv_ngg_state ngg = {0}; - struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info; + struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY]; struct radv_es_output_info *es_info = - radv_pipeline_has_tess(pipeline) ? &gs_info->tes.es_info : &gs_info->vs.es_info; - unsigned gs_type = radv_pipeline_has_gs(pipeline) ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX; - unsigned max_verts_per_prim = radv_get_num_input_vertices(pipeline); + nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info; + unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX; + unsigned max_verts_per_prim = radv_get_num_input_vertices(nir); unsigned min_verts_per_prim = gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1; - unsigned gs_num_invocations = radv_pipeline_has_gs(pipeline) ? MAX2(gs_info->gs.invocations, 1) : 1; + unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1; bool uses_adjacency; - switch(pCreateInfo->pInputAssemblyState->topology) { + switch(key->topology) { case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY: case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY: case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY: @@ -1669,17 +1792,11 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo, /* We can't allow using the whole LDS, because GS waves compete with * other shader stages for LDS space. * - * Streamout can increase the ESGS buffer size later on, so be more - * conservative with streamout and use 4K dwords. This may be suboptimal. - * - * Otherwise, use the limit of 7K dwords. The reason is that we need - * to leave some headroom for the max_esverts increase at the end. - * * TODO: We should really take the shader's internal LDS use into * account. The linker will fail if the size is greater than * 8K dwords. */ - const unsigned max_lds_size = (0 /*gs_info->info.so.num_outputs*/ ? 4 : 7) * 1024 - 128; + const unsigned max_lds_size = 8 * 1024 - 768; const unsigned target_lds_size = max_lds_size; unsigned esvert_lds_size = 0; unsigned gsprim_lds_size = 0; @@ -1720,12 +1837,22 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo, esvert_lds_size = es_info->esgs_itemsize / 4; gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim; } else { - /* TODO: This needs to be adjusted once LDS use for compaction - * after culling is implemented. */ - /* - if (es_info->info.so.num_outputs) - esvert_lds_size = 4 * es_info->info.so.num_outputs + 1; - */ + /* VS and TES. */ + /* LDS size for passing data from GS to ES. */ + struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL] + ? &infos[MESA_SHADER_TESS_EVAL].so + : &infos[MESA_SHADER_VERTEX].so; + + if (so_info->num_outputs) + esvert_lds_size = 4 * so_info->num_outputs + 1; + + /* GS stores Primitive IDs (one DWORD) into LDS at the address + * corresponding to the ES thread of the provoking vertex. All + * ES threads load and export PrimitiveID for their thread. + */ + if (!nir[MESA_SHADER_TESS_CTRL] && + infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id) + esvert_lds_size = MAX2(esvert_lds_size, 1); } unsigned max_gsprims = max_gsprims_base; @@ -1763,9 +1890,18 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo, /* Round up towards full wave sizes for better ALU utilization. */ if (!max_vert_out_per_gs_instance) { - const unsigned wavesize = 64; unsigned orig_max_esverts; unsigned orig_max_gsprims; + unsigned wavesize; + + if (gs_type == MESA_SHADER_GEOMETRY) { + wavesize = gs_info->wave_size; + } else { + wavesize = nir[MESA_SHADER_TESS_CTRL] + ? infos[MESA_SHADER_TESS_EVAL].wave_size + : infos[MESA_SHADER_VERTEX].wave_size; + } + do { orig_max_esverts = max_esverts; orig_max_gsprims = max_gsprims; @@ -1812,28 +1948,28 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo, * this check passes, there is enough space for a full primitive without * vertex reuse. */ - ngg.hw_max_esverts = max_esverts - max_verts_per_prim + 1; - ngg.max_gsprims = max_gsprims; - ngg.max_out_verts = max_out_vertices; - ngg.prim_amp_factor = prim_amp_factor; - ngg.max_vert_out_per_gs_instance = max_vert_out_per_gs_instance; - ngg.ngg_emit_size = max_gsprims * gsprim_lds_size; + ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1; + ngg->max_gsprims = max_gsprims; + ngg->max_out_verts = max_out_vertices; + ngg->prim_amp_factor = prim_amp_factor; + ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance; + ngg->ngg_emit_size = max_gsprims * gsprim_lds_size; + ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size; if (gs_type == MESA_SHADER_GEOMETRY) { - ngg.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4; + ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4; } else { - ngg.vgt_esgs_ring_itemsize = 1; + ngg->vgt_esgs_ring_itemsize = 1; } - pipeline->graphics.esgs_ring_size = 4 * max_esverts * esvert_lds_size; + pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size; - assert(ngg.hw_max_esverts >= 24); /* HW limitation */ - - return ngg; + assert(ngg->hw_max_esverts >= 24); /* HW limitation */ } static void -calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_state *gs) +calculate_gs_ring_sizes(struct radv_pipeline *pipeline, + const struct gfx9_gs_info *gs) { struct radv_device *device = pipeline->device; unsigned num_se = device->physical_device->rad_info.max_se; @@ -1847,7 +1983,7 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_sta unsigned alignment = 256 * num_se; /* The maximum size is 63.999 MB per SE. */ unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se; - struct radv_shader_variant_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info; + struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info; /* Calculate the minimum size. */ unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse * @@ -1868,23 +2004,6 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_sta pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size); } -static void si_multiwave_lds_size_workaround(struct radv_device *device, - unsigned *lds_size) -{ - /* If tessellation is all offchip and on-chip GS isn't used, this - * workaround is not needed. - */ - return; - - /* SPI barrier management bug: - * Make sure we have at least 4k of LDS in use to avoid the bug. - * It applies to workgroup sizes of more than one wavefront. - */ - if (device->physical_device->rad_info.family == CHIP_BONAIRE || - device->physical_device->rad_info.family == CHIP_KABINI) - *lds_size = MAX2(*lds_size, 8); -} - struct radv_shader_variant * radv_get_shader(struct radv_pipeline *pipeline, gl_shader_stage stage) @@ -1907,119 +2026,6 @@ radv_get_shader(struct radv_pipeline *pipeline, return pipeline->shaders[stage]; } -static struct radv_tessellation_state -calculate_tess_state(struct radv_pipeline *pipeline, - const VkGraphicsPipelineCreateInfo *pCreateInfo) -{ - unsigned num_tcs_input_cp; - unsigned num_tcs_output_cp; - unsigned lds_size; - unsigned num_patches; - struct radv_tessellation_state tess = {0}; - - num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints; - num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT - num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; - - lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size; - - if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) { - assert(lds_size <= 65536); - lds_size = align(lds_size, 512) / 512; - } else { - assert(lds_size <= 32768); - lds_size = align(lds_size, 256) / 256; - } - si_multiwave_lds_size_workaround(pipeline->device, &lds_size); - - tess.lds_size = lds_size; - - tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) | - S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) | - S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp); - tess.num_patches = num_patches; - - struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL); - unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0; - - switch (tes->info.tes.primitive_mode) { - case GL_TRIANGLES: - type = V_028B6C_TESS_TRIANGLE; - break; - case GL_QUADS: - type = V_028B6C_TESS_QUAD; - break; - case GL_ISOLINES: - type = V_028B6C_TESS_ISOLINE; - break; - } - - switch (tes->info.tes.spacing) { - case TESS_SPACING_EQUAL: - partitioning = V_028B6C_PART_INTEGER; - break; - case TESS_SPACING_FRACTIONAL_ODD: - partitioning = V_028B6C_PART_FRAC_ODD; - break; - case TESS_SPACING_FRACTIONAL_EVEN: - partitioning = V_028B6C_PART_FRAC_EVEN; - break; - default: - break; - } - - bool ccw = tes->info.tes.ccw; - const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state = - vk_find_struct_const(pCreateInfo->pTessellationState, - PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO); - - if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT) - ccw = !ccw; - - if (tes->info.tes.point_mode) - topology = V_028B6C_OUTPUT_POINT; - else if (tes->info.tes.primitive_mode == GL_ISOLINES) - topology = V_028B6C_OUTPUT_LINE; - else if (ccw) - topology = V_028B6C_OUTPUT_TRIANGLE_CCW; - else - topology = V_028B6C_OUTPUT_TRIANGLE_CW; - - if (pipeline->device->has_distributed_tess) { - if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI || - pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10) - distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS; - else - distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS; - } else - distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST; - - tess.tf_param = S_028B6C_TYPE(type) | - S_028B6C_PARTITIONING(partitioning) | - S_028B6C_TOPOLOGY(topology) | - S_028B6C_DISTRIBUTION_MODE(distribution_mode); - - return tess; -} - -static const struct radv_prim_vertex_count prim_size_table[] = { - [V_008958_DI_PT_NONE] = {0, 0}, - [V_008958_DI_PT_POINTLIST] = {1, 1}, - [V_008958_DI_PT_LINELIST] = {2, 2}, - [V_008958_DI_PT_LINESTRIP] = {2, 1}, - [V_008958_DI_PT_TRILIST] = {3, 3}, - [V_008958_DI_PT_TRIFAN] = {3, 1}, - [V_008958_DI_PT_TRISTRIP] = {3, 1}, - [V_008958_DI_PT_LINELIST_ADJ] = {4, 4}, - [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1}, - [V_008958_DI_PT_TRILIST_ADJ] = {6, 6}, - [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2}, - [V_008958_DI_PT_RECTLIST] = {3, 3}, - [V_008958_DI_PT_LINELOOP] = {2, 1}, - [V_008958_DI_PT_POLYGON] = {3, 1}, - [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0}, -}; - static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline) { if (radv_pipeline_has_gs(pipeline)) @@ -2086,9 +2092,9 @@ radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders) radv_optimize_nir(ordered_shaders[i - 1], false, false); nir_remove_dead_variables(ordered_shaders[i], - nir_var_shader_out); + nir_var_shader_out, NULL); nir_remove_dead_variables(ordered_shaders[i - 1], - nir_var_shader_in); + nir_var_shader_in, NULL); bool progress = nir_remove_unused_varyings(ordered_shaders[i], ordered_shaders[i - 1]); @@ -2112,6 +2118,54 @@ radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders) } } +static void +radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders, + struct radv_shader_info infos[MESA_SHADER_STAGES]) +{ + bool has_tess = shaders[MESA_SHADER_TESS_CTRL]; + bool has_gs = shaders[MESA_SHADER_GEOMETRY]; + + if (!has_tess && !has_gs) + return; + + unsigned vs_info_idx = MESA_SHADER_VERTEX; + unsigned tes_info_idx = MESA_SHADER_TESS_EVAL; + + if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { + /* These are merged into the next stage */ + vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY; + tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL; + } + + if (has_tess) { + nir_linked_io_var_info vs2tcs = + nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]); + nir_linked_io_var_info tcs2tes = + nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]); + + infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars; + infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars; + infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars; + infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars; + infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars; + infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars; + + if (has_gs) { + nir_linked_io_var_info tes2gs = + nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]); + + infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars; + infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars; + } + } else if (has_gs) { + nir_linked_io_var_info vs2gs = + nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]); + + infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars; + infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars; + } +} + static uint32_t radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state, uint32_t attrib_binding) @@ -2130,9 +2184,10 @@ radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state, static struct radv_pipeline_key radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo, - const struct radv_blend_state *blend, - bool has_view_index) + const struct radv_blend_state *blend) { + RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); + struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; const VkPipelineVertexInputStateCreateInfo *input_state = pCreateInfo->pVertexInputState; const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state = @@ -2144,7 +2199,7 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline, if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT) key.optimisations_disabled = 1; - key.has_multiview_view_index = has_view_index; + key.has_multiview_view_index = !!subpass->view_mask; uint32_t binding_input_rate = 0; uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS]; @@ -2232,25 +2287,43 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline, } } - if (pCreateInfo->pTessellationState) - key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints; - + const VkPipelineTessellationStateCreateInfo *tess = + radv_pipeline_get_tessellation_state(pCreateInfo); + if (tess) + key.tess_input_vertices = tess->patchControlPoints; - if (pCreateInfo->pMultisampleState && - pCreateInfo->pMultisampleState->rasterizationSamples > 1) { - uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples; - uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState); + const VkPipelineMultisampleStateCreateInfo *vkms = + radv_pipeline_get_multisample_state(pCreateInfo); + if (vkms && vkms->rasterizationSamples > 1) { + uint32_t num_samples = vkms->rasterizationSamples; + uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo); key.num_samples = num_samples; key.log2_ps_iter_samples = util_logbase2(ps_iter_samples); } key.col_format = blend->spi_shader_col_format; - if (pipeline->device->physical_device->rad_info.chip_class < GFX8) - radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10); + key.is_dual_src = blend->mrt0_is_dual_src; + if (pipeline->device->physical_device->rad_info.chip_class < GFX8) { + key.is_int8 = blend->col_format_is_int8; + key.is_int10 = blend->col_format_is_int10; + } + + if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) + key.topology = pCreateInfo->pInputAssemblyState->topology; return key; } +static bool +radv_nir_stage_uses_xfb(const nir_shader *nir) +{ + nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL); + bool uses_xfb = !!xfb; + + ralloc_free(xfb); + return uses_xfb; +} + static void radv_fill_shader_keys(struct radv_device *device, struct radv_shader_variant_key *keys, @@ -2267,6 +2340,7 @@ radv_fill_shader_keys(struct radv_device *device, keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i]; keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i]; } + keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology); if (nir[MESA_SHADER_TESS_CTRL]) { keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true; @@ -2284,12 +2358,65 @@ radv_fill_shader_keys(struct radv_device *device, keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true; } - if (device->physical_device->rad_info.chip_class >= GFX10) { + if (device->physical_device->use_ngg) { if (nir[MESA_SHADER_TESS_CTRL]) { keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true; } else { keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true; } + + if (nir[MESA_SHADER_TESS_CTRL] && + nir[MESA_SHADER_GEOMETRY] && + nir[MESA_SHADER_GEOMETRY]->info.gs.invocations * + nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) { + /* Fallback to the legacy path if tessellation is + * enabled with extreme geometry because + * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it + * might hang. + */ + keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false; + } + + if (!device->physical_device->use_ngg_gs) { + if (nir[MESA_SHADER_GEOMETRY]) { + if (nir[MESA_SHADER_TESS_CTRL]) + keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false; + else + keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false; + } + } + + gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX; + + for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) { + if (nir[i]) + last_xfb_stage = i; + } + + bool uses_xfb = nir[last_xfb_stage] && + radv_nir_stage_uses_xfb(nir[last_xfb_stage]); + + if (!device->physical_device->use_ngg_streamout && uses_xfb) { + if (nir[MESA_SHADER_TESS_CTRL]) + keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false; + else + keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false; + } + + /* Determine if the pipeline is eligible for the NGG passthrough + * mode. It can't be enabled for geometry shaders, for NGG + * streamout or for vertex shaders that export the primitive ID + * (this is checked later because we don't have the info here.) + */ + if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) { + if (nir[MESA_SHADER_TESS_CTRL] && + keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) { + keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true; + } else if (nir[MESA_SHADER_VERTEX] && + keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) { + keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true; + } + } } for(int i = 0; i < MESA_SHADER_STAGES; ++i) @@ -2300,6 +2427,181 @@ radv_fill_shader_keys(struct radv_device *device, keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10; keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples; keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples; + keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src; + + if (nir[MESA_SHADER_COMPUTE]) { + keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size; + } +} + +static uint8_t +radv_get_wave_size(struct radv_device *device, + const VkPipelineShaderStageCreateInfo *pStage, + gl_shader_stage stage, + const struct radv_shader_variant_key *key) +{ + if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg) + return 64; + else if (stage == MESA_SHADER_COMPUTE) { + if (key->cs.subgroup_size) { + /* Return the required subgroup size if specified. */ + return key->cs.subgroup_size; + } + return device->physical_device->cs_wave_size; + } + else if (stage == MESA_SHADER_FRAGMENT) + return device->physical_device->ps_wave_size; + else + return device->physical_device->ge_wave_size; +} + +static uint8_t +radv_get_ballot_bit_size(struct radv_device *device, + const VkPipelineShaderStageCreateInfo *pStage, + gl_shader_stage stage, + const struct radv_shader_variant_key *key) +{ + if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size) + return key->cs.subgroup_size; + return 64; +} + +static void +radv_fill_shader_info(struct radv_pipeline *pipeline, + const VkPipelineShaderStageCreateInfo **pStages, + struct radv_shader_variant_key *keys, + struct radv_shader_info *infos, + nir_shader **nir) +{ + unsigned active_stages = 0; + unsigned filled_stages = 0; + + for (int i = 0; i < MESA_SHADER_STAGES; i++) { + if (nir[i]) + active_stages |= (1 << i); + } + + if (nir[MESA_SHADER_FRAGMENT]) { + radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]); + radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT], + pipeline->layout, + &keys[MESA_SHADER_FRAGMENT], + &infos[MESA_SHADER_FRAGMENT], + pipeline->device->physical_device->use_llvm); + + /* TODO: These are no longer used as keys we should refactor this */ + keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id = + infos[MESA_SHADER_FRAGMENT].ps.prim_id_input; + keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id = + infos[MESA_SHADER_FRAGMENT].ps.layer_input; + keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists = + !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls; + keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index = + infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input; + keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id = + infos[MESA_SHADER_FRAGMENT].ps.prim_id_input; + keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id = + infos[MESA_SHADER_FRAGMENT].ps.layer_input; + keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists = + !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls; + keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index = + infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input; + + /* NGG passthrough mode can't be enabled for vertex shaders + * that export the primitive ID. + * + * TODO: I should really refactor the keys logic. + */ + if (nir[MESA_SHADER_VERTEX] && + keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) { + keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false; + } + + filled_stages |= (1 << MESA_SHADER_FRAGMENT); + } + + if (nir[MESA_SHADER_TESS_CTRL]) { + infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read = + nir[MESA_SHADER_TESS_EVAL]->info.inputs_read; + infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read = + nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read; + } + + if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 && + nir[MESA_SHADER_TESS_CTRL]) { + struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]}; + struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL]; + key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs; + + radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]); + + for (int i = 0; i < 2; i++) { + radv_nir_shader_info_pass(combined_nir[i], + pipeline->layout, &key, + &infos[MESA_SHADER_TESS_CTRL], + pipeline->device->physical_device->use_llvm); + } + + keys[MESA_SHADER_TESS_EVAL].tes.num_patches = + infos[MESA_SHADER_TESS_CTRL].tcs.num_patches; + keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = + util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written); + + filled_stages |= (1 << MESA_SHADER_VERTEX); + filled_stages |= (1 << MESA_SHADER_TESS_CTRL); + } + + if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 && + nir[MESA_SHADER_GEOMETRY]) { + gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; + struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]}; + + radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]); + + for (int i = 0; i < 2; i++) { + radv_nir_shader_info_pass(combined_nir[i], + pipeline->layout, + &keys[pre_stage], + &infos[MESA_SHADER_GEOMETRY], + pipeline->device->physical_device->use_llvm); + } + + filled_stages |= (1 << pre_stage); + filled_stages |= (1 << MESA_SHADER_GEOMETRY); + } + + active_stages ^= filled_stages; + while (active_stages) { + int i = u_bit_scan(&active_stages); + + if (i == MESA_SHADER_TESS_CTRL) { + keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = + util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written); + } + + if (i == MESA_SHADER_TESS_EVAL) { + keys[MESA_SHADER_TESS_EVAL].tes.num_patches = + infos[MESA_SHADER_TESS_CTRL].tcs.num_patches; + keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = + util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written); + } + + radv_nir_shader_info_init(&infos[i]); + radv_nir_shader_info_pass(nir[i], pipeline->layout, + &keys[i], &infos[i], pipeline->device->physical_device->use_llvm); + } + + for (int i = 0; i < MESA_SHADER_STAGES; i++) { + if (nir[i]) { + infos[i].wave_size = + radv_get_wave_size(pipeline->device, pStages[i], + i, &keys[i]); + infos[i].ballot_bit_size = + radv_get_ballot_bit_size(pipeline->device, + pStages[i], i, + &keys[i]); + } + } } static void @@ -2379,23 +2681,26 @@ void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit) (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0); } -static -void radv_create_shaders(struct radv_pipeline *pipeline, - struct radv_device *device, - struct radv_pipeline_cache *cache, - const struct radv_pipeline_key *key, - const VkPipelineShaderStageCreateInfo **pStages, - const VkPipelineCreateFlags flags, - VkPipelineCreationFeedbackEXT *pipeline_feedback, - VkPipelineCreationFeedbackEXT **stage_feedbacks) +VkResult radv_create_shaders(struct radv_pipeline *pipeline, + struct radv_device *device, + struct radv_pipeline_cache *cache, + const struct radv_pipeline_key *key, + const VkPipelineShaderStageCreateInfo **pStages, + const VkPipelineCreateFlags flags, + VkPipelineCreationFeedbackEXT *pipeline_feedback, + VkPipelineCreationFeedbackEXT **stage_feedbacks) { struct radv_shader_module fs_m = {0}; struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, }; nir_shader *nir[MESA_SHADER_STAGES] = {0}; struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL}; struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}}; + struct radv_shader_info infos[MESA_SHADER_STAGES] = {0}; unsigned char hash[20], gs_copy_hash[20]; - bool use_ngg = device->physical_device->rad_info.chip_class >= GFX10; + bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info; + bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) || + (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) || + device->keep_shader_info; radv_start_feedback(pipeline_feedback); @@ -2416,18 +2721,24 @@ void radv_create_shaders(struct radv_pipeline *pipeline, gs_copy_hash[0] ^= 1; bool found_in_application_cache = true; - if (modules[MESA_SHADER_GEOMETRY] && !use_ngg) { + if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) { struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0}; radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants, &found_in_application_cache); pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY]; } - if (radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders, + if (!keep_executable_info && !keep_statistic_info && + radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders, &found_in_application_cache) && (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) { radv_stop_feedback(pipeline_feedback, found_in_application_cache); - return; + return VK_SUCCESS; + } + + if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) { + radv_stop_feedback(pipeline_feedback, found_in_application_cache); + return VK_PIPELINE_COMPILE_REQUIRED_EXT; } if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) { @@ -2440,16 +2751,27 @@ void radv_create_shaders(struct radv_pipeline *pipeline, for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) { const VkPipelineShaderStageCreateInfo *stage = pStages[i]; + unsigned subgroup_size = 64, ballot_bit_size = 64; if (!modules[i]) continue; radv_start_feedback(stage_feedbacks[i]); + if (key->compute_subgroup_size) { + /* Only compute shaders currently support requiring a + * specific subgroup size. + */ + assert(i == MESA_SHADER_COMPUTE); + subgroup_size = key->compute_subgroup_size; + ballot_bit_size = key->compute_subgroup_size; + } + nir[i] = radv_shader_compile_to_nir(device, modules[i], stage ? stage->pName : "main", i, stage ? stage->pSpecializationInfo : NULL, - flags, pipeline->layout); + flags, pipeline->layout, + subgroup_size, ballot_bit_size); /* We don't want to alter meta shaders IR directly so clone it * first. @@ -2469,22 +2791,95 @@ void radv_create_shaders(struct radv_pipeline *pipeline, if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) radv_link_shaders(pipeline, nir); + radv_set_linked_driver_locations(pipeline, nir, infos); + for (int i = 0; i < MESA_SHADER_STAGES; ++i) { if (nir[i]) { - NIR_PASS_V(nir[i], nir_lower_bool_to_int32); - NIR_PASS_V(nir[i], nir_lower_non_uniform_access, - nir_lower_non_uniform_ubo_access | - nir_lower_non_uniform_ssbo_access | - nir_lower_non_uniform_texture_access | - nir_lower_non_uniform_image_access); + /* do this again since information such as outputs_read can be out-of-date */ + nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i])); + + if (device->physical_device->use_llvm) { + NIR_PASS_V(nir[i], nir_lower_bool_to_int32); + } else { + NIR_PASS_V(nir[i], nir_lower_non_uniform_access, + nir_lower_non_uniform_ubo_access | + nir_lower_non_uniform_ssbo_access | + nir_lower_non_uniform_texture_access | + nir_lower_non_uniform_image_access); + } } + } - if (radv_can_dump_shader(device, modules[i], false)) + if (nir[MESA_SHADER_FRAGMENT]) + radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]); + + for (int i = 0; i < MESA_SHADER_STAGES; ++i) { + if (radv_can_dump_shader(device, modules[i], false)) nir_print_shader(nir[i], stderr); } radv_fill_shader_keys(device, keys, key, nir); + radv_fill_shader_info(pipeline, pStages, keys, infos, nir); + + if ((nir[MESA_SHADER_VERTEX] && + keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) || + (nir[MESA_SHADER_TESS_EVAL] && + keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) { + struct gfx10_ngg_info *ngg_info; + + if (nir[MESA_SHADER_GEOMETRY]) + ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info; + else if (nir[MESA_SHADER_TESS_CTRL]) + ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info; + else + ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info; + + gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info); + } else if (nir[MESA_SHADER_GEOMETRY]) { + struct gfx9_gs_info *gs_info = + &infos[MESA_SHADER_GEOMETRY].gs_ring_info; + + gfx9_get_gs_info(key, pipeline, nir, infos, gs_info); + } + + if(modules[MESA_SHADER_GEOMETRY]) { + struct radv_shader_binary *gs_copy_binary = NULL; + if (!pipeline->gs_copy_shader && + !radv_pipeline_has_ngg(pipeline)) { + struct radv_shader_info info = {}; + struct radv_shader_variant_key key = {}; + + key.has_multiview_view_index = + keys[MESA_SHADER_GEOMETRY].has_multiview_view_index; + + radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY], + pipeline->layout, &key, + &info, pipeline->device->physical_device->use_llvm); + info.wave_size = 64; /* Wave32 not supported. */ + info.ballot_bit_size = 64; + + pipeline->gs_copy_shader = radv_create_gs_copy_shader( + device, nir[MESA_SHADER_GEOMETRY], &info, + &gs_copy_binary, keep_executable_info, keep_statistic_info, + keys[MESA_SHADER_GEOMETRY].has_multiview_view_index); + } + + if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) { + struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL}; + struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0}; + + binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary; + variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader; + + radv_pipeline_cache_insert_shaders(device, cache, + gs_copy_hash, + variants, + binaries); + } + free(gs_copy_binary); + } + if (nir[MESA_SHADER_FRAGMENT]) { if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) { radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]); @@ -2492,24 +2887,12 @@ void radv_create_shaders(struct radv_pipeline *pipeline, pipeline->shaders[MESA_SHADER_FRAGMENT] = radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1, pipeline->layout, keys + MESA_SHADER_FRAGMENT, + infos + MESA_SHADER_FRAGMENT, + keep_executable_info, keep_statistic_info, &binaries[MESA_SHADER_FRAGMENT]); radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false); } - - /* TODO: These are no longer used as keys we should refactor this */ - keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id = - pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input; - keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id = - pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input; - keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists = - !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls; - keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id = - pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input; - keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id = - pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input; - keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists = - !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.num_input_clips_culls; } if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) { @@ -2522,13 +2905,14 @@ void radv_create_shaders(struct radv_pipeline *pipeline, pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2, pipeline->layout, - &key, &binaries[MESA_SHADER_TESS_CTRL]); + &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info, + keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]); radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false); } modules[MESA_SHADER_VERTEX] = NULL; keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; - keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written); + keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); } if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) { @@ -2540,7 +2924,8 @@ void radv_create_shaders(struct radv_pipeline *pipeline, pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2, pipeline->layout, - &keys[pre_stage] , &binaries[MESA_SHADER_GEOMETRY]); + &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info, + keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]); radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false); } @@ -2550,54 +2935,33 @@ void radv_create_shaders(struct radv_pipeline *pipeline, for (int i = 0; i < MESA_SHADER_STAGES; ++i) { if(modules[i] && !pipeline->shaders[i]) { if (i == MESA_SHADER_TESS_CTRL) { - keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written); + keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written); } if (i == MESA_SHADER_TESS_EVAL) { keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; - keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written); + keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written); } radv_start_feedback(stage_feedbacks[i]); pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1, pipeline->layout, - keys + i, &binaries[i]); + keys + i, infos + i, keep_executable_info, + keep_statistic_info, &binaries[i]); radv_stop_feedback(stage_feedbacks[i], false); } } - if(modules[MESA_SHADER_GEOMETRY] && !use_ngg) { - struct radv_shader_binary *gs_copy_binary = NULL; - if (!pipeline->gs_copy_shader) { - pipeline->gs_copy_shader = radv_create_gs_copy_shader( - device, nir[MESA_SHADER_GEOMETRY], &gs_copy_binary, - keys[MESA_SHADER_GEOMETRY].has_multiview_view_index); - } - - if (pipeline->gs_copy_shader) { - struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL}; - struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0}; - - binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary; - variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader; - - radv_pipeline_cache_insert_shaders(device, cache, - gs_copy_hash, - variants, - binaries); - } - free(gs_copy_binary); + if (!keep_executable_info && !keep_statistic_info) { + radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders, + binaries); } - radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders, - binaries); - for (int i = 0; i < MESA_SHADER_STAGES; ++i) { free(binaries[i]); if (nir[i]) { - if (!pipeline->device->keep_shader_info) - ralloc_free(nir[i]); + ralloc_free(nir[i]); if (radv_can_dump_shader_stats(device, modules[i])) radv_shader_dump_stats(device, @@ -2610,6 +2974,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline, ralloc_free(fs_m.nir); radv_stop_feedback(pipeline_feedback, false); + return VK_SUCCESS; } static uint32_t @@ -2675,7 +3040,7 @@ struct radv_bin_size_entry { }; static VkExtent2D -radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) +radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) { static const struct radv_bin_size_entry color_size_table[][3][9] = { { @@ -2901,7 +3266,8 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr unsigned effective_samples = total_samples; unsigned color_bytes_per_pixel = 0; - const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState; + const VkPipelineColorBlendStateCreateInfo *vkblend = + radv_pipeline_get_color_blend_state(pCreateInfo); if (vkblend) { for (unsigned i = 0; i < subpass->color_count; i++) { if (!vkblend->pAttachments[i].colorWriteMask) @@ -2938,74 +3304,227 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr while(ds_entry[1].bpp <= ds_bytes_per_pixel) ++ds_entry; - extent.width = MIN2(extent.width, ds_entry->extent.width); - extent.height = MIN2(extent.height, ds_entry->extent.height); + if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height) + extent = ds_entry->extent; } return extent; } -static void -radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs, - struct radv_pipeline *pipeline, - const VkGraphicsPipelineCreateInfo *pCreateInfo) +static VkExtent2D +radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) { - if (pipeline->device->physical_device->rad_info.chip_class < GFX9) - return; + RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); + struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; + VkExtent2D extent = {512, 512}; + + const unsigned db_tag_size = 64; + const unsigned db_tag_count = 312; + const unsigned color_tag_size = 1024; + const unsigned color_tag_count = 31; + const unsigned fmask_tag_size = 256; + const unsigned fmask_tag_count = 44; + + const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends; + const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces); + + const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count; + const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count; + const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count; + + const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config); + const unsigned samples_log = util_logbase2_ceil(total_samples); + + unsigned color_bytes_per_pixel = 0; + unsigned fmask_bytes_per_pixel = 0; + + const VkPipelineColorBlendStateCreateInfo *vkblend = + radv_pipeline_get_color_blend_state(pCreateInfo); + if (vkblend) { + for (unsigned i = 0; i < subpass->color_count; i++) { + if (!vkblend->pAttachments[i].colorWriteMask) + continue; + + if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) + continue; + + VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format; + color_bytes_per_pixel += vk_format_get_blocksize(format); + + if (total_samples > 1) { + assert(samples_log <= 3); + const unsigned fmask_array[] = {0, 1, 1, 4}; + fmask_bytes_per_pixel += fmask_array[samples_log]; + } + } + + color_bytes_per_pixel *= total_samples; + } + color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1); + + const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel); + extent.width = 1ull << ((color_pixel_count_log + 1) / 2); + extent.height = 1ull << (color_pixel_count_log / 2); + + if (fmask_bytes_per_pixel) { + const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel); + + const VkExtent2D fmask_extent = (VkExtent2D){ + .width = 1ull << ((fmask_pixel_count_log + 1) / 2), + .height = 1ull << (color_pixel_count_log / 2) + }; + + if (fmask_extent.width * fmask_extent.height < extent.width * extent.height) + extent = fmask_extent; + } + if (subpass->depth_stencil_attachment) { + struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment; + + /* Coefficients taken from AMDVLK */ + unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0; + unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0; + unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples; + + const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel); + + const VkExtent2D db_extent = (VkExtent2D){ + .width = 1ull << ((db_pixel_count_log + 1) / 2), + .height = 1ull << (color_pixel_count_log / 2) + }; + + if (db_extent.width * db_extent.height < extent.width * extent.height) + extent = db_extent; + } + + extent.width = MAX2(extent.width, 128); + extent.height = MAX2(extent.width, 64); + + return extent; +} + +static void +radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs, + struct radv_pipeline *pipeline, + const VkGraphicsPipelineCreateInfo *pCreateInfo) +{ uint32_t pa_sc_binner_cntl_0 = S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) | S_028C44_DISABLE_START_OF_PRIM(1); uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF); - VkExtent2D bin_size = radv_compute_bin_size(pipeline, pCreateInfo); + if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); + struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; + const VkPipelineColorBlendStateCreateInfo *vkblend = + radv_pipeline_get_color_blend_state(pCreateInfo); + unsigned min_bytes_per_pixel = 0; + + if (vkblend) { + for (unsigned i = 0; i < subpass->color_count; i++) { + if (!vkblend->pAttachments[i].colorWriteMask) + continue; + + if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) + continue; + + VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format; + unsigned bytes = vk_format_get_blocksize(format); + if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel) + min_bytes_per_pixel = bytes; + } + } + + pa_sc_binner_cntl_0 = + S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) | + S_028C44_BIN_SIZE_X(0) | + S_028C44_BIN_SIZE_Y(0) | + S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */ + S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */ + S_028C44_DISABLE_START_OF_PRIM(1); + } + + pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0; + pipeline->graphics.binning.db_dfsm_control = db_dfsm_control; +} + +struct radv_binning_settings +radv_get_binning_settings(const struct radv_physical_device *pdev) +{ + struct radv_binning_settings settings; + if (pdev->rad_info.has_dedicated_vram) { + if (pdev->rad_info.num_render_backends > 4) { + settings.context_states_per_bin = 1; + settings.persistent_states_per_bin = 1; + } else { + settings.context_states_per_bin = 3; + settings.persistent_states_per_bin = 8; + } + settings.fpovs_per_batch = 63; + } else { + /* The context states are affected by the scissor bug. */ + settings.context_states_per_bin = 6; + /* 32 causes hangs for RAVEN. */ + settings.persistent_states_per_bin = 16; + settings.fpovs_per_batch = 63; + } + + if (pdev->rad_info.has_gfx9_scissor_bug) + settings.context_states_per_bin = 1; + + return settings; +} + +static void +radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs, + struct radv_pipeline *pipeline, + const VkGraphicsPipelineCreateInfo *pCreateInfo, + const struct radv_blend_state *blend) +{ + if (pipeline->device->physical_device->rad_info.chip_class < GFX9) + return; + + VkExtent2D bin_size; + if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo); + } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) { + bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo); + } else + unreachable("Unhandled generation for binning bin size calculation"); if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) { - unsigned context_states_per_bin; /* allowed range: [1, 6] */ - unsigned persistent_states_per_bin; /* allowed range: [1, 32] */ - unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */ - - switch (pipeline->device->physical_device->rad_info.family) { - case CHIP_VEGA10: - case CHIP_VEGA12: - case CHIP_VEGA20: - context_states_per_bin = 1; - persistent_states_per_bin = 1; - fpovs_per_batch = 63; - break; - case CHIP_RAVEN: - case CHIP_RAVEN2: - context_states_per_bin = 6; - persistent_states_per_bin = 32; - fpovs_per_batch = 63; - break; - default: - unreachable("unhandled family while determining binning state."); + struct radv_binning_settings settings = + radv_get_binning_settings(pipeline->device->physical_device); + + bool disable_start_of_prim = true; + uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF); + + const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; + + if (pipeline->device->dfsm_allowed && ps && + !ps->info.ps.can_discard && + !ps->info.ps.writes_memory && + blend->cb_target_enabled_4bit) { + db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO); + disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0; } - pa_sc_binner_cntl_0 = + const uint32_t pa_sc_binner_cntl_0 = S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) | S_028C44_BIN_SIZE_X(bin_size.width == 16) | S_028C44_BIN_SIZE_Y(bin_size.height == 16) | S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) | S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) | - S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) | - S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) | - S_028C44_DISABLE_START_OF_PRIM(1) | - S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) | + S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) | + S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) | + S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) | + S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1); - } - radeon_set_context_reg(ctx_cs, R_028C44_PA_SC_BINNER_CNTL_0, - pa_sc_binner_cntl_0); - - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { - radeon_set_context_reg(ctx_cs, R_028038_DB_DFSM_CONTROL, - db_dfsm_control); - } else { - radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL, - db_dfsm_control); - } + pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0; + pipeline->graphics.binning.db_dfsm_control = db_dfsm_control; + } else + radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo); } @@ -3015,11 +3534,12 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, const VkGraphicsPipelineCreateInfo *pCreateInfo, const struct radv_graphics_pipeline_create_info *extra) { - const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState; + const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo); RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; + struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; struct radv_render_pass_attachment *attachment = NULL; - uint32_t db_depth_control = 0, db_stencil_control = 0; + uint32_t db_depth_control = 0; uint32_t db_render_control = 0, db_render_override2 = 0; uint32_t db_render_override = 0; @@ -3037,28 +3557,25 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */ db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2); + + if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) + db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2); } if (has_stencil_attachment && vkds && vkds->stencilTestEnable) { db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1); db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp); - db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp)); - db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp)); - db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp)); db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp); - db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp)); - db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp)); - db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp)); } if (attachment && extra) { db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear); db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear); - db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize); - db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace); - db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace); + db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable); + db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable); + db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable); db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear); db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear); } @@ -3066,7 +3583,8 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); - if (!pCreateInfo->pRasterizationState->depthClampEnable) { + if (!pCreateInfo->pRasterizationState->depthClampEnable && + ps->info.ps.writes_z) { /* From VK_EXT_depth_range_unrestricted spec: * * "The behavior described in Primitive Clipping still applies. @@ -3080,12 +3598,11 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1); } - radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control); - radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); - radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control); radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override); radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2); + + pipeline->graphics.db_depth_control = db_depth_control; } static void @@ -3099,7 +3616,7 @@ radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs, radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control); radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask); - if (pipeline->device->physical_device->has_rbplus) { + if (pipeline->device->physical_device->rad_info.has_rbplus) { radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8); radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8); @@ -3114,17 +3631,6 @@ radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs, pipeline->graphics.cb_target_mask = blend->cb_target_mask; } -static const VkConservativeRasterizationModeEXT -radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo) -{ - const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster = - vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT); - - if (!conservative_raster) - return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT; - return conservative_raster->conservativeRasterizationMode; -} - static void radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs, struct radv_pipeline *pipeline, @@ -3149,39 +3655,22 @@ radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs, S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) | S_028810_DX_LINEAR_ATTR_CLIP_ENA(1)); - radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0, - S_0286D4_FLAT_SHADE_ENA(1) | - S_0286D4_PNT_SPRITE_ENA(1) | - S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | - S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | - S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | - S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) | - S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */ - - radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL, - S_028BE4_PIX_CENTER(1) | // TODO verify - S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) | - S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH)); - - radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL, - S_028814_FACE(vkraster->frontFace) | - S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) | - S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) | - S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) | - S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) | - S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) | - S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | - S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | - S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0)); + pipeline->graphics.pa_su_sc_mode_cntl = + S_028814_FACE(vkraster->frontFace) | + S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) | + S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) | + S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) | + S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) | + S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) | + S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | + S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) | + S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0); + + radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, + S_028BDC_DX10_DIAMOND_TEST_ENA(1)); /* Conservative rasterization. */ if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) { - struct radv_multisample_state *ms = &pipeline->graphics.ms; - - ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1); - ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) | - S_028804_OVERRASTERIZATION_AMOUNT(4); - pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) | S_028C4C_POSTZ_AA_MASK_ENABLE(1) | S_028C4C_CENTROID_SAMPLE_OVERRIDE(1); @@ -3220,7 +3709,9 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs, radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]); radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa); + radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0); radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); + radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config); /* The exclusion bits can be set to improve rasterization efficiency * if no sample lies on the pixel boundary (-8 sample offset). It's @@ -3230,6 +3721,12 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs, radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion)); + + /* GFX9: Flush DFSM when the AA mode changes. */ + if (pipeline->device->dfsm_allowed) { + radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); + radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0)); + } } static void @@ -3237,26 +3734,23 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs, struct radv_pipeline *pipeline) { const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); + const struct radv_shader_variant *vs = + pipeline->shaders[MESA_SHADER_TESS_EVAL] ? + pipeline->shaders[MESA_SHADER_TESS_EVAL] : + pipeline->shaders[MESA_SHADER_VERTEX]; unsigned vgt_primitiveid_en = 0; uint32_t vgt_gs_mode = 0; + if (radv_pipeline_has_ngg(pipeline)) + return; + if (radv_pipeline_has_gs(pipeline)) { const struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY]; vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out, pipeline->device->physical_device->rad_info.chip_class); - } else if (radv_pipeline_has_ngg(pipeline)) { - const struct radv_shader_variant *vs = - pipeline->shaders[MESA_SHADER_TESS_EVAL] ? - pipeline->shaders[MESA_SHADER_TESS_EVAL] : - pipeline->shaders[MESA_SHADER_VERTEX]; - bool enable_prim_id = - outinfo->export_prim_id || vs->info.info.uses_prim_id; - - vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(enable_prim_id) | - S_028A84_NGG_DISABLE_PROVOK_REUSE(enable_prim_id); - } else if (outinfo->export_prim_id) { + } else if (outinfo->export_prim_id || vs->info.uses_prim_id) { vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A); vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1); } @@ -3287,9 +3781,17 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, bool misc_vec_ena = outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index; + unsigned spi_vs_out_config, nparams; - radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, - S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1)); + /* VS is required to export at least one param. */ + nparams = MAX2(outinfo->param_exports, 1); + spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1); + + if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0); + } + + radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config); radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT, S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | @@ -3303,12 +3805,6 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, V_02870C_SPI_SHADER_4COMP : V_02870C_SPI_SHADER_NONE)); - radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL, - S_028818_VTX_W0_FMT(1) | - S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) | - S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) | - S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1)); - radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL, S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) | S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) | @@ -3317,6 +3813,7 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs, S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) | S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) | S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) | + S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) | cull_dist_mask << 8 | clip_dist_mask); @@ -3342,9 +3839,9 @@ radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs, static void radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, - struct radv_shader_variant *shader, - const struct radv_tessellation_state *tess) + struct radv_shader_variant *shader) { + unsigned num_lds_blocks = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks; uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; uint32_t rsrc2 = shader->config.rsrc2; @@ -3352,7 +3849,7 @@ radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs, radeon_emit(cs, va >> 8); radeon_emit(cs, S_00B524_MEM_BASE(va >> 40)); - rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size); + rsrc2 |= S_00B52C_LDS_SIZE(num_lds_blocks); if (pipeline->device->physical_device->rad_info.chip_class == GFX7 && pipeline->device->physical_device->rad_info.family != CHIP_HAWAII) radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2); @@ -3366,16 +3863,18 @@ static void radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, - struct radv_shader_variant *shader, - const struct radv_ngg_state *ngg_state) + struct radv_shader_variant *shader) { uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; gl_shader_stage es_type = radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX; + struct radv_shader_variant *es = + es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX]; + const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info; radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2); radeon_emit(cs, va >> 8); - radeon_emit(cs, va >> 40); + radeon_emit(cs, S_00B324_MEM_BASE(va >> 40)); radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2); radeon_emit(cs, shader->config.rsrc1); radeon_emit(cs, shader->config.rsrc2); @@ -3388,10 +3887,25 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, bool misc_vec_ena = outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index; + bool es_enable_prim_id = outinfo->export_prim_id || + (es && es->info.uses_prim_id); bool break_wave_at_eoi = false; + unsigned ge_cntl; + unsigned nparams; + + if (es_type == MESA_SHADER_TESS_EVAL) { + struct radv_shader_variant *gs = + pipeline->shaders[MESA_SHADER_GEOMETRY]; + + if (es_enable_prim_id || (gs && gs->info.uses_prim_id)) + break_wave_at_eoi = true; + } + nparams = MAX2(outinfo->param_exports, 1); radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, - S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1)); + S_0286C4_VS_EXPORT_COUNT(nparams - 1) | + S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0)); + radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT, S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP)); radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT, @@ -3406,11 +3920,6 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, V_02870C_SPI_SHADER_4COMP : V_02870C_SPI_SHADER_NONE)); - radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL, - S_028818_VTX_W0_FMT(1) | - S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) | - S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) | - S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1)); radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL, S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) | S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) | @@ -3419,15 +3928,14 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) | S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) | S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) | + S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) | cull_dist_mask << 8 | clip_dist_mask); - bool vgt_reuse_off = pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 && - pipeline->device->physical_device->rad_info.chip_external_rev == 0x1 && - es_type == MESA_SHADER_TESS_EVAL; + radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, + S_028A84_PRIMITIVEID_EN(es_enable_prim_id) | + S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id)); - radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF, - S_028AB4_REUSE_OFF(vgt_reuse_off)); radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, ngg_state->vgt_esgs_ring_itemsize); @@ -3459,31 +3967,40 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs, */ radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL, S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) && - !radv_pipeline_has_gs(pipeline))); + !radv_pipeline_has_gs(pipeline)) | + /* Reuse for NGG. */ + S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0)); - radeon_set_context_reg(ctx_cs, R_03096C_GE_CNTL, - S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) | - S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) | - S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi)); + ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) | + S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */ + S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi); + + /* Bug workaround for a possible hang with non-tessellation cases. + * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0 + * + * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5 + */ + if (pipeline->device->physical_device->rad_info.chip_class == GFX10 && + !radv_pipeline_has_tess(pipeline) && + ngg_state->hw_max_esverts != 256) { + ge_cntl &= C_03096C_VERT_GRP_SIZE; + + if (ngg_state->hw_max_esverts > 5) { + ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5); + } + } + + radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl); } static void radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs, struct radv_pipeline *pipeline, - struct radv_shader_variant *shader, - const struct radv_tessellation_state *tess) + struct radv_shader_variant *shader) { uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) { - unsigned hs_rsrc2 = shader->config.rsrc2; - - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { - hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size); - } else { - hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size); - } - if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2); radeon_emit(cs, va >> 8); @@ -3496,7 +4013,7 @@ radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs, radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2); radeon_emit(cs, shader->config.rsrc1); - radeon_emit(cs, hs_rsrc2); + radeon_emit(cs, shader->config.rsrc2); } else { radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4); radeon_emit(cs, va >> 8); @@ -3509,9 +4026,7 @@ radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs, static void radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, - struct radv_pipeline *pipeline, - const struct radv_tessellation_state *tess, - const struct radv_ngg_state *ngg) + struct radv_pipeline *pipeline) { struct radv_shader_variant *vs; @@ -3521,11 +4036,11 @@ radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs, return; if (vs->info.vs.as_ls) - radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess); + radv_pipeline_generate_hw_ls(cs, pipeline, vs); else if (vs->info.vs.as_es) radv_pipeline_generate_hw_es(cs, pipeline, vs); else if (vs->info.is_ngg) - radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs, ngg); + radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs); else radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs); } @@ -3533,13 +4048,8 @@ radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs, static void radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, - struct radv_pipeline *pipeline, - const struct radv_tessellation_state *tess, - const struct radv_ngg_state *ngg) + struct radv_pipeline *pipeline) { - if (!radv_pipeline_has_tess(pipeline)) - return; - struct radv_shader_variant *tes, *tcs; tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL]; @@ -3547,64 +4057,147 @@ radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs, if (tes) { if (tes->info.is_ngg) { - radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes, ngg); + radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes); } else if (tes->info.tes.as_es) radv_pipeline_generate_hw_es(cs, pipeline, tes); else radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes); } - radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess); - - radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM, - tess->tf_param); + radv_pipeline_generate_hw_hs(cs, pipeline, tcs); - if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) - radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2, - tess->ls_hs_config); - else - radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, - tess->ls_hs_config); + if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && + !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) { + radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, + S_028A44_ES_VERTS_PER_SUBGRP(250) | + S_028A44_GS_PRIMS_PER_SUBGRP(126) | + S_028A44_GS_INST_PRIMS_IN_SUBGRP(126)); + } } static void -radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, - struct radeon_cmdbuf *cs, - struct radv_pipeline *pipeline, - struct radv_shader_variant *gs, - const struct radv_gs_state *gs_state) +radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs, + struct radv_pipeline *pipeline, + const VkGraphicsPipelineCreateInfo *pCreateInfo) { - unsigned gs_max_out_vertices; - uint8_t *num_components; - uint8_t max_stream; - unsigned offset; - uint64_t va; - - gs_max_out_vertices = gs->info.gs.vertices_out; - max_stream = gs->info.info.gs.max_stream; - num_components = gs->info.info.gs.num_stream_output_components; + struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL); + unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0; + unsigned num_tcs_input_cp, num_tcs_output_cp, num_patches; + unsigned ls_hs_config; - offset = num_components[0] * gs_max_out_vertices; + num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints; + num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT + num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; - radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3); - radeon_emit(ctx_cs, offset); - if (max_stream >= 1) - offset += num_components[1] * gs_max_out_vertices; - radeon_emit(ctx_cs, offset); - if (max_stream >= 2) - offset += num_components[2] * gs_max_out_vertices; - radeon_emit(ctx_cs, offset); - if (max_stream >= 3) - offset += num_components[3] * gs_max_out_vertices; - radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset); + ls_hs_config = S_028B58_NUM_PATCHES(num_patches) | + S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) | + S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp); - radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4); - radeon_emit(ctx_cs, num_components[0]); - radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0); - radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0); - radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0); + if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) { + radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, + 2, ls_hs_config); + } else { + radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, + ls_hs_config); + } - uint32_t gs_num_invocations = gs->info.gs.invocations; + switch (tes->info.tes.primitive_mode) { + case GL_TRIANGLES: + type = V_028B6C_TESS_TRIANGLE; + break; + case GL_QUADS: + type = V_028B6C_TESS_QUAD; + break; + case GL_ISOLINES: + type = V_028B6C_TESS_ISOLINE; + break; + } + + switch (tes->info.tes.spacing) { + case TESS_SPACING_EQUAL: + partitioning = V_028B6C_PART_INTEGER; + break; + case TESS_SPACING_FRACTIONAL_ODD: + partitioning = V_028B6C_PART_FRAC_ODD; + break; + case TESS_SPACING_FRACTIONAL_EVEN: + partitioning = V_028B6C_PART_FRAC_EVEN; + break; + default: + break; + } + + bool ccw = tes->info.tes.ccw; + const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state = + vk_find_struct_const(pCreateInfo->pTessellationState, + PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO); + + if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT) + ccw = !ccw; + + if (tes->info.tes.point_mode) + topology = V_028B6C_OUTPUT_POINT; + else if (tes->info.tes.primitive_mode == GL_ISOLINES) + topology = V_028B6C_OUTPUT_LINE; + else if (ccw) + topology = V_028B6C_OUTPUT_TRIANGLE_CCW; + else + topology = V_028B6C_OUTPUT_TRIANGLE_CW; + + if (pipeline->device->physical_device->rad_info.has_distributed_tess) { + if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI || + pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10) + distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS; + else + distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS; + } else + distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST; + + radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM, + S_028B6C_TYPE(type) | + S_028B6C_PARTITIONING(partitioning) | + S_028B6C_TOPOLOGY(topology) | + S_028B6C_DISTRIBUTION_MODE(distribution_mode)); +} + +static void +radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, + struct radeon_cmdbuf *cs, + struct radv_pipeline *pipeline, + struct radv_shader_variant *gs) +{ + const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info; + unsigned gs_max_out_vertices; + uint8_t *num_components; + uint8_t max_stream; + unsigned offset; + uint64_t va; + + gs_max_out_vertices = gs->info.gs.vertices_out; + max_stream = gs->info.gs.max_stream; + num_components = gs->info.gs.num_stream_output_components; + + offset = num_components[0] * gs_max_out_vertices; + + radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3); + radeon_emit(ctx_cs, offset); + if (max_stream >= 1) + offset += num_components[1] * gs_max_out_vertices; + radeon_emit(ctx_cs, offset); + if (max_stream >= 2) + offset += num_components[2] * gs_max_out_vertices; + radeon_emit(ctx_cs, offset); + if (max_stream >= 3) + offset += num_components[3] * gs_max_out_vertices; + radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset); + + radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4); + radeon_emit(ctx_cs, num_components[0]); + radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0); + radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0); + radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0); + + uint32_t gs_num_invocations = gs->info.gs.invocations; radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT, S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0)); @@ -3645,9 +4238,7 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, static void radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs, - struct radv_pipeline *pipeline, - const struct radv_gs_state *gs_state, - const struct radv_ngg_state *ngg_state) + struct radv_pipeline *pipeline) { struct radv_shader_variant *gs; @@ -3656,21 +4247,28 @@ radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs, return; if (gs->info.is_ngg) - radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs, ngg_state); + radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs); else - radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs, gs_state); + radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs); radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out); } -static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16) +static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, + bool explicit, bool float16) { uint32_t ps_input_cntl; if (offset <= AC_EXP_PARAM_OFFSET_31) { ps_input_cntl = S_028644_OFFSET(offset); - if (flat_shade) + if (flat_shade || explicit) ps_input_cntl |= S_028644_FLAT_SHADE(1); + if (explicit) { + /* Force parameter cache to be read in passthrough + * mode. + */ + ps_input_cntl |= S_028644_OFFSET(1 << 5); + } if (float16) { ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) | S_028644_ATTR0_VALID(1); @@ -3696,53 +4294,63 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs, unsigned ps_offset = 0; - if (ps->info.info.ps.prim_id_input) { + if (ps->info.ps.prim_id_input) { unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID]; if (vs_offset != AC_EXP_PARAM_UNDEFINED) { - ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false); + ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false); ++ps_offset; } } - if (ps->info.info.ps.layer_input || - ps->info.info.needs_multiview_view_index) { + if (ps->info.ps.layer_input || + ps->info.needs_multiview_view_index) { unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER]; if (vs_offset != AC_EXP_PARAM_UNDEFINED) - ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false); + ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false); + else + ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false); + ++ps_offset; + } + + if (ps->info.ps.viewport_index_input) { + unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT]; + if (vs_offset != AC_EXP_PARAM_UNDEFINED) + ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false); else - ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false); + ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false); ++ps_offset; } - if (ps->info.info.ps.has_pcoord) { + if (ps->info.ps.has_pcoord) { unsigned val; val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20); ps_input_cntl[ps_offset] = val; ps_offset++; } - if (ps->info.info.ps.num_input_clips_culls) { + if (ps->info.ps.num_input_clips_culls) { unsigned vs_offset; vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0]; if (vs_offset != AC_EXP_PARAM_UNDEFINED) { - ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false); + ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false); ++ps_offset; } vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1]; if (vs_offset != AC_EXP_PARAM_UNDEFINED && - ps->info.info.ps.num_input_clips_culls > 4) { - ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false); + ps->info.ps.num_input_clips_culls > 4) { + ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false); ++ps_offset; } } - for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) { + for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) { unsigned vs_offset; bool flat_shade; + bool explicit; bool float16; - if (!(ps->info.fs.input_mask & (1u << i))) + if (!(ps->info.ps.input_mask & (1u << i))) continue; vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i]; @@ -3752,10 +4360,11 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs, continue; } - flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u << ps_offset)); - float16 = !!(ps->info.fs.float16_shaded_mask & (1u << ps_offset)); + flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset)); + explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset)); + float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset)); - ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16); + ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16); ++ps_offset; } @@ -3772,29 +4381,37 @@ radv_compute_db_shader_control(const struct radv_device *device, const struct radv_pipeline *pipeline, const struct radv_shader_variant *ps) { + unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z; unsigned z_order; - if (ps->info.fs.early_fragment_test || !ps->info.info.ps.writes_memory) + if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory) z_order = V_02880C_EARLY_Z_THEN_LATE_Z; else z_order = V_02880C_LATE_Z; - bool disable_rbplus = device->physical_device->has_rbplus && - !device->physical_device->rbplus_allowed; + if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER) + conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z; + else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS) + conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z; + + bool disable_rbplus = device->physical_device->rad_info.has_rbplus && + !device->physical_device->rad_info.rbplus_allowed; /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled * but this appears to break Project Cars (DXVK). See * https://bugs.freedesktop.org/show_bug.cgi?id=109401 */ - bool mask_export_enable = ps->info.info.ps.writes_sample_mask; + bool mask_export_enable = ps->info.ps.writes_sample_mask; - return S_02880C_Z_EXPORT_ENABLE(ps->info.info.ps.writes_z) | - S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.info.ps.writes_stencil) | - S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) | + return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) | + S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) | + S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) | S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) | + S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) | S_02880C_Z_ORDER(z_order) | - S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) | - S_02880C_EXEC_ON_HIER_FAIL(ps->info.info.ps.writes_memory) | - S_02880C_EXEC_ON_NOOP(ps->info.info.ps.writes_memory) | + S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) | + S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) | + S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) | + S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) | S_02880C_DUAL_QUAD_DISABLE(disable_rbplus); } @@ -3827,14 +4444,15 @@ radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs, ps->config.spi_ps_input_addr); radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL, - S_0286D8_NUM_INTERP(ps->info.fs.num_interp)); + S_0286D8_NUM_INTERP(ps->info.ps.num_interp) | + S_0286D8_PS_W32_EN(ps->info.wave_size == 32)); radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl); radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT, - ac_get_spi_shader_z_format(ps->info.info.ps.writes_z, - ps->info.info.ps.writes_stencil, - ps->info.info.ps.writes_sample_mask)); + ac_get_spi_shader_z_format(ps->info.ps.writes_z, + ps->info.ps.writes_stencil, + ps->info.ps.writes_sample_mask)); if (pipeline->device->dfsm_allowed) { /* optimise this? */ @@ -3860,8 +4478,9 @@ radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs, S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth)); } -static uint32_t -radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline) +static void +radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf *ctx_cs, + const struct radv_pipeline *pipeline) { uint32_t stages = 0; if (radv_pipeline_has_tess(pipeline)) { @@ -3884,6 +4503,10 @@ radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline) if (radv_pipeline_has_ngg(pipeline)) { stages |= S_028B54_PRIMGEN_EN(1); + if (pipeline->streamout_shader) + stages |= S_028B54_NGG_WAVE_ID_EN(1); + if (radv_pipeline_has_ngg_passthrough(pipeline)) + stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1); } else if (radv_pipeline_has_gs(pipeline)) { stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); } @@ -3891,65 +4514,89 @@ radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline) if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2); - return stages; + if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) { + uint8_t hs_size = 64, gs_size = 64, vs_size = 64; + + if (radv_pipeline_has_tess(pipeline)) + hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size; + + if (pipeline->shaders[MESA_SHADER_GEOMETRY]) { + vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size; + if (pipeline->gs_copy_shader) + vs_size = pipeline->gs_copy_shader->info.wave_size; + } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) + vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size; + else if (pipeline->shaders[MESA_SHADER_VERTEX]) + vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size; + + if (radv_pipeline_has_ngg(pipeline)) + gs_size = vs_size; + + /* legacy GS only supports Wave64 */ + stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) | + S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) | + S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0); + } + + radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, stages); } -static uint32_t -radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo) +static void +radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf *ctx_cs, + const VkGraphicsPipelineCreateInfo *pCreateInfo) { const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info = vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT); + uint32_t cliprect_rule = 0; - if (!discard_rectangle_info) - return 0xffff; - - unsigned mask = 0; - - for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) { - /* Interpret i as a bitmask, and then set the bit in the mask if - * that combination of rectangles in which the pixel is contained - * should pass the cliprect test. */ - unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1); - - if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT && - !relevant_subset) - continue; + if (!discard_rectangle_info) { + cliprect_rule = 0xffff; + } else { + for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) { + /* Interpret i as a bitmask, and then set the bit in + * the mask if that combination of rectangles in which + * the pixel is contained should pass the cliprect + * test. + */ + unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1); + + if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT && + !relevant_subset) + continue; - if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT && - relevant_subset) - continue; + if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT && + relevant_subset) + continue; - mask |= 1u << i; + cliprect_rule |= 1u << i; + } } - return mask; + radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, cliprect_rule); } static void gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs, - struct radv_pipeline *pipeline, - const struct radv_tessellation_state *tess, - const struct radv_gs_state *gs_state) + struct radv_pipeline *pipeline) { bool break_wave_at_eoi = false; unsigned primgroup_size; - unsigned vertgroup_size; + unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */ if (radv_pipeline_has_tess(pipeline)) { - primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */ - vertgroup_size = 0; + primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; } else if (radv_pipeline_has_gs(pipeline)) { + const struct gfx9_gs_info *gs_state = + &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info; unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl; primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl); - vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl); } else { primgroup_size = 128; /* recommended without a GS and tess */ - vertgroup_size = 0; } if (radv_pipeline_has_tess(pipeline)) { - if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id || - radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id) + if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id || + radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id) break_wave_at_eoi = true; } @@ -3960,15 +4607,40 @@ gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs, S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi)); } +static void +radv_pipeline_generate_vgt_gs_out(struct radeon_cmdbuf *ctx_cs, + struct radv_pipeline *pipeline, + const VkGraphicsPipelineCreateInfo *pCreateInfo, + const struct radv_graphics_pipeline_create_info *extra) +{ + uint32_t gs_out; + + if (radv_pipeline_has_gs(pipeline)) { + gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim); + } else if (radv_pipeline_has_tess(pipeline)) { + if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) { + gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST; + } else { + gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode); + } + } else { + gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology); + } + + if (extra && extra->use_rectlist) { + gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP; + if (radv_pipeline_has_ngg(pipeline)) + gs_out = V_028A6C_VGT_OUT_RECT_V0; + } + + radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out); +} + static void radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo, const struct radv_graphics_pipeline_create_info *extra, - const struct radv_blend_state *blend, - const struct radv_tessellation_state *tess, - const struct radv_gs_state *gs, - const struct radv_ngg_state *ngg, - unsigned prim, unsigned gs_out) + const struct radv_blend_state *blend) { struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs; struct radeon_cmdbuf *cs = &pipeline->cs; @@ -3983,32 +4655,24 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo); radv_pipeline_generate_multisample_state(ctx_cs, pipeline); radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline); - radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess, ngg); - radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess, ngg); - radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline, gs, ngg); + radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline); + + if (radv_pipeline_has_tess(pipeline)) { + radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline); + radv_pipeline_generate_tess_state(ctx_cs, pipeline, pCreateInfo); + } + + radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline); radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline); radv_pipeline_generate_ps_inputs(ctx_cs, pipeline); radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline); - radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo); + radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend); + radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline); + radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo); + radv_pipeline_generate_vgt_gs_out(ctx_cs, pipeline, pCreateInfo, extra); if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline)) - gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess, gs); - - radeon_set_context_reg(ctx_cs, R_0286E8_SPI_TMPRING_SIZE, - S_0286E8_WAVES(pipeline->max_waves) | - S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10)); - - radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline)); - - if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) { - radeon_set_uconfig_reg_idx(pipeline->device->physical_device, - cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim); - } else { - radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim); - } - radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out); - - radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo)); + gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline); pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4); @@ -4017,15 +4681,13 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, } static struct radv_ia_multi_vgt_param_helpers -radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline, - const struct radv_tessellation_state *tess, - uint32_t prim) +radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline) { struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0}; const struct radv_device *device = pipeline->device; if (radv_pipeline_has_tess(pipeline)) - ia_multi_vgt_param.primgroup_size = tess->num_patches; + ia_multi_vgt_param.primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; else if (radv_pipeline_has_gs(pipeline)) ia_multi_vgt_param.primgroup_size = 64; else @@ -4037,33 +4699,16 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline, if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3) ia_multi_vgt_param.partial_es_wave = true; - ia_multi_vgt_param.wd_switch_on_eop = false; - if (device->physical_device->rad_info.chip_class >= GFX7) { - /* WD_SWITCH_ON_EOP has no effect on GPUs with less than - * 4 shader engines. Set 1 to pass the assertion below. - * The other cases are hardware requirements. */ - if (device->physical_device->rad_info.max_se < 4 || - prim == V_008958_DI_PT_POLYGON || - prim == V_008958_DI_PT_LINELOOP || - prim == V_008958_DI_PT_TRIFAN || - prim == V_008958_DI_PT_TRISTRIP_ADJ || - (pipeline->graphics.prim_restart_enable && - (device->physical_device->rad_info.family < CHIP_POLARIS10 || - (prim != V_008958_DI_PT_POINTLIST && - prim != V_008958_DI_PT_LINESTRIP)))) - ia_multi_vgt_param.wd_switch_on_eop = true; - } - ia_multi_vgt_param.ia_switch_on_eoi = false; - if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input) + if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input) ia_multi_vgt_param.ia_switch_on_eoi = true; if (radv_pipeline_has_gs(pipeline) && - pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id) + pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id) ia_multi_vgt_param.ia_switch_on_eoi = true; if (radv_pipeline_has_tess(pipeline)) { /* SWITCH_ON_EOI must be set if PrimID is used. */ - if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.uses_prim_id || - radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.info.uses_prim_id) + if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id || + radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id) ia_multi_vgt_param.ia_switch_on_eoi = true; } @@ -4076,7 +4721,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline, radv_pipeline_has_gs(pipeline)) ia_multi_vgt_param.partial_vs_wave = true; /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */ - if (device->has_distributed_tess) { + if (device->physical_device->rad_info.has_distributed_tess) { if (radv_pipeline_has_gs(pipeline)) { if (device->physical_device->rad_info.chip_class <= GFX8) ia_multi_vgt_param.partial_es_wave = true; @@ -4086,17 +4731,6 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline, } } - /* Workaround for a VGT hang when strip primitive types are used with - * primitive restart. - */ - if (pipeline->graphics.prim_restart_enable && - (prim == V_008958_DI_PT_LINESTRIP || - prim == V_008958_DI_PT_TRISTRIP || - prim == V_008958_DI_PT_LINESTRIP_ADJ || - prim == V_008958_DI_PT_TRISTRIP_ADJ)) { - ia_multi_vgt_param.partial_vs_wave = true; - } - if (radv_pipeline_has_gs(pipeline)) { /* On these chips there is the possibility of a hang if the * pipeline uses a GS and partial_vs_wave is not set. @@ -4134,18 +4768,6 @@ radv_compute_vertex_input_state(struct radv_pipeline *pipeline, { const VkPipelineVertexInputStateCreateInfo *vi_info = pCreateInfo->pVertexInputState; - struct radv_vertex_elements_info *velems = &pipeline->vertex_elements; - - for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) { - const VkVertexInputAttributeDescription *desc = - &vi_info->pVertexAttributeDescriptions[i]; - unsigned loc = desc->location; - const struct vk_format_description *format_desc; - - format_desc = vk_format_description(desc->format); - - velems->format_size[loc] = format_desc->block.bits / 8; - } for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) { const VkVertexInputBindingDescription *desc = @@ -4166,7 +4788,7 @@ radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline) struct radv_shader_variant *shader = radv_get_shader(pipeline, i); - if (shader && shader->info.info.so.num_outputs > 0) + if (shader && shader->info.so.num_outputs > 0) return shader; } @@ -4181,12 +4803,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline, const struct radv_graphics_pipeline_create_info *extra) { VkResult result; - bool has_view_index = false; - - RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); - struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass; - if (subpass->view_mask) - has_view_index = true; pipeline->device = device; pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); @@ -4209,40 +4825,18 @@ radv_pipeline_init(struct radv_pipeline *pipeline, stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i]; } - struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index); - radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks); + struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend); + + result = radv_create_shaders(pipeline, device, cache, &key, pStages, + pCreateInfo->flags, pipeline_feedback, + stage_feedbacks); + if (result != VK_SUCCESS) + return result; pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo); - uint32_t gs_out; - uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology); - - pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology); - - if (radv_pipeline_has_gs(pipeline)) { - gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim); - pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP; - } else if (radv_pipeline_has_tess(pipeline)) { - if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) - gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST; - else - gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode); - pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP; - } else { - gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology); - } - if (extra && extra->use_rectlist) { - prim = V_008958_DI_PT_RECTLIST; - gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP; - pipeline->graphics.can_use_guardband = true; - if (radv_pipeline_has_ngg(pipeline)) - gs_out = V_028A6C_VGT_OUT_RECT_V0; - } - pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable; - /* prim vertex count will need TESS changes */ - pipeline->graphics.prim_vertex_count = prim_size_table[prim]; - - radv_pipeline_init_dynamic_state(pipeline, pCreateInfo); + radv_pipeline_init_input_assembly_state(pipeline, pCreateInfo, extra); + radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, extra); /* Ensure that some export memory is always allocated, for two reasons: * @@ -4254,41 +4848,53 @@ radv_pipeline_init(struct radv_pipeline *pipeline, * stalls without this setting. * * Don't add this to CB_SHADER_MASK. + * + * GFX10 supports pixel shaders without exports by setting both the + * color and Z formats to SPI_SHADER_ZERO. The hw will skip export + * instructions if any are present. */ struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; - if (!blend.spi_shader_col_format) { - if (!ps->info.info.ps.writes_z && - !ps->info.info.ps.writes_stencil && - !ps->info.info.ps.writes_sample_mask) + if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 || + ps->info.ps.can_discard) && + !blend.spi_shader_col_format) { + if (!ps->info.ps.writes_z && + !ps->info.ps.writes_stencil && + !ps->info.ps.writes_sample_mask) blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; } + blend.cb_shader_mask = ps->info.ps.cb_shader_mask; + + if (extra && + (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR || + extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS || + extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS || + extra->custom_blend_mode == V_028808_CB_RESOLVE)) { + /* According to the CB spec states, CB_SHADER_MASK should be + * set to enable writes to all four channels of MRT0. + */ + blend.cb_shader_mask = 0xf; + } + for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { if (pipeline->shaders[i]) { pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets; } } - struct radv_ngg_state ngg = {0}; - struct radv_gs_state gs = {0}; + if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) { + struct radv_shader_variant *gs = + pipeline->shaders[MESA_SHADER_GEOMETRY]; - if (radv_pipeline_has_ngg(pipeline)) { - ngg = calculate_ngg_info(pCreateInfo, pipeline); - } else if (radv_pipeline_has_gs(pipeline)) { - gs = calculate_gs_info(pCreateInfo, pipeline); - calculate_gs_ring_sizes(pipeline, &gs); + calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info); } - struct radv_tessellation_state tess = {0}; if (radv_pipeline_has_tess(pipeline)) { - if (prim == V_008958_DI_PT_PATCH) { - pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints; - pipeline->graphics.prim_vertex_count.incr = 1; - } - tess = calculate_tess_state(pipeline, pCreateInfo); + pipeline->graphics.tess_patch_control_points = + pCreateInfo->pTessellationState->patchControlPoints; } - pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim); + pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline); radv_compute_vertex_input_state(pipeline, pCreateInfo); @@ -4300,7 +4906,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline, if (loc->sgpr_idx != -1) { pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX]; pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4; - if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id) + if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id) pipeline->graphics.vtx_emit_num = 3; else pipeline->graphics.vtx_emit_num = 2; @@ -4310,7 +4916,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline, pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline); result = radv_pipeline_scratch_init(device, pipeline); - radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, &gs, &ngg, prim, gs_out); + radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend); return result; } @@ -4329,11 +4935,14 @@ radv_graphics_pipeline_create( struct radv_pipeline *pipeline; VkResult result; - pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8, + pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); if (pipeline == NULL) return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); + vk_object_base_init(&device->vk, &pipeline->base, + VK_OBJECT_TYPE_PIPELINE); + result = radv_pipeline_init(pipeline, device, cache, pCreateInfo, extra); if (result != VK_SUCCESS) { @@ -4366,73 +4975,109 @@ VkResult radv_CreateGraphicsPipelines( if (r != VK_SUCCESS) { result = r; pPipelines[i] = VK_NULL_HANDLE; + + if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT) + break; } } + for (; i < count; ++i) + pPipelines[i] = VK_NULL_HANDLE; + return result; } +static void +radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs, + struct radv_pipeline *pipeline) +{ + struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE]; + uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; + struct radv_device *device = pipeline->device; + + radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2); + radeon_emit(cs, va >> 8); + radeon_emit(cs, S_00B834_DATA(va >> 40)); + + radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2); + radeon_emit(cs, shader->config.rsrc1); + radeon_emit(cs, shader->config.rsrc2); + if (device->physical_device->rad_info.chip_class >= GFX10) { + radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3); + } +} static void -radv_compute_generate_pm4(struct radv_pipeline *pipeline) +radv_pipeline_generate_compute_state(struct radeon_cmdbuf *cs, + struct radv_pipeline *pipeline) { - struct radv_shader_variant *compute_shader; + struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE]; struct radv_device *device = pipeline->device; - unsigned compute_resource_limits; + unsigned threads_per_threadgroup; + unsigned threadgroups_per_cu = 1; unsigned waves_per_threadgroup; - uint64_t va; + unsigned max_waves_per_sh = 0; - pipeline->cs.buf = malloc(20 * 4); - pipeline->cs.max_dw = 20; + /* Calculate best compute resource limits. */ + threads_per_threadgroup = shader->info.cs.block_size[0] * + shader->info.cs.block_size[1] * + shader->info.cs.block_size[2]; + waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup, + shader->info.wave_size); + + if (device->physical_device->rad_info.chip_class >= GFX10 && + waves_per_threadgroup == 1) + threadgroups_per_cu = 2; + + radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, + ac_get_compute_resource_limits(&device->physical_device->rad_info, + waves_per_threadgroup, + max_waves_per_sh, + threadgroups_per_cu)); + + radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3); + radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[0])); + radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[1])); + radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[2])); +} - compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE]; - va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset; +static void +radv_compute_generate_pm4(struct radv_pipeline *pipeline) +{ + struct radv_device *device = pipeline->device; + struct radeon_cmdbuf *cs = &pipeline->cs; - radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2); - radeon_emit(&pipeline->cs, va >> 8); - radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40)); + cs->max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 19 : 16; + cs->buf = malloc(cs->max_dw * 4); - radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2); - radeon_emit(&pipeline->cs, compute_shader->config.rsrc1); - radeon_emit(&pipeline->cs, compute_shader->config.rsrc2); + radv_pipeline_generate_hw_cs(cs, pipeline); + radv_pipeline_generate_compute_state(cs, pipeline); - radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE, - S_00B860_WAVES(pipeline->max_waves) | - S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10)); + assert(pipeline->cs.cdw <= pipeline->cs.max_dw); +} - /* Calculate best compute resource limits. */ - waves_per_threadgroup = - DIV_ROUND_UP(compute_shader->info.cs.block_size[0] * - compute_shader->info.cs.block_size[1] * - compute_shader->info.cs.block_size[2], 64); - compute_resource_limits = - S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0); - - if (device->physical_device->rad_info.chip_class >= GFX7) { - unsigned num_cu_per_se = - device->physical_device->rad_info.num_good_compute_units / - device->physical_device->rad_info.max_se; - - /* Force even distribution on all SIMDs in CU if the workgroup - * size is 64. This has shown some good improvements if # of - * CUs per SE is not a multiple of 4. - */ - if (num_cu_per_se % 4 && waves_per_threadgroup == 1) - compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1); - } +static struct radv_pipeline_key +radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline, + const VkComputePipelineCreateInfo *pCreateInfo) +{ + const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage; + struct radv_pipeline_key key; + memset(&key, 0, sizeof(key)); - radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS, - compute_resource_limits); + if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT) + key.optimisations_disabled = 1; - radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3); - radeon_emit(&pipeline->cs, - S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0])); - radeon_emit(&pipeline->cs, - S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1])); - radeon_emit(&pipeline->cs, - S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2])); + const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size = + vk_find_struct_const(stage->pNext, + PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT); - assert(pipeline->cs.cdw <= pipeline->cs.max_dw); + if (subgroup_size) { + assert(subgroup_size->requiredSubgroupSize == 32 || + subgroup_size->requiredSubgroupSize == 64); + key.compute_subgroup_size = subgroup_size->requiredSubgroupSize; + } + + return key; } static VkResult radv_compute_pipeline_create( @@ -4449,11 +5094,14 @@ static VkResult radv_compute_pipeline_create( struct radv_pipeline *pipeline; VkResult result; - pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8, + pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); if (pipeline == NULL) return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); + vk_object_base_init(&device->vk, &pipeline->base, + VK_OBJECT_TYPE_PIPELINE); + pipeline->device = device; pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); assert(pipeline->layout); @@ -4467,7 +5115,17 @@ static VkResult radv_compute_pipeline_create( stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0]; pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage; - radv_create_shaders(pipeline, device, cache, &(struct radv_pipeline_key) {0}, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks); + + struct radv_pipeline_key key = + radv_generate_compute_pipeline_key(pipeline, pCreateInfo); + + result = radv_create_shaders(pipeline, device, cache, &key, pStages, + pCreateInfo->flags, pipeline_feedback, + stage_feedbacks); + if (result != VK_SUCCESS) { + radv_pipeline_destroy(device, pipeline, pAllocator); + return result; + } pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class); pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets; @@ -4503,7 +5161,353 @@ VkResult radv_CreateComputePipelines( if (r != VK_SUCCESS) { result = r; pPipelines[i] = VK_NULL_HANDLE; + + if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT) + break; + } + } + + for (; i < count; ++i) + pPipelines[i] = VK_NULL_HANDLE; + + return result; +} + + +static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline) +{ + uint32_t ret = 0; + for (int i = 0; i < MESA_SHADER_STAGES; ++i) { + if (!pipeline->shaders[i]) + continue; + + if (i == MESA_SHADER_GEOMETRY && + !radv_pipeline_has_ngg(pipeline)) { + ret += 2u; + } else { + ret += 1u; } + + } + return ret; +} + +static struct radv_shader_variant * +radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage) +{ + for (int i = 0; i < MESA_SHADER_STAGES; ++i) { + if (!pipeline->shaders[i]) + continue; + if (!index) { + *stage = i; + return pipeline->shaders[i]; + } + + --index; + + if (i == MESA_SHADER_GEOMETRY && + !radv_pipeline_has_ngg(pipeline)) { + if (!index) { + *stage = i; + return pipeline->gs_copy_shader; + } + --index; + } + } + + *stage = -1; + return NULL; +} + +/* Basically strlcpy (which does not exist on linux) specialized for + * descriptions. */ +static void desc_copy(char *desc, const char *src) { + int len = strlen(src); + assert(len < VK_MAX_DESCRIPTION_SIZE); + memcpy(desc, src, len); + memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len); +} + +VkResult radv_GetPipelineExecutablePropertiesKHR( + VkDevice _device, + const VkPipelineInfoKHR* pPipelineInfo, + uint32_t* pExecutableCount, + VkPipelineExecutablePropertiesKHR* pProperties) +{ + RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline); + const uint32_t total_count = radv_get_executable_count(pipeline); + + if (!pProperties) { + *pExecutableCount = total_count; + return VK_SUCCESS; + } + + const uint32_t count = MIN2(total_count, *pExecutableCount); + for (unsigned i = 0, executable_idx = 0; + i < MESA_SHADER_STAGES && executable_idx < count; ++i) { + if (!pipeline->shaders[i]) + continue; + pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i); + const char *name = NULL; + const char *description = NULL; + switch(i) { + case MESA_SHADER_VERTEX: + name = "Vertex Shader"; + description = "Vulkan Vertex Shader"; + break; + case MESA_SHADER_TESS_CTRL: + if (!pipeline->shaders[MESA_SHADER_VERTEX]) { + pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT; + name = "Vertex + Tessellation Control Shaders"; + description = "Combined Vulkan Vertex and Tessellation Control Shaders"; + } else { + name = "Tessellation Control Shader"; + description = "Vulkan Tessellation Control Shader"; + } + break; + case MESA_SHADER_TESS_EVAL: + name = "Tessellation Evaluation Shader"; + description = "Vulkan Tessellation Evaluation Shader"; + break; + case MESA_SHADER_GEOMETRY: + if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) { + pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT; + name = "Tessellation Evaluation + Geometry Shaders"; + description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders"; + } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) { + pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT; + name = "Vertex + Geometry Shader"; + description = "Combined Vulkan Vertex and Geometry Shaders"; + } else { + name = "Geometry Shader"; + description = "Vulkan Geometry Shader"; + } + break; + case MESA_SHADER_FRAGMENT: + name = "Fragment Shader"; + description = "Vulkan Fragment Shader"; + break; + case MESA_SHADER_COMPUTE: + name = "Compute Shader"; + description = "Vulkan Compute Shader"; + break; + } + + pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size; + desc_copy(pProperties[executable_idx].name, name); + desc_copy(pProperties[executable_idx].description, description); + + ++executable_idx; + if (i == MESA_SHADER_GEOMETRY && + !radv_pipeline_has_ngg(pipeline)) { + assert(pipeline->gs_copy_shader); + if (executable_idx >= count) + break; + + pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT; + pProperties[executable_idx].subgroupSize = 64; + desc_copy(pProperties[executable_idx].name, "GS Copy Shader"); + desc_copy(pProperties[executable_idx].description, + "Extra shader stage that loads the GS output ringbuffer into the rasterizer"); + + ++executable_idx; + } + } + + VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS; + *pExecutableCount = count; + return result; +} + +VkResult radv_GetPipelineExecutableStatisticsKHR( + VkDevice _device, + const VkPipelineExecutableInfoKHR* pExecutableInfo, + uint32_t* pStatisticCount, + VkPipelineExecutableStatisticKHR* pStatistics) +{ + RADV_FROM_HANDLE(radv_device, device, _device); + RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline); + gl_shader_stage stage; + struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage); + + enum chip_class chip_class = device->physical_device->rad_info.chip_class; + unsigned lds_increment = chip_class >= GFX7 ? 512 : 256; + unsigned max_waves = radv_get_max_waves(device, shader, stage); + + VkPipelineExecutableStatisticKHR *s = pStatistics; + VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0); + VkResult result = VK_SUCCESS; + + if (s < end) { + desc_copy(s->name, "SGPRs"); + desc_copy(s->description, "Number of SGPR registers allocated per subgroup"); + s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR; + s->value.u64 = shader->config.num_sgprs; + } + ++s; + + if (s < end) { + desc_copy(s->name, "VGPRs"); + desc_copy(s->description, "Number of VGPR registers allocated per subgroup"); + s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR; + s->value.u64 = shader->config.num_vgprs; + } + ++s; + + if (s < end) { + desc_copy(s->name, "Spilled SGPRs"); + desc_copy(s->description, "Number of SGPR registers spilled per subgroup"); + s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR; + s->value.u64 = shader->config.spilled_sgprs; + } + ++s; + + if (s < end) { + desc_copy(s->name, "Spilled VGPRs"); + desc_copy(s->description, "Number of VGPR registers spilled per subgroup"); + s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR; + s->value.u64 = shader->config.spilled_vgprs; + } + ++s; + + if (s < end) { + desc_copy(s->name, "PrivMem VGPRs"); + desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup"); + s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR; + s->value.u64 = shader->info.private_mem_vgprs; + } + ++s; + + if (s < end) { + desc_copy(s->name, "Code size"); + desc_copy(s->description, "Code size in bytes"); + s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR; + s->value.u64 = shader->exec_size; + } + ++s; + + if (s < end) { + desc_copy(s->name, "LDS size"); + desc_copy(s->description, "LDS size in bytes per workgroup"); + s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR; + s->value.u64 = shader->config.lds_size * lds_increment; + } + ++s; + + if (s < end) { + desc_copy(s->name, "Scratch size"); + desc_copy(s->description, "Private memory in bytes per subgroup"); + s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR; + s->value.u64 = shader->config.scratch_bytes_per_wave; + } + ++s; + + if (s < end) { + desc_copy(s->name, "Subgroups per SIMD"); + desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit"); + s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR; + s->value.u64 = max_waves; + } + ++s; + + if (shader->statistics) { + for (unsigned i = 0; i < shader->statistics->count; i++) { + struct radv_compiler_statistic_info *info = &shader->statistics->infos[i]; + uint32_t value = shader->statistics->values[i]; + if (s < end) { + desc_copy(s->name, info->name); + desc_copy(s->description, info->desc); + s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR; + s->value.u64 = value; + } + ++s; + } + } + + if (!pStatistics) + *pStatisticCount = s - pStatistics; + else if (s > end) { + *pStatisticCount = end - pStatistics; + result = VK_INCOMPLETE; + } else { + *pStatisticCount = s - pStatistics; + } + + return result; +} + +static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src) +{ + size_t total_size = strlen(src) + 1; + + if (!data) { + *data_size = total_size; + return VK_SUCCESS; + } + + size_t size = MIN2(total_size, *data_size); + + memcpy(data, src, size); + if (size) + *((char*)data + size - 1) = 0; + return size < total_size ? VK_INCOMPLETE : VK_SUCCESS; +} + +VkResult radv_GetPipelineExecutableInternalRepresentationsKHR( + VkDevice device, + const VkPipelineExecutableInfoKHR* pExecutableInfo, + uint32_t* pInternalRepresentationCount, + VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations) +{ + RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline); + gl_shader_stage stage; + struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage); + + VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations; + VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0); + VkResult result = VK_SUCCESS; + /* optimized NIR */ + if (p < end) { + p->isText = true; + desc_copy(p->name, "NIR Shader(s)"); + desc_copy(p->description, "The optimized NIR shader(s)"); + if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS) + result = VK_INCOMPLETE; + } + ++p; + + /* backend IR */ + if (p < end) { + p->isText = true; + if (pipeline->device->physical_device->use_llvm) { + desc_copy(p->name, "LLVM IR"); + desc_copy(p->description, "The LLVM IR after some optimizations"); + } else { + desc_copy(p->name, "ACO IR"); + desc_copy(p->description, "The ACO IR after some optimizations"); + } + if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS) + result = VK_INCOMPLETE; + } + ++p; + + /* Disassembler */ + if (p < end) { + p->isText = true; + desc_copy(p->name, "Assembly"); + desc_copy(p->description, "Final Assembly"); + if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS) + result = VK_INCOMPLETE; + } + ++p; + + if (!pInternalRepresentations) + *pInternalRepresentationCount = p - pInternalRepresentations; + else if(p > end) { + result = VK_INCOMPLETE; + *pInternalRepresentationCount = end - pInternalRepresentations; + } else { + *pInternalRepresentationCount = p - pInternalRepresentations; } return result;