X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_query.c;h=0991c267000bbbb46bf66e96d8e819b59ffa472c;hb=568aec29d9eb57c05668f061677d5e9bc3b4de97;hp=7e0fd1d073f2fdab49e4e940d1b883635cb68686;hpb=14ae0bfa5400f2a325b93040a8e7734332c7469f;p=mesa.git

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 7e0fd1d073f..0991c267000 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1196,21 +1196,35 @@ void radv_CmdWriteTimestamp(
 
 	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12);
 
-	if (mec) {
-		radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0));
-		radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
-		radeon_emit(cs, 3 << 29);
-		radeon_emit(cs, query_va);
-		radeon_emit(cs, query_va >> 32);
+	switch(pipelineStage) {
+	case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
+		radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+		radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |
+		                COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
+		                COPY_DATA_DST_SEL(V_370_MEM_ASYNC));
 		radeon_emit(cs, 0);
 		radeon_emit(cs, 0);
-	} else {
-		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-		radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
 		radeon_emit(cs, query_va);
-		radeon_emit(cs, (3 << 29) | ((query_va >> 32) & 0xFFFF));
-		radeon_emit(cs, 0);
-		radeon_emit(cs, 0);
+		radeon_emit(cs, query_va >> 32);
+		break;
+	default:
+		if (mec) {
+			radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0));
+			radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
+			radeon_emit(cs, 3 << 29);
+			radeon_emit(cs, query_va);
+			radeon_emit(cs, query_va >> 32);
+			radeon_emit(cs, 0);
+			radeon_emit(cs, 0);
+		} else {
+			radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
+			radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5));
+			radeon_emit(cs, query_va);
+			radeon_emit(cs, (3 << 29) | ((query_va >> 32) & 0xFFFF));
+			radeon_emit(cs, 0);
+			radeon_emit(cs, 0);
+		}
+		break;
 	}
 
 	radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));