X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_radeon_winsys.h;h=52b55c38e697c72d77e42a3ef8854364b4338a3c;hb=65dcff7a26730e2e1112f7f326b941e3a3549870;hp=8cf29a38d9474de0fe7c337a87e52dc20941f82c;hpb=c121739c4772a9442bc6866abae9306773abe3de;p=mesa.git diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h index 8cf29a38d94..52b55c38e69 100644 --- a/src/amd/vulkan/radv_radeon_winsys.h +++ b/src/amd/vulkan/radv_radeon_winsys.h @@ -35,6 +35,10 @@ #include "main/macros.h" #include "amd_family.h" +struct radeon_info; +struct ac_surf_info; +struct radeon_surf; + #define FREE(x) free(x) enum radeon_bo_domain { /* bitfield */ @@ -47,6 +51,8 @@ enum radeon_bo_flag { /* bitfield */ RADEON_FLAG_GTT_WC = (1 << 0), RADEON_FLAG_CPU_ACCESS = (1 << 1), RADEON_FLAG_NO_CPU_ACCESS = (1 << 2), + RADEON_FLAG_VIRTUAL = (1 << 3), + RADEON_FLAG_VA_UNCACHED = (1 << 4), }; enum radeon_bo_usage { /* bitfield */ @@ -70,63 +76,6 @@ struct radeon_winsys_cs { uint32_t *buf; /* The base pointer of the chunk. */ }; -struct radeon_info { - /* PCI info: domain:bus:dev:func */ - uint32_t pci_domain; - uint32_t pci_bus; - uint32_t pci_dev; - uint32_t pci_func; - - /* Device info. */ - uint32_t pci_id; - enum radeon_family family; - const char *name; - enum chip_class chip_class; - uint32_t gart_page_size; - uint64_t gart_size; - uint64_t vram_size; - uint64_t visible_vram_size; - bool has_dedicated_vram; - bool has_virtual_memory; - bool gfx_ib_pad_with_type2; - bool has_uvd; - uint32_t sdma_rings; - uint32_t compute_rings; - uint32_t vce_fw_version; - uint32_t vce_harvest_config; - uint32_t clock_crystal_freq; - - /* Kernel info. */ - uint32_t drm_major; /* version */ - uint32_t drm_minor; - uint32_t drm_patchlevel; - bool has_userptr; - - /* Shader cores. */ - uint32_t r600_max_quad_pipes; /* wave size / 16 */ - uint32_t max_shader_clock; - uint32_t num_good_compute_units; - uint32_t max_se; /* shader engines */ - uint32_t max_sh_per_se; /* shader arrays per shader engine */ - - /* Render backends (color + depth blocks). */ - uint32_t r300_num_gb_pipes; - uint32_t r300_num_z_pipes; - uint32_t r600_gb_backend_map; /* R600 harvest config */ - bool r600_gb_backend_map_valid; - uint32_t r600_num_banks; - uint32_t num_render_backends; - uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ - uint32_t pipe_interleave_bytes; - uint32_t enabled_rb_mask; /* GCN harvest config */ - - /* Tile modes. */ - uint32_t si_tile_mode_array[32]; - uint32_t cik_macrotile_mode_array[16]; -}; - -#define RADEON_SURF_MAX_LEVEL 32 - #define RADEON_SURF_TYPE_MASK 0xFF #define RADEON_SURF_TYPE_SHIFT 0 #define RADEON_SURF_TYPE_1D 0 @@ -137,88 +86,11 @@ struct radeon_info { #define RADEON_SURF_TYPE_2D_ARRAY 5 #define RADEON_SURF_MODE_MASK 0xFF #define RADEON_SURF_MODE_SHIFT 8 -#define RADEON_SURF_MODE_LINEAR_ALIGNED 1 -#define RADEON_SURF_MODE_1D 2 -#define RADEON_SURF_MODE_2D 3 -#define RADEON_SURF_SCANOUT (1 << 16) -#define RADEON_SURF_ZBUFFER (1 << 17) -#define RADEON_SURF_SBUFFER (1 << 18) -#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) -#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19) -#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20) -#define RADEON_SURF_FMASK (1 << 21) -#define RADEON_SURF_DISABLE_DCC (1 << 22) #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) #define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT)) -struct radeon_surf_level { - uint64_t offset; - uint64_t slice_size; - uint32_t npix_x; - uint32_t npix_y; - uint32_t npix_z; - uint32_t nblk_x; - uint32_t nblk_y; - uint32_t nblk_z; - uint32_t pitch_bytes; - uint32_t mode; - uint64_t dcc_offset; - uint64_t dcc_fast_clear_size; - bool dcc_enabled; -}; - - -/* surface defintions from the winsys */ -struct radeon_surf { - /* These are inputs to the calculator. */ - uint32_t npix_x; - uint32_t npix_y; - uint32_t npix_z; - uint32_t blk_w; - uint32_t blk_h; - uint32_t blk_d; - uint32_t array_size; - uint32_t last_level; - uint32_t bpe; - uint32_t nsamples; - uint32_t flags; - - /* These are return values. Some of them can be set by the caller, but - * they will be treated as hints (e.g. bankw, bankh) and might be - * changed by the calculator. - */ - uint64_t bo_size; - uint64_t bo_alignment; - /* This applies to EG and later. */ - uint32_t bankw; - uint32_t bankh; - uint32_t mtilea; - uint32_t tile_split; - uint32_t stencil_tile_split; - uint64_t stencil_offset; - struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL]; - struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL]; - uint32_t tiling_index[RADEON_SURF_MAX_LEVEL]; - uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL]; - uint32_t pipe_config; - uint32_t num_banks; - uint32_t macro_tile_index; - uint32_t micro_tile_mode; /* displayable, thin, depth, rotated */ - - /* Whether the depth miptree or stencil miptree as used by the DB are - * adjusted from their TC compatible form to ensure depth/stencil - * compatibility. If either is true, the corresponding plane cannot be - * sampled from. - */ - bool depth_adjusted; - bool stencil_adjusted; - - uint64_t dcc_size; - uint64_t dcc_alignment; -}; - enum radeon_bo_layout { RADEON_LAYOUT_LINEAR = 0, RADEON_LAYOUT_TILED, @@ -232,16 +104,25 @@ struct radeon_bo_metadata { /* Tiling flags describing the texture layout for display code * and DRI sharing. */ - enum radeon_bo_layout microtile; - enum radeon_bo_layout macrotile; - unsigned pipe_config; - unsigned bankw; - unsigned bankh; - unsigned tile_split; - unsigned mtilea; - unsigned num_banks; - unsigned stride; - bool scanout; + union { + struct { + enum radeon_bo_layout microtile; + enum radeon_bo_layout macrotile; + unsigned pipe_config; + unsigned bankw; + unsigned bankh; + unsigned tile_split; + unsigned mtilea; + unsigned num_banks; + unsigned stride; + bool scanout; + } legacy; + + struct { + /* surface flags */ + unsigned swizzle_mode:5; + } gfx9; + } u; /* Additional metadata associated with the buffer, in bytes. * The maximum size is 64 * 4. This is opaque for the winsys & kernel. @@ -251,9 +132,25 @@ struct radeon_bo_metadata { uint32_t metadata[64]; }; -struct radeon_winsys_bo; +uint32_t syncobj_handle; struct radeon_winsys_fence; -struct radeon_winsys_sem; + +struct radeon_winsys_bo { + uint64_t va; +}; +struct radv_winsys_sem_counts { + uint32_t syncobj_count; + uint32_t sem_count; + uint32_t *syncobj; + struct radeon_winsys_sem **sem; +}; + +struct radv_winsys_sem_info { + bool cs_emit_signal; + bool cs_emit_wait; + struct radv_winsys_sem_counts wait; + struct radv_winsys_sem_counts signal; +}; struct radeon_winsys { void (*destroy)(struct radeon_winsys *ws); @@ -261,6 +158,11 @@ struct radeon_winsys { void (*query_info)(struct radeon_winsys *ws, struct radeon_info *info); + bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, + unsigned num_registers, uint32_t *out); + + const char *(*get_chip_name)(struct radeon_winsys *ws); + struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws, uint64_t size, unsigned alignment, @@ -280,10 +182,12 @@ struct radeon_winsys { void (*buffer_unmap)(struct radeon_winsys_bo *bo); - uint64_t (*buffer_get_va)(struct radeon_winsys_bo *bo); - void (*buffer_set_metadata)(struct radeon_winsys_bo *bo, struct radeon_bo_metadata *md); + + void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent, + uint64_t offset, uint64_t size, + struct radeon_winsys_bo *bo, uint64_t bo_offset); struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws); void (*ctx_destroy)(struct radeon_winsys_ctx *ctx); @@ -307,10 +211,7 @@ struct radeon_winsys { unsigned cs_count, struct radeon_winsys_cs *initial_preamble_cs, struct radeon_winsys_cs *continue_preamble_cs, - struct radeon_winsys_sem **wait_sem, - unsigned wait_sem_count, - struct radeon_winsys_sem **signal_sem, - unsigned signal_sem_count, + struct radv_winsys_sem_info *sem_info, bool can_patch, struct radeon_winsys_fence *fence); @@ -321,9 +222,10 @@ struct radeon_winsys { void (*cs_execute_secondary)(struct radeon_winsys_cs *parent, struct radeon_winsys_cs *child); - void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t trace_id); + void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, const int *trace_ids, int trace_id_count); int (*surface_init)(struct radeon_winsys *ws, + const struct ac_surf_info *surf_info, struct radeon_surf *surf); int (*surface_best)(struct radeon_winsys *ws, @@ -336,9 +238,17 @@ struct radeon_winsys { bool absolute, uint64_t timeout); + /* old semaphores - non shareable */ struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws); void (*destroy_sem)(struct radeon_winsys_sem *sem); + /* new shareable sync objects */ + int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle); + void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle); + + int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd); + int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj); + }; static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value) @@ -353,4 +263,9 @@ static inline void radeon_emit_array(struct radeon_winsys_cs *cs, cs->cdw += count; } +static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo) +{ + return bo->va; +} + #endif /* RADV_RADEON_WINSYS_H */