X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_radeon_winsys.h;h=7f19934ab80964aca3e5a4792c90f1fa84526206;hb=0defc5554780a444c9e2009178dc88f97740a174;hp=817371497ed37685ec2722490d5108daf55206c2;hpb=dfc06d2faca4be197f397c0134bc2cb211b2f149;p=mesa.git diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h index 817371497ed..7f19934ab80 100644 --- a/src/amd/vulkan/radv_radeon_winsys.h +++ b/src/amd/vulkan/radv_radeon_winsys.h @@ -29,12 +29,14 @@ #ifndef RADV_RADEON_WINSYS_H #define RADV_RADEON_WINSYS_H +#include #include #include #include #include "main/macros.h" #include "amd_family.h" +struct radeon_info; struct ac_surf_info; struct radeon_surf; @@ -50,7 +52,11 @@ enum radeon_bo_flag { /* bitfield */ RADEON_FLAG_GTT_WC = (1 << 0), RADEON_FLAG_CPU_ACCESS = (1 << 1), RADEON_FLAG_NO_CPU_ACCESS = (1 << 2), - RADEON_FLAG_VIRTUAL = (1 << 3) + RADEON_FLAG_VIRTUAL = (1 << 3), + RADEON_FLAG_VA_UNCACHED = (1 << 4), + RADEON_FLAG_IMPLICIT_SYNC = (1 << 5), + RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6), + RADEON_FLAG_READ_ONLY = (1 << 7), }; enum radeon_bo_usage { /* bitfield */ @@ -68,67 +74,33 @@ enum ring_type { RING_LAST, }; +enum radeon_ctx_priority { + RADEON_CTX_PRIORITY_INVALID = -1, + RADEON_CTX_PRIORITY_LOW = 0, + RADEON_CTX_PRIORITY_MEDIUM, + RADEON_CTX_PRIORITY_HIGH, + RADEON_CTX_PRIORITY_REALTIME, +}; + +enum radeon_value_id { + RADEON_TIMESTAMP, + RADEON_NUM_BYTES_MOVED, + RADEON_NUM_EVICTIONS, + RADEON_NUM_VRAM_CPU_PAGE_FAULTS, + RADEON_VRAM_USAGE, + RADEON_VRAM_VIS_USAGE, + RADEON_GTT_USAGE, + RADEON_GPU_TEMPERATURE, + RADEON_CURRENT_SCLK, + RADEON_CURRENT_MCLK, +}; + struct radeon_winsys_cs { unsigned cdw; /* Number of used dwords. */ unsigned max_dw; /* Maximum number of dwords. */ uint32_t *buf; /* The base pointer of the chunk. */ }; -struct radeon_info { - /* PCI info: domain:bus:dev:func */ - uint32_t pci_domain; - uint32_t pci_bus; - uint32_t pci_dev; - uint32_t pci_func; - - /* Device info. */ - uint32_t pci_id; - enum radeon_family family; - const char *name; - enum chip_class chip_class; - uint32_t gart_page_size; - uint64_t gart_size; - uint64_t vram_size; - uint64_t visible_vram_size; - bool has_dedicated_vram; - bool has_virtual_memory; - bool gfx_ib_pad_with_type2; - bool has_uvd; - uint32_t sdma_rings; - uint32_t compute_rings; - uint32_t vce_fw_version; - uint32_t vce_harvest_config; - uint32_t clock_crystal_freq; /* in kHz */ - - /* Kernel info. */ - uint32_t drm_major; /* version */ - uint32_t drm_minor; - uint32_t drm_patchlevel; - bool has_userptr; - - /* Shader cores. */ - uint32_t r600_max_quad_pipes; /* wave size / 16 */ - uint32_t max_shader_clock; - uint32_t num_good_compute_units; - uint32_t max_se; /* shader engines */ - uint32_t max_sh_per_se; /* shader arrays per shader engine */ - - /* Render backends (color + depth blocks). */ - uint32_t r300_num_gb_pipes; - uint32_t r300_num_z_pipes; - uint32_t r600_gb_backend_map; /* R600 harvest config */ - bool r600_gb_backend_map_valid; - uint32_t r600_num_banks; - uint32_t num_render_backends; - uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ - uint32_t pipe_interleave_bytes; - uint32_t enabled_rb_mask; /* GCN harvest config */ - - /* Tile modes. */ - uint32_t si_tile_mode_array[32]; - uint32_t cik_macrotile_mode_array[16]; -}; - #define RADEON_SURF_TYPE_MASK 0xFF #define RADEON_SURF_TYPE_SHIFT 0 #define RADEON_SURF_TYPE_1D 0 @@ -157,16 +129,25 @@ struct radeon_bo_metadata { /* Tiling flags describing the texture layout for display code * and DRI sharing. */ - enum radeon_bo_layout microtile; - enum radeon_bo_layout macrotile; - unsigned pipe_config; - unsigned bankw; - unsigned bankh; - unsigned tile_split; - unsigned mtilea; - unsigned num_banks; - unsigned stride; - bool scanout; + union { + struct { + enum radeon_bo_layout microtile; + enum radeon_bo_layout macrotile; + unsigned pipe_config; + unsigned bankw; + unsigned bankh; + unsigned tile_split; + unsigned mtilea; + unsigned num_banks; + unsigned stride; + bool scanout; + } legacy; + + struct { + /* surface flags */ + unsigned swizzle_mode:5; + } gfx9; + } u; /* Additional metadata associated with the buffer, in bytes. * The maximum size is 64 * 4. This is opaque for the winsys & kernel. @@ -176,9 +157,31 @@ struct radeon_bo_metadata { uint32_t metadata[64]; }; -struct radeon_winsys_bo; +uint32_t syncobj_handle; struct radeon_winsys_fence; -struct radeon_winsys_sem; + +struct radeon_winsys_bo { + uint64_t va; + bool is_local; +}; +struct radv_winsys_sem_counts { + uint32_t syncobj_count; + uint32_t sem_count; + uint32_t *syncobj; + struct radeon_winsys_sem **sem; +}; + +struct radv_winsys_sem_info { + bool cs_emit_signal; + bool cs_emit_wait; + struct radv_winsys_sem_counts wait; + struct radv_winsys_sem_counts signal; +}; + +struct radv_winsys_bo_list { + struct radeon_winsys_bo **bos; + unsigned count; +}; struct radeon_winsys { void (*destroy)(struct radeon_winsys *ws); @@ -186,6 +189,14 @@ struct radeon_winsys { void (*query_info)(struct radeon_winsys *ws, struct radeon_info *info); + uint64_t (*query_value)(struct radeon_winsys *ws, + enum radeon_value_id value); + + bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, + unsigned num_registers, uint32_t *out); + + const char *(*get_chip_name)(struct radeon_winsys *ws); + struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws, uint64_t size, unsigned alignment, @@ -195,6 +206,10 @@ struct radeon_winsys { void (*buffer_destroy)(struct radeon_winsys_bo *bo); void *(*buffer_map)(struct radeon_winsys_bo *bo); + struct radeon_winsys_bo *(*buffer_from_ptr)(struct radeon_winsys *ws, + void *pointer, + uint64_t size); + struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws, int fd, unsigned *stride, unsigned *offset); @@ -205,15 +220,14 @@ struct radeon_winsys { void (*buffer_unmap)(struct radeon_winsys_bo *bo); - uint64_t (*buffer_get_va)(struct radeon_winsys_bo *bo); - void (*buffer_set_metadata)(struct radeon_winsys_bo *bo, struct radeon_bo_metadata *md); void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent, uint64_t offset, uint64_t size, struct radeon_winsys_bo *bo, uint64_t bo_offset); - struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws); + struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws, + enum radeon_ctx_priority priority); void (*ctx_destroy)(struct radeon_winsys_ctx *ctx); bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, @@ -236,10 +250,8 @@ struct radeon_winsys { unsigned cs_count, struct radeon_winsys_cs *initial_preamble_cs, struct radeon_winsys_cs *continue_preamble_cs, - struct radeon_winsys_sem **wait_sem, - unsigned wait_sem_count, - struct radeon_winsys_sem **signal_sem, - unsigned signal_sem_count, + struct radv_winsys_sem_info *sem_info, + const struct radv_winsys_bo_list *bo_list, /* optional */ bool can_patch, struct radeon_winsys_fence *fence); @@ -250,7 +262,7 @@ struct radeon_winsys { void (*cs_execute_secondary)(struct radeon_winsys_cs *parent, struct radeon_winsys_cs *child); - void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t trace_id); + void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, const int *trace_ids, int trace_id_count); int (*surface_init)(struct radeon_winsys *ws, const struct ac_surf_info *surf_info, @@ -265,10 +277,33 @@ struct radeon_winsys { struct radeon_winsys_fence *fence, bool absolute, uint64_t timeout); + bool (*fences_wait)(struct radeon_winsys *ws, + struct radeon_winsys_fence *const *fences, + uint32_t fence_count, + bool wait_all, + uint64_t timeout); + /* old semaphores - non shareable */ struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws); void (*destroy_sem)(struct radeon_winsys_sem *sem); + /* new shareable sync objects */ + int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle); + void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle); + + void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle); + void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle); + bool (*wait_syncobj)(struct radeon_winsys *ws, const uint32_t *handles, uint32_t handle_count, + bool wait_all, uint64_t timeout); + + int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int *fd); + int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t *syncobj); + + int (*export_syncobj_to_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int *fd); + + /* Note that this, unlike the normal import, uses an existing syncobj. */ + int (*import_syncobj_from_sync_file)(struct radeon_winsys *ws, uint32_t syncobj, int fd); + }; static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value) @@ -283,4 +318,20 @@ static inline void radeon_emit_array(struct radeon_winsys_cs *cs, cs->cdw += count; } +static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo) +{ + return bo->va; +} + +static inline void radv_cs_add_buffer(struct radeon_winsys *ws, + struct radeon_winsys_cs *cs, + struct radeon_winsys_bo *bo, + uint8_t priority) +{ + if (bo->is_local) + return; + + ws->cs_add_buffer(cs, bo, priority); +} + #endif /* RADV_RADEON_WINSYS_H */