X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_shader.c;h=3af15d4e8446b92217c370eac13811e127174977;hb=6c1108d25b46ddf7789b2c9f9f7b0a79b3e279a0;hp=5166ecc15abe2b90ff679ae977820e75e1d122e3;hpb=49f5ddd3aeee948db85f2b8e67167753a9d48e56;p=mesa.git diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 5166ecc15ab..3af15d4e844 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -31,14 +31,11 @@ #include "radv_private.h" #include "radv_shader.h" #include "radv_shader_helper.h" +#include "radv_shader_args.h" #include "nir/nir.h" #include "nir/nir_builder.h" #include "spirv/nir_spirv.h" -#include -#include -#include - #include "sid.h" #include "ac_binary.h" #include "ac_llvm_util.h" @@ -48,9 +45,11 @@ #include "util/debug.h" #include "ac_exp_param.h" +#include "aco_interface.h" + #include "util/string_buffer.h" -static const struct nir_shader_compiler_options nir_options = { +static const struct nir_shader_compiler_options nir_options_llvm = { .vertex_id_zero_based = true, .lower_scmp = true, .lower_flrp16 = true, @@ -59,6 +58,7 @@ static const struct nir_shader_compiler_options nir_options = { .lower_device_index_to_zero = true, .lower_fsat = true, .lower_fdiv = true, + .lower_fmod = true, .lower_bitfield_insert_to_bitfield_select = true, .lower_bitfield_extract = true, .lower_sub = true, @@ -78,6 +78,58 @@ static const struct nir_shader_compiler_options nir_options = { .lower_rotate = true, .max_unroll_iterations = 32, .use_interpolated_input_intrinsics = true, + /* nir_lower_int64() isn't actually called for the LLVM backend, but + * this helps the loop unrolling heuristics. */ + .lower_int64_options = nir_lower_imul64 | + nir_lower_imul_high64 | + nir_lower_imul_2x32_64 | + nir_lower_divmod64 | + nir_lower_minmax64 | + nir_lower_iabs64, + .lower_doubles_options = nir_lower_drcp | + nir_lower_dsqrt | + nir_lower_drsq | + nir_lower_ddiv, +}; + +static const struct nir_shader_compiler_options nir_options_aco = { + .vertex_id_zero_based = true, + .lower_scmp = true, + .lower_flrp16 = true, + .lower_flrp32 = true, + .lower_flrp64 = true, + .lower_device_index_to_zero = true, + .lower_fdiv = true, + .lower_fmod = true, + .lower_bitfield_insert_to_bitfield_select = true, + .lower_bitfield_extract = true, + .lower_pack_snorm_2x16 = true, + .lower_pack_snorm_4x8 = true, + .lower_pack_unorm_2x16 = true, + .lower_pack_unorm_4x8 = true, + .lower_unpack_snorm_2x16 = true, + .lower_unpack_snorm_4x8 = true, + .lower_unpack_unorm_2x16 = true, + .lower_unpack_unorm_4x8 = true, + .lower_unpack_half_2x16 = true, + .lower_extract_byte = true, + .lower_extract_word = true, + .lower_ffma = true, + .lower_fpow = true, + .lower_mul_2x32_64 = true, + .lower_rotate = true, + .max_unroll_iterations = 32, + .use_interpolated_input_intrinsics = true, + .lower_int64_options = nir_lower_imul64 | + nir_lower_imul_high64 | + nir_lower_imul_2x32_64 | + nir_lower_divmod64 | + nir_lower_minmax64 | + nir_lower_iabs64, + .lower_doubles_options = nir_lower_drcp | + nir_lower_dsqrt | + nir_lower_drsq | + nir_lower_ddiv, }; bool @@ -87,9 +139,11 @@ radv_can_dump_shader(struct radv_device *device, { if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)) return false; + if (module) + return !module->nir || + (device->instance->debug_flags & RADV_DEBUG_DUMP_META_SHADERS); - /* Only dump non-meta shaders, useful for debugging purposes. */ - return (module && !module->nir) || is_gs_copy_shader; + return is_gs_copy_shader; } bool @@ -101,29 +155,6 @@ radv_can_dump_shader_stats(struct radv_device *device, module && !module->nir; } -unsigned shader_io_get_unique_index(gl_varying_slot slot) -{ - /* handle patch indices separate */ - if (slot == VARYING_SLOT_TESS_LEVEL_OUTER) - return 0; - if (slot == VARYING_SLOT_TESS_LEVEL_INNER) - return 1; - if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX) - return 2 + (slot - VARYING_SLOT_PATCH0); - if (slot == VARYING_SLOT_POS) - return 0; - if (slot == VARYING_SLOT_PSIZ) - return 1; - if (slot == VARYING_SLOT_CLIP_DIST0) - return 2; - if (slot == VARYING_SLOT_CLIP_DIST1) - return 3; - /* 3 is reserved for clip dist as well */ - if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31) - return 4 + (slot - VARYING_SLOT_VAR0); - unreachable("illegal slot in get unique index\n"); -} - VkResult radv_CreateShaderModule( VkDevice _device, const VkShaderModuleCreateInfo* pCreateInfo, @@ -136,12 +167,15 @@ VkResult radv_CreateShaderModule( assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO); assert(pCreateInfo->flags == 0); - module = vk_alloc2(&device->alloc, pAllocator, + module = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*module) + pCreateInfo->codeSize, 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); if (module == NULL) return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); + vk_object_base_init(&device->vk, &module->base, + VK_OBJECT_TYPE_SHADER_MODULE); + module->nir = NULL; module->size = pCreateInfo->codeSize; memcpy(module->data, pCreateInfo->pCode, module->size); @@ -164,7 +198,8 @@ void radv_DestroyShaderModule( if (!module) return; - vk_free2(&device->alloc, pAllocator, module); + vk_object_base_finish(&module->base); + vk_free2(&device->vk.alloc, pAllocator, module); } void @@ -198,9 +233,10 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively, NIR_PASS(progress, shader, nir_opt_copy_prop_vars); NIR_PASS(progress, shader, nir_opt_dead_write_vars); NIR_PASS(progress, shader, nir_remove_dead_variables, - nir_var_function_temp); + nir_var_function_temp | nir_var_shader_in | nir_var_shader_out, + NULL); - NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL); + NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL); NIR_PASS_V(shader, nir_lower_phis_to_scalar); NIR_PASS(progress, shader, nir_copy_prop); @@ -250,6 +286,17 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively, NIR_PASS(progress, shader, nir_opt_move, nir_move_load_ubo); } +static void +shared_var_info(const struct glsl_type *type, unsigned *size, unsigned *align) +{ + assert(glsl_type_is_vector_or_scalar(type)); + + uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8; + unsigned length = glsl_get_vector_elements(type); + *size = comp_size * length, + *align = comp_size; +} + nir_shader * radv_shader_compile_to_nir(struct radv_device *device, struct radv_shader_module *module, @@ -257,15 +304,20 @@ radv_shader_compile_to_nir(struct radv_device *device, gl_shader_stage stage, const VkSpecializationInfo *spec_info, const VkPipelineCreateFlags flags, - const struct radv_pipeline_layout *layout) + const struct radv_pipeline_layout *layout, + unsigned subgroup_size, unsigned ballot_bit_size) { nir_shader *nir; + const nir_shader_compiler_options *nir_options = + device->physical_device->use_llvm ? &nir_options_llvm : + &nir_options_aco; + if (module->nir) { /* Some things such as our meta clear/blit code will give us a NIR * shader directly. In that case, we just ignore the SPIR-V entirely * and just use the NIR shader */ nir = module->nir; - nir->options = &nir_options; + nir->options = nir_options; nir_validate_shader(nir, "in internal shader"); assert(exec_list_length(&nir->functions) == 1); @@ -274,50 +326,73 @@ radv_shader_compile_to_nir(struct radv_device *device, assert(module->size % 4 == 0); if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV) - radv_print_spirv(spirv, module->size, stderr); + radv_print_spirv(module->data, module->size, stderr); uint32_t num_spec_entries = 0; struct nir_spirv_specialization *spec_entries = NULL; if (spec_info && spec_info->mapEntryCount > 0) { num_spec_entries = spec_info->mapEntryCount; - spec_entries = malloc(num_spec_entries * sizeof(*spec_entries)); + spec_entries = calloc(num_spec_entries, sizeof(*spec_entries)); for (uint32_t i = 0; i < num_spec_entries; i++) { VkSpecializationMapEntry entry = spec_info->pMapEntries[i]; const void *data = spec_info->pData + entry.offset; assert(data + entry.size <= spec_info->pData + spec_info->dataSize); spec_entries[i].id = spec_info->pMapEntries[i].constantID; - if (spec_info->dataSize == 8) - spec_entries[i].data64 = *(const uint64_t *)data; - else - spec_entries[i].data32 = *(const uint32_t *)data; + switch (entry.size) { + case 8: + spec_entries[i].value.u64 = *(const uint64_t *)data; + break; + case 4: + spec_entries[i].value.u32 = *(const uint32_t *)data; + break; + case 2: + spec_entries[i].value.u16 = *(const uint16_t *)data; + break; + case 1: + spec_entries[i].value.u8 = *(const uint8_t *)data; + break; + default: + assert(!"Invalid spec constant size"); + break; + } } } const struct spirv_to_nir_options spirv_options = { .lower_ubo_ssbo_access_to_offsets = true, .caps = { + .amd_fragment_mask = true, .amd_gcn_shader = true, - .amd_shader_ballot = device->physical_device->use_shader_ballot, + .amd_image_gather_bias_lod = true, + .amd_image_read_write_lod = true, + .amd_shader_ballot = true, + .amd_shader_explicit_vertex_parameter = true, .amd_trinary_minmax = true, + .demote_to_helper_invocation = true, .derivative_group = true, .descriptor_array_dynamic_indexing = true, .descriptor_array_non_uniform_indexing = true, .descriptor_indexing = true, .device_group = true, .draw_parameters = true, - .float16 = true, + .float_controls = true, + .float16 = device->physical_device->rad_info.has_packed_math_16bit, + .float32_atomic_add = true, .float64 = true, .geometry_streams = true, + .image_ms_array = true, .image_read_without_format = true, .image_write_without_format = true, .int8 = true, .int16 = true, .int64 = true, .int64_atomics = true, + .min_lod = true, .multiview = true, .physical_storage_buffer_address = true, .post_depth_coverage = true, .runtime_descriptor_array = true, + .shader_clock = true, .shader_viewport_index_layer = true, .stencil_export = true, .storage_8bit = true, @@ -343,7 +418,7 @@ radv_shader_compile_to_nir(struct radv_device *device, nir = spirv_to_nir(spirv, module->size / 4, spec_entries, num_spec_entries, stage, entrypoint_name, - &spirv_options, &nir_options); + &spirv_options, nir_options); assert(nir->info.stage == stage); nir_validate_shader(nir, "after spirv_to_nir"); @@ -353,7 +428,7 @@ radv_shader_compile_to_nir(struct radv_device *device, * inline functions. That way they get properly initialized at the top * of the function and not at the top of its caller. */ - NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp); + NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp); NIR_PASS_V(nir, nir_lower_returns); NIR_PASS_V(nir, nir_inline_functions); NIR_PASS_V(nir, nir_opt_deref); @@ -370,12 +445,12 @@ radv_shader_compile_to_nir(struct radv_device *device, /* Make sure we lower constant initializers on output variables so that * nir_remove_dead_variables below sees the corresponding stores */ - NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out); + NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_shader_out); /* Now that we've deleted all but the main function, we can go ahead and * lower the rest of the constant initializers. */ - NIR_PASS_V(nir, nir_lower_constant_initializers, ~0); + NIR_PASS_V(nir, nir_lower_variable_initializers, ~0); /* Split member structs. We do this before lower_io_to_temporaries so that * it doesn't lower system values to temporaries by accident. @@ -383,15 +458,36 @@ radv_shader_compile_to_nir(struct radv_device *device, NIR_PASS_V(nir, nir_split_var_copies); NIR_PASS_V(nir, nir_split_per_member_structs); + if (nir->info.stage == MESA_SHADER_FRAGMENT && + !device->physical_device->use_llvm) + NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out); if (nir->info.stage == MESA_SHADER_FRAGMENT) NIR_PASS_V(nir, nir_lower_input_attachments, true); NIR_PASS_V(nir, nir_remove_dead_variables, - nir_var_shader_in | nir_var_shader_out | nir_var_system_value); + nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared, + NULL); + + NIR_PASS_V(nir, nir_propagate_invariant); NIR_PASS_V(nir, nir_lower_system_values); NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays); NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout); + if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE) + NIR_PASS_V(nir, nir_lower_discard_to_demote); + + nir_lower_doubles_options lower_doubles = + nir->options->lower_doubles_options; + + if (device->physical_device->rad_info.chip_class == GFX6) { + /* GFX6 doesn't support v_floor_f64 and the precision + * of v_fract_f64 which is used to implement 64-bit + * floor is less than what Vulkan requires. + */ + lower_doubles |= nir_lower_dfloor; + } + + NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles); } /* Vulkan uses the separate-shader linking model */ @@ -399,6 +495,9 @@ radv_shader_compile_to_nir(struct radv_device *device, nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); + if (nir->info.stage == MESA_SHADER_GEOMETRY) + nir_lower_gs_intrinsics(nir, true); + static const nir_lower_tex_options tex_options = { .lower_txp = ~0, .lower_tg4_offsets = true, @@ -421,15 +520,19 @@ radv_shader_compile_to_nir(struct radv_device *device, nir_split_var_copies(nir); nir_lower_global_vars_to_local(nir); - nir_remove_dead_variables(nir, nir_var_function_temp); + nir_remove_dead_variables(nir, nir_var_function_temp, NULL); + bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7; nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) { - .subgroup_size = 64, - .ballot_bit_size = 64, + .subgroup_size = subgroup_size, + .ballot_bit_size = ballot_bit_size, .lower_to_scalar = 1, .lower_subgroup_masks = 1, .lower_shuffle = 1, .lower_shuffle_to_32bit = 1, .lower_vote_eq_to_ballot = 1, + .lower_quad_broadcast_dynamic = 1, + .lower_quad_broadcast_dynamic_to_const = gfx7minus, + .lower_shuffle_to_swizzle_amd = 1, }); nir_lower_load_const_to_scalar(nir); @@ -442,6 +545,21 @@ radv_shader_compile_to_nir(struct radv_device *device, */ nir_lower_var_copies(nir); + /* Lower deref operations for compute shared memory. */ + if (nir->info.stage == MESA_SHADER_COMPUTE) { + NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, + nir_var_mem_shared, shared_var_info); + NIR_PASS_V(nir, nir_lower_explicit_io, + nir_var_mem_shared, nir_address_format_32bit_offset); + } + + /* Lower large variables that are always constant with load_constant + * intrinsics, which get turned into PC-relative loads from a data + * section next to the shader. + */ + NIR_PASS_V(nir, nir_opt_large_constants, + glsl_get_natural_size_align_bytes, 16); + /* Indirect lowering must be called after the radv_optimize_nir() loop * has been called at least once. Otherwise indirect lowering can * bloat the instruction count of the loop and cause it to be @@ -453,53 +571,6 @@ radv_shader_compile_to_nir(struct radv_device *device, return nir; } -static void mark_16bit_fs_input(struct radv_shader_variant_info *shader_info, - const struct glsl_type *type, - int location) -{ - if (glsl_type_is_scalar(type) || glsl_type_is_vector(type) || glsl_type_is_matrix(type)) { - unsigned attrib_count = glsl_count_attribute_slots(type, false); - if (glsl_type_is_16bit(type)) { - shader_info->fs.float16_shaded_mask |= ((1ull << attrib_count) - 1) << location; - } - } else if (glsl_type_is_array(type)) { - unsigned stride = glsl_count_attribute_slots(glsl_get_array_element(type), false); - for (unsigned i = 0; i < glsl_get_length(type); ++i) { - mark_16bit_fs_input(shader_info, glsl_get_array_element(type), location + i * stride); - } - } else { - assert(glsl_type_is_struct_or_ifc(type)); - for (unsigned i = 0; i < glsl_get_length(type); i++) { - mark_16bit_fs_input(shader_info, glsl_get_struct_field(type, i), location); - location += glsl_count_attribute_slots(glsl_get_struct_field(type, i), false); - } - } -} - -static void -handle_fs_input_decl(struct radv_shader_variant_info *shader_info, - struct nir_variable *variable) -{ - unsigned attrib_count = glsl_count_attribute_slots(variable->type, false); - - if (variable->data.compact) { - unsigned component_count = variable->data.location_frac + - glsl_get_length(variable->type); - attrib_count = (component_count + 3) / 4; - } else { - mark_16bit_fs_input(shader_info, variable->type, - variable->data.driver_location); - } - - uint64_t mask = ((1ull << attrib_count) - 1); - - if (variable->data.interpolation == INTERP_MODE_FLAT) - shader_info->fs.flat_shaded_mask |= mask << variable->data.driver_location; - - if (variable->data.location >= VARYING_SLOT_VAR0) - shader_info->fs.input_mask |= mask << (variable->data.location - VARYING_SLOT_VAR0); -} - static int type_size_vec4(const struct glsl_type *type, bool bindless) { @@ -567,28 +638,13 @@ lower_view_index(nir_shader *nir) return progress; } -/* Gather information needed to setup the vs<->ps linking registers in - * radv_pipeline_generate_ps_inputs(). - */ - -static void -handle_fs_inputs(nir_shader *nir, struct radv_shader_variant_info *shader_info) -{ - shader_info->fs.num_interp = nir->num_inputs; - - nir_foreach_variable(variable, &nir->inputs) - handle_fs_input_decl(shader_info, variable); -} - -static void -lower_fs_io(nir_shader *nir, struct radv_shader_variant_info *shader_info) +void +radv_lower_fs_io(nir_shader *nir) { NIR_PASS_V(nir, lower_view_index); nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs, MESA_SHADER_FRAGMENT); - handle_fs_inputs(nir, shader_info); - NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0); /* This pass needs actual constants */ @@ -598,7 +654,7 @@ lower_fs_io(nir_shader *nir, struct radv_shader_variant_info *shader_info) } -void * +static void * radv_alloc_shader_memory(struct radv_device *device, struct radv_shader_variant *shader) { @@ -615,7 +671,7 @@ radv_alloc_shader_memory(struct radv_device *device, } offset = align_u64(s->bo_offset + s->code_size, 256); } - if (slab->size - offset >= shader->code_size) { + if (offset <= slab->size && slab->size - offset >= shader->code_size) { shader->bo = slab->bo; shader->bo_offset = offset; list_addtail(&shader->slab_list, &slab->shaders); @@ -627,14 +683,25 @@ radv_alloc_shader_memory(struct radv_device *device, mtx_unlock(&device->shader_slab_mutex); struct radv_shader_slab *slab = calloc(1, sizeof(struct radv_shader_slab)); - slab->size = 256 * 1024; + slab->size = MAX2(256 * 1024, shader->code_size); slab->bo = device->ws->buffer_create(device->ws, slab->size, 256, RADEON_DOMAIN_VRAM, RADEON_FLAG_NO_INTERPROCESS_SHARING | (device->physical_device->rad_info.cpdma_prefetch_writes_memory ? 0 : RADEON_FLAG_READ_ONLY), RADV_BO_PRIORITY_SHADER); + if (!slab->bo) { + free(slab); + return NULL; + } + slab->ptr = (char*)device->ws->buffer_map(slab->bo); + if (!slab->ptr) { + device->ws->buffer_destroy(slab->bo); + free(slab); + return NULL; + } + list_inithead(&slab->shaders); mtx_lock(&device->shader_slab_mutex); @@ -669,7 +736,7 @@ radv_get_shader_binary_size(size_t code_size) static void radv_postprocess_config(const struct radv_physical_device *pdevice, const struct ac_shader_config *config_in, - const struct radv_shader_variant_info *info, + const struct radv_shader_info *info, gl_shader_stage stage, struct ac_shader_config *config_out) { @@ -678,73 +745,36 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, unsigned num_input_vgprs = info->num_input_vgprs; if (stage == MESA_SHADER_FRAGMENT) { - num_input_vgprs = 0; - if (G_0286CC_PERSP_SAMPLE_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 2; - if (G_0286CC_PERSP_CENTER_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 2; - if (G_0286CC_PERSP_CENTROID_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 2; - if (G_0286CC_PERSP_PULL_MODEL_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 3; - if (G_0286CC_LINEAR_SAMPLE_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 2; - if (G_0286CC_LINEAR_CENTER_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 2; - if (G_0286CC_LINEAR_CENTROID_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 2; - if (G_0286CC_LINE_STIPPLE_TEX_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 1; - if (G_0286CC_POS_X_FLOAT_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 1; - if (G_0286CC_POS_Y_FLOAT_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 1; - if (G_0286CC_POS_Z_FLOAT_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 1; - if (G_0286CC_POS_W_FLOAT_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 1; - if (G_0286CC_FRONT_FACE_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 1; - if (G_0286CC_ANCILLARY_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 1; - if (G_0286CC_SAMPLE_COVERAGE_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 1; - if (G_0286CC_POS_FIXED_PT_ENA(config_in->spi_ps_input_addr)) - num_input_vgprs += 1; + num_input_vgprs = ac_get_fs_input_vgpr_cnt(config_in, NULL, NULL); } unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs); /* +3 for scratch wave offset and VCC */ unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3); + unsigned num_shared_vgprs = config_in->num_shared_vgprs; + /* shared VGPRs are introduced in Navi and are allocated in blocks of 8 (RDNA ref 3.6.5) */ + assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0) + || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0)); + unsigned num_shared_vgpr_blocks = num_shared_vgprs / 8; *config_out = *config_in; config_out->num_vgprs = num_vgprs; config_out->num_sgprs = num_sgprs; - - /* Enable 64-bit and 16-bit denormals, because there is no performance - * cost. - * - * If denormals are enabled, all floating-point output modifiers are - * ignored. - * - * Don't enable denormals for 32-bit floats, because: - * - Floating-point output modifiers would be ignored by the hw. - * - Some opcodes don't support denormals, such as v_mad_f32. We would - * have to stop using those. - * - GFX6 & GFX7 would be very slow. - */ - config_out->float_mode |= V_00B028_FP_64_DENORMS; + config_out->num_shared_vgprs = num_shared_vgprs; config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) | - S_00B12C_SCRATCH_EN(scratch_enabled) | - S_00B12C_SO_BASE0_EN(!!info->info.so.strides[0]) | - S_00B12C_SO_BASE1_EN(!!info->info.so.strides[1]) | - S_00B12C_SO_BASE2_EN(!!info->info.so.strides[2]) | - S_00B12C_SO_BASE3_EN(!!info->info.so.strides[3]) | - S_00B12C_SO_EN(!!info->info.so.num_outputs); + S_00B12C_SCRATCH_EN(scratch_enabled); + + if (!pdevice->use_ngg_streamout) { + config_out->rsrc2 |= S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) | + S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) | + S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) | + S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) | + S_00B12C_SO_EN(!!info->so.num_outputs); + } config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / - (info->info.wave_size == 32 ? 8 : 4)) | + (info->wave_size == 32 ? 8 : 4)) | S_00B848_DX10_CLAMP(1) | S_00B848_FLOAT_MODE(config_out->float_mode); @@ -762,16 +792,17 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1); } else if (info->tes.as_es) { assert(pdevice->rad_info.chip_class <= GFX8); - vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2; + vgpr_comp_cnt = info->uses_prim_id ? 3 : 2; config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1); } else { - bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id; + bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id; vgpr_comp_cnt = enable_prim_id ? 3 : 2; config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1); } + config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks); break; case MESA_SHADER_TESS_CTRL: if (pdevice->rad_info.chip_class >= GFX9) { @@ -780,15 +811,16 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded. */ if (pdevice->rad_info.chip_class >= GFX10) { - vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3 : 1; + vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 1; } else { - vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1; + vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1; } } else { config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1); } config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) | S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10); + config_out->rsrc2 |= S_00B42C_SHARED_VGPR_CNT(num_shared_vgpr_blocks); break; case MESA_SHADER_VERTEX: if (info->is_ngg) { @@ -799,21 +831,21 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID). * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded. */ - vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1; + vgpr_comp_cnt = info->vs.needs_instance_id ? 2 : 1; } else if (info->vs.as_es) { assert(pdevice->rad_info.chip_class <= GFX8); /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */ - vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0; + vgpr_comp_cnt = info->vs.needs_instance_id ? 1 : 0; } else { /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID) * If PrimID is disabled. InstanceID / StepRate1 is loaded instead. * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded. */ - if (info->info.vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) { + if (info->vs.needs_instance_id && pdevice->rad_info.chip_class >= GFX10) { vgpr_comp_cnt = 3; } else if (info->vs.export_prim_id) { vgpr_comp_cnt = 2; - } else if (info->info.vs.needs_instance_id) { + } else if (info->vs.needs_instance_id) { vgpr_comp_cnt = 1; } else { vgpr_comp_cnt = 0; @@ -821,25 +853,30 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); } + config_out->rsrc2 |= S_00B12C_SHARED_VGPR_CNT(num_shared_vgpr_blocks); break; case MESA_SHADER_FRAGMENT: config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); + config_out->rsrc2 |= S_00B02C_SHARED_VGPR_CNT(num_shared_vgpr_blocks); break; case MESA_SHADER_GEOMETRY: config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) | S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10); + config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks); break; case MESA_SHADER_COMPUTE: config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) | S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10); config_out->rsrc2 |= - S_00B84C_TGID_X_EN(info->info.cs.uses_block_id[0]) | - S_00B84C_TGID_Y_EN(info->info.cs.uses_block_id[1]) | - S_00B84C_TGID_Z_EN(info->info.cs.uses_block_id[2]) | - S_00B84C_TIDIG_COMP_CNT(info->info.cs.uses_thread_id[2] ? 2 : - info->info.cs.uses_thread_id[1] ? 1 : 0) | - S_00B84C_TG_SIZE_EN(info->info.cs.uses_local_invocation_idx) | + S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) | + S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) | + S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) | + S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 : + info->cs.uses_thread_id[1] ? 1 : 0) | + S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) | S_00B84C_LDS_SIZE(config_in->lds_size); + config_out->rsrc3 |= S_00B8A0_SHARED_VGPR_CNT(num_shared_vgpr_blocks); + break; default: unreachable("unsupported shader type"); @@ -855,18 +892,18 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */ if (es_stage == MESA_SHADER_VERTEX) { - es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3 : 0; + es_vgpr_comp_cnt = info->vs.needs_instance_id ? 3 : 0; } else if (es_stage == MESA_SHADER_TESS_EVAL) { - bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id; + bool enable_prim_id = info->tes.export_prim_id || info->uses_prim_id; es_vgpr_comp_cnt = enable_prim_id ? 3 : 2; } else unreachable("Unexpected ES shader stage"); bool tes_triangles = stage == MESA_SHADER_TESS_EVAL && info->tes.primitive_mode >= 4; /* GL_TRIANGLES */ - if (info->info.uses_invocation_id || stage == MESA_SHADER_VERTEX) { + if (info->uses_invocation_id || stage == MESA_SHADER_VERTEX) { gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */ - } else if (info->info.uses_prim_id) { + } else if (info->uses_prim_id) { gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */ } else if (info->gs.vertices_in >= 3 || tes_triangles) { gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */ @@ -886,13 +923,13 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, if (es_type == MESA_SHADER_VERTEX) { /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */ - if (info->info.vs.needs_instance_id) { + if (info->vs.needs_instance_id) { es_vgpr_comp_cnt = pdevice->rad_info.chip_class >= GFX10 ? 3 : 1; } else { es_vgpr_comp_cnt = 0; } } else if (es_type == MESA_SHADER_TESS_EVAL) { - es_vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2; + es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2; } else { unreachable("invalid shader ES type"); } @@ -900,9 +937,9 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and * VGPR[0:4] are always loaded. */ - if (info->info.uses_invocation_id) { + if (info->uses_invocation_id) { gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */ - } else if (info->info.uses_prim_id) { + } else if (info->uses_prim_id) { gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */ } else if (info->gs.vertices_in >= 3) { gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */ @@ -921,38 +958,6 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, } } -static void radv_init_llvm_target() -{ - LLVMInitializeAMDGPUTargetInfo(); - LLVMInitializeAMDGPUTarget(); - LLVMInitializeAMDGPUTargetMC(); - LLVMInitializeAMDGPUAsmPrinter(); - - /* For inline assembly. */ - LLVMInitializeAMDGPUAsmParser(); - - /* Workaround for bug in llvm 4.0 that causes image intrinsics - * to disappear. - * https://reviews.llvm.org/D26348 - * - * Workaround for bug in llvm that causes the GPU to hang in presence - * of nested loops because there is an exec mask issue. The proper - * solution is to fix LLVM but this might require a bunch of work. - * https://bugs.llvm.org/show_bug.cgi?id=37744 - * - * "mesa" is the prefix for error messages. - */ - const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" }; - LLVMParseCommandLineOptions(2, argv, NULL); -} - -static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT; - -static void radv_init_llvm_once(void) -{ - call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target); -} - struct radv_shader_variant * radv_shader_variant_create(struct radv_device *device, const struct radv_shader_binary *binary, @@ -967,50 +972,35 @@ radv_shader_variant_create(struct radv_device *device, variant->ref_count = 1; if (binary->type == RADV_BINARY_TYPE_RTLD) { - struct ac_rtld_symbol lds_symbols[1]; + struct ac_rtld_symbol lds_symbols[2]; unsigned num_lds_symbols = 0; const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data; size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size; - unsigned esgs_ring_size = 0; if (device->physical_device->rad_info.chip_class >= GFX9 && - binary->stage == MESA_SHADER_GEOMETRY && !binary->is_gs_copy_shader) { - /* TODO: Do not hardcode this value */ - esgs_ring_size = 32 * 1024; - } - - if (binary->variant_info.is_ngg) { - /* GS stores Primitive IDs into LDS at the address - * corresponding to the ES thread of the provoking - * vertex. All ES threads load and export PrimitiveID - * for their thread. - */ - if (binary->stage == MESA_SHADER_VERTEX && - binary->variant_info.vs.export_prim_id) { - /* TODO: Do not harcode this value */ - esgs_ring_size = 256 /* max_out_verts */ * 4; - } - } - - if (esgs_ring_size) { + (binary->stage == MESA_SHADER_GEOMETRY || binary->info.is_ngg) && + !binary->is_gs_copy_shader) { /* We add this symbol even on LLVM <= 8 to ensure that * shader->config.lds_size is set correctly below. */ struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++]; sym->name = "esgs_ring"; - sym->size = esgs_ring_size; + sym->size = binary->info.ngg_info.esgs_ring_size; sym->align = 64 * 1024; + } - /* Make sure to have LDS space for NGG scratch. */ - /* TODO: Compute this correctly somehow? */ - if (binary->variant_info.is_ngg) - sym->size -= 32; + if (binary->info.is_ngg && + binary->stage == MESA_SHADER_GEOMETRY) { + struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++]; + sym->name = "ngg_emit"; + sym->size = binary->info.ngg_info.ngg_emit_size * 4; + sym->align = 4; } struct ac_rtld_open_info open_info = { .info = &device->physical_device->rad_info, .shader_type = binary->stage, - .wave_size = binary->variant_info.info.wave_size, + .wave_size = binary->info.wave_size, .num_parts = 1, .elf_ptrs = &elf_data, .elf_sizes = &elf_size, @@ -1023,7 +1013,8 @@ radv_shader_variant_create(struct radv_device *device, return NULL; } - if (!ac_rtld_read_config(&rtld_binary, &config)) { + if (!ac_rtld_read_config(&device->physical_device->rad_info, + &rtld_binary, &config)) { ac_rtld_close(&rtld_binary); free(variant); return NULL; @@ -1035,17 +1026,25 @@ radv_shader_variant_create(struct radv_device *device, } variant->code_size = rtld_binary.rx_size; + variant->exec_size = rtld_binary.exec_size; } else { assert(binary->type == RADV_BINARY_TYPE_LEGACY); config = ((struct radv_shader_binary_legacy *)binary)->config; - variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size); + variant->code_size = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size); + variant->exec_size = ((struct radv_shader_binary_legacy *)binary)->exec_size; } - variant->info = binary->variant_info; - radv_postprocess_config(device->physical_device, &config, &binary->variant_info, + variant->info = binary->info; + radv_postprocess_config(device->physical_device, &config, &binary->info, binary->stage, &variant->config); - + void *dest_ptr = radv_alloc_shader_memory(device, variant); + if (!dest_ptr) { + if (binary->type == RADV_BINARY_TYPE_RTLD) + ac_rtld_close(&rtld_binary); + free(variant); + return NULL; + } if (binary->type == RADV_BINARY_TYPE_RTLD) { struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary; @@ -1071,7 +1070,7 @@ radv_shader_variant_create(struct radv_device *device, return NULL; } - variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL; + variant->ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL; variant->disasm_string = malloc(disasm_size + 1); memcpy(variant->disasm_string, disasm_data, disasm_size); variant->disasm_string[disasm_size] = 0; @@ -1080,15 +1079,20 @@ radv_shader_variant_create(struct radv_device *device, ac_rtld_close(&rtld_binary); } else { struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary; - memcpy(dest_ptr, bin->data, bin->code_size); + memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size); /* Add end-of-code markers for the UMR disassembler. */ uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4; for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++) ptr32[i] = DEBUGGER_END_OF_CODE_MARKER; - variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL; - variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->llvm_ir_size)) : NULL; + variant->ir_string = bin->ir_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size)) : NULL; + variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->stats_size + bin->code_size + bin->ir_size)) : NULL; + + if (bin->stats_size) { + variant->statistics = calloc(bin->stats_size, 1); + memcpy(variant->statistics, bin->data, bin->stats_size); + } } return variant; } @@ -1122,68 +1126,52 @@ shader_variant_compile(struct radv_device *device, struct nir_shader * const *shaders, int shader_count, gl_shader_stage stage, + struct radv_shader_info *info, struct radv_nir_compiler_options *options, bool gs_copy_shader, bool keep_shader_info, + bool keep_statistic_info, struct radv_shader_binary **binary_out) { enum radeon_family chip_family = device->physical_device->rad_info.family; - enum ac_target_machine_options tm_options = 0; - struct ac_llvm_compiler ac_llvm; struct radv_shader_binary *binary = NULL; - struct radv_shader_variant_info variant_info = {0}; - bool thread_compiler; - - if (shaders[0]->info.stage == MESA_SHADER_FRAGMENT) - lower_fs_io(shaders[0], &variant_info); options->family = chip_family; options->chip_class = device->physical_device->rad_info.chip_class; options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader); options->dump_preoptir = options->dump_shader && device->instance->debug_flags & RADV_DEBUG_PREOPTIR; - options->record_llvm_ir = keep_shader_info; + options->record_ir = keep_shader_info; + options->record_stats = keep_statistic_info; options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR; options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size; options->address32_hi = device->physical_device->rad_info.address32_hi; options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug; - - if ((stage == MESA_SHADER_GEOMETRY && !options->key.vs_common_out.as_ngg) || - gs_copy_shader) - options->wave_size = 64; - else if (stage == MESA_SHADER_COMPUTE) - options->wave_size = device->physical_device->cs_wave_size; - else if (stage == MESA_SHADER_FRAGMENT) - options->wave_size = device->physical_device->ps_wave_size; - else - options->wave_size = device->physical_device->ge_wave_size; - - if (options->supports_spill) - tm_options |= AC_TM_SUPPORTS_SPILL; - if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED) - tm_options |= AC_TM_SISCHED; - if (options->check_ir) - tm_options |= AC_TM_CHECK_IR; - if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT) - tm_options |= AC_TM_NO_LOAD_STORE_OPT; - - thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM); - radv_init_llvm_once(); - radv_init_llvm_compiler(&ac_llvm, - thread_compiler, - chip_family, tm_options, - options->wave_size); - if (gs_copy_shader) { - assert(shader_count == 1); - radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary, - &variant_info, options); + options->use_ngg_streamout = device->physical_device->use_ngg_streamout; + options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup; + + struct radv_shader_args args = {}; + args.options = options; + args.shader_info = info; + args.is_gs_copy_shader = gs_copy_shader; + radv_declare_shader_args(&args, + gs_copy_shader ? MESA_SHADER_VERTEX + : shaders[shader_count - 1]->info.stage, + shader_count >= 2, + shader_count >= 2 ? shaders[shader_count - 2]->info.stage + : MESA_SHADER_VERTEX); + + if (device->physical_device->use_llvm || + options->dump_shader || options->record_ir) + ac_init_llvm_once(); + + if (device->physical_device->use_llvm) { + llvm_compile_shader(device, shader_count, shaders, &binary, &args); } else { - radv_compile_nir_shader(&ac_llvm, &binary, &variant_info, - shaders, shader_count, options); + aco_compile_shader(shader_count, shaders, &binary, &args); } - binary->variant_info = variant_info; - radv_destroy_llvm_compiler(&ac_llvm, thread_compiler); + binary->info = *info; struct radv_shader_variant *variant = radv_shader_variant_create(device, binary, keep_shader_info); @@ -1193,14 +1181,25 @@ shader_variant_compile(struct radv_device *device, } if (options->dump_shader) { - fprintf(stderr, "disasm:\n%s\n", variant->disasm_string); + fprintf(stderr, "%s", radv_get_shader_name(info, shaders[0]->info.stage)); + for (int i = 1; i < shader_count; ++i) + fprintf(stderr, " + %s", radv_get_shader_name(info, shaders[i]->info.stage)); + + fprintf(stderr, "\ndisasm:\n%s\n", variant->disasm_string); } if (keep_shader_info) { variant->nir_string = radv_dump_nir_shaders(shaders, shader_count); if (!gs_copy_shader && !module->nir) { - variant->spirv = (uint32_t *)module->data; + variant->spirv = malloc(module->size); + if (!variant->spirv) { + free(variant); + free(binary); + return NULL; + } + + memcpy(variant->spirv, module->data, module->size); variant->spirv_size = module->size; } } @@ -1220,7 +1219,8 @@ radv_shader_variant_compile(struct radv_device *device, int shader_count, struct radv_pipeline_layout *layout, const struct radv_shader_variant_key *key, - bool keep_shader_info, + struct radv_shader_info *info, + bool keep_shader_info, bool keep_statistic_info, struct radv_shader_binary **binary_out) { struct radv_nir_compiler_options options = {0}; @@ -1229,27 +1229,28 @@ radv_shader_variant_compile(struct radv_device *device, if (key) options.key = *key; - options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH); - options.supports_spill = true; + options.explicit_scratch_args = !device->physical_device->use_llvm; options.robust_buffer_access = device->robust_buffer_access; - return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, - &options, false, keep_shader_info, binary_out); + return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info, + &options, false, keep_shader_info, keep_statistic_info, binary_out); } struct radv_shader_variant * radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *shader, + struct radv_shader_info *info, struct radv_shader_binary **binary_out, - bool keep_shader_info, + bool keep_shader_info, bool keep_statistic_info, bool multiview) { struct radv_nir_compiler_options options = {0}; + options.explicit_scratch_args = !device->physical_device->use_llvm; options.key.has_multiview_view_index = multiview; return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX, - &options, true, keep_shader_info, binary_out); + info, &options, true, keep_shader_info, keep_statistic_info, binary_out); } void @@ -1263,14 +1264,16 @@ radv_shader_variant_destroy(struct radv_device *device, list_del(&variant->slab_list); mtx_unlock(&device->shader_slab_mutex); + free(variant->spirv); free(variant->nir_string); free(variant->disasm_string); - free(variant->llvm_ir_string); + free(variant->ir_string); + free(variant->statistics); free(variant); } const char * -radv_get_shader_name(struct radv_shader_variant_info *info, +radv_get_shader_name(struct radv_shader_info *info, gl_shader_stage stage) { switch (stage) { @@ -1330,16 +1333,16 @@ radv_get_max_waves(struct radv_device *device, { enum chip_class chip_class = device->physical_device->rad_info.chip_class; unsigned lds_increment = chip_class >= GFX7 ? 512 : 256; - uint8_t wave_size = variant->info.info.wave_size; + uint8_t wave_size = variant->info.wave_size; struct ac_shader_config *conf = &variant->config; unsigned max_simd_waves; unsigned lds_per_wave = 0; - max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family); + max_simd_waves = device->physical_device->rad_info.max_wave64_per_simd; if (stage == MESA_SHADER_FRAGMENT) { lds_per_wave = conf->lds_size * lds_increment + - align(variant->info.fs.num_interp * 48, + align(variant->info.ps.num_interp * 48, lds_increment); } else if (stage == MESA_SHADER_COMPUTE) { unsigned max_workgroup_size = @@ -1348,21 +1351,24 @@ radv_get_max_waves(struct radv_device *device, DIV_ROUND_UP(max_workgroup_size, wave_size); } - if (conf->num_sgprs) + if (conf->num_sgprs) { + unsigned sgprs = align(conf->num_sgprs, chip_class >= GFX8 ? 16 : 8); max_simd_waves = MIN2(max_simd_waves, - ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs); + device->physical_device->rad_info.num_physical_sgprs_per_simd / + sgprs); + } - if (conf->num_vgprs) + if (conf->num_vgprs) { + unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4); max_simd_waves = MIN2(max_simd_waves, - RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs); + device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd / vgprs); + } - /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD - * that PS can use. - */ + unsigned max_lds_per_simd = device->physical_device->rad_info.lds_size_per_workgroup / device->physical_device->rad_info.num_simd_per_compute_unit; if (lds_per_wave) - max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave); + max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave); return max_simd_waves; } @@ -1392,13 +1398,23 @@ generate_shader_stats(struct radv_device *device, "Code Size: %d bytes\n" "LDS: %d blocks\n" "Scratch: %d bytes per wave\n" - "Max Waves: %d\n" - "********************\n\n\n", + "Max Waves: %d\n", conf->num_sgprs, conf->num_vgprs, conf->spilled_sgprs, conf->spilled_vgprs, - variant->info.private_mem_vgprs, variant->code_size, + variant->info.private_mem_vgprs, variant->exec_size, conf->lds_size, conf->scratch_bytes_per_wave, max_simd_waves); + + if (variant->statistics) { + _mesa_string_buffer_printf(buf, "*** COMPILER STATS ***\n"); + for (unsigned i = 0; i < variant->statistics->count; i++) { + struct radv_compiler_statistic_info *info = &variant->statistics->infos[i]; + uint32_t value = variant->statistics->values[i]; + _mesa_string_buffer_printf(buf, "%s: %lu\n", info->name, value); + } + } + + _mesa_string_buffer_printf(buf, "********************\n\n\n"); } void @@ -1447,8 +1463,8 @@ radv_GetShaderInfoAMD(VkDevice _device, VkShaderStatisticsInfoAMD statistics = {}; statistics.shaderStageMask = shaderStage; - statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS; - statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class); + statistics.numPhysicalVgprs = device->physical_device->rad_info.num_physical_wave64_vgprs_per_simd; + statistics.numPhysicalSgprs = device->physical_device->rad_info.num_physical_sgprs_per_simd; statistics.numAvailableSgprs = statistics.numPhysicalSgprs; if (stage == MESA_SHADER_COMPUTE) { @@ -1485,7 +1501,7 @@ radv_GetShaderInfoAMD(VkDevice _device, buf = _mesa_string_buffer_create(NULL, 1024); _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage)); - _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string); + _mesa_string_buffer_printf(buf, "%s\n\n", variant->ir_string); _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string); generate_shader_stats(device, variant, stage, buf);