X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_shader.c;h=3af15d4e8446b92217c370eac13811e127174977;hb=6c1108d25b46ddf7789b2c9f9f7b0a79b3e279a0;hp=fb5dc1b03762c391a87f6331da6bf3d5603b362b;hpb=b3c0f82841a29e191d07028391bfe687ae01b7df;p=mesa.git diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index fb5dc1b0376..3af15d4e844 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -86,6 +86,10 @@ static const struct nir_shader_compiler_options nir_options_llvm = { nir_lower_divmod64 | nir_lower_minmax64 | nir_lower_iabs64, + .lower_doubles_options = nir_lower_drcp | + nir_lower_dsqrt | + nir_lower_drsq | + nir_lower_ddiv, }; static const struct nir_shader_compiler_options nir_options_aco = { @@ -120,9 +124,12 @@ static const struct nir_shader_compiler_options nir_options_aco = { nir_lower_imul_high64 | nir_lower_imul_2x32_64 | nir_lower_divmod64 | - nir_lower_logic64 | nir_lower_minmax64 | nir_lower_iabs64, + .lower_doubles_options = nir_lower_drcp | + nir_lower_dsqrt | + nir_lower_drsq | + nir_lower_ddiv, }; bool @@ -226,7 +233,8 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively, NIR_PASS(progress, shader, nir_opt_copy_prop_vars); NIR_PASS(progress, shader, nir_opt_dead_write_vars); NIR_PASS(progress, shader, nir_remove_dead_variables, - nir_var_function_temp | nir_var_shader_in | nir_var_shader_out); + nir_var_function_temp | nir_var_shader_in | nir_var_shader_out, + NULL); NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL); NIR_PASS_V(shader, nir_lower_phis_to_scalar); @@ -301,8 +309,8 @@ radv_shader_compile_to_nir(struct radv_device *device, { nir_shader *nir; const nir_shader_compiler_options *nir_options = - device->physical_device->use_aco ? &nir_options_aco : - &nir_options_llvm; + device->physical_device->use_llvm ? &nir_options_llvm : + &nir_options_aco; if (module->nir) { /* Some things such as our meta clear/blit code will give us a NIR @@ -350,8 +358,6 @@ radv_shader_compile_to_nir(struct radv_device *device, } } } - bool int8_int16_enable = !device->physical_device->use_aco || - device->physical_device->rad_info.chip_class >= GFX8; const struct spirv_to_nir_options spirv_options = { .lower_ubo_ssbo_access_to_offsets = true, .caps = { @@ -359,10 +365,10 @@ radv_shader_compile_to_nir(struct radv_device *device, .amd_gcn_shader = true, .amd_image_gather_bias_lod = true, .amd_image_read_write_lod = true, - .amd_shader_ballot = device->physical_device->use_shader_ballot, + .amd_shader_ballot = true, .amd_shader_explicit_vertex_parameter = true, .amd_trinary_minmax = true, - .demote_to_helper_invocation = device->physical_device->use_aco, + .demote_to_helper_invocation = true, .derivative_group = true, .descriptor_array_dynamic_indexing = true, .descriptor_array_non_uniform_indexing = true, @@ -370,14 +376,15 @@ radv_shader_compile_to_nir(struct radv_device *device, .device_group = true, .draw_parameters = true, .float_controls = true, - .float16 = device->physical_device->rad_info.has_double_rate_fp16 && !device->physical_device->use_aco, + .float16 = device->physical_device->rad_info.has_packed_math_16bit, + .float32_atomic_add = true, .float64 = true, .geometry_streams = true, .image_ms_array = true, .image_read_without_format = true, .image_write_without_format = true, - .int8 = int8_int16_enable, - .int16 = int8_int16_enable, + .int8 = true, + .int16 = true, .int64 = true, .int64_atomics = true, .min_lod = true, @@ -388,8 +395,8 @@ radv_shader_compile_to_nir(struct radv_device *device, .shader_clock = true, .shader_viewport_index_layer = true, .stencil_export = true, - .storage_8bit = int8_int16_enable, - .storage_16bit = int8_int16_enable, + .storage_8bit = true, + .storage_16bit = true, .storage_image_ms = true, .subgroup_arithmetic = true, .subgroup_ballot = true, @@ -452,13 +459,14 @@ radv_shader_compile_to_nir(struct radv_device *device, NIR_PASS_V(nir, nir_split_per_member_structs); if (nir->info.stage == MESA_SHADER_FRAGMENT && - device->physical_device->use_aco) + !device->physical_device->use_llvm) NIR_PASS_V(nir, nir_lower_io_to_vector, nir_var_shader_out); if (nir->info.stage == MESA_SHADER_FRAGMENT) NIR_PASS_V(nir, nir_lower_input_attachments, true); NIR_PASS_V(nir, nir_remove_dead_variables, - nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared); + nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared, + NULL); NIR_PASS_V(nir, nir_propagate_invariant); @@ -467,6 +475,19 @@ radv_shader_compile_to_nir(struct radv_device *device, NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout); if (device->instance->debug_flags & RADV_DEBUG_DISCARD_TO_DEMOTE) NIR_PASS_V(nir, nir_lower_discard_to_demote); + + nir_lower_doubles_options lower_doubles = + nir->options->lower_doubles_options; + + if (device->physical_device->rad_info.chip_class == GFX6) { + /* GFX6 doesn't support v_floor_f64 and the precision + * of v_fract_f64 which is used to implement 64-bit + * floor is less than what Vulkan requires. + */ + lower_doubles |= nir_lower_dfloor; + } + + NIR_PASS_V(nir, nir_lower_doubles, NULL, lower_doubles); } /* Vulkan uses the separate-shader linking model */ @@ -499,7 +520,7 @@ radv_shader_compile_to_nir(struct radv_device *device, nir_split_var_copies(nir); nir_lower_global_vars_to_local(nir); - nir_remove_dead_variables(nir, nir_var_function_temp); + nir_remove_dead_variables(nir, nir_var_function_temp, NULL); bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7; nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) { .subgroup_size = subgroup_size, @@ -511,6 +532,7 @@ radv_shader_compile_to_nir(struct radv_device *device, .lower_vote_eq_to_ballot = 1, .lower_quad_broadcast_dynamic = 1, .lower_quad_broadcast_dynamic_to_const = gfx7minus, + .lower_shuffle_to_swizzle_amd = 1, }); nir_lower_load_const_to_scalar(nir); @@ -632,7 +654,7 @@ radv_lower_fs_io(nir_shader *nir) } -void * +static void * radv_alloc_shader_memory(struct radv_device *device, struct radv_shader_variant *shader) { @@ -668,7 +690,18 @@ radv_alloc_shader_memory(struct radv_device *device, (device->physical_device->rad_info.cpdma_prefetch_writes_memory ? 0 : RADEON_FLAG_READ_ONLY), RADV_BO_PRIORITY_SHADER); + if (!slab->bo) { + free(slab); + return NULL; + } + slab->ptr = (char*)device->ws->buffer_map(slab->bo); + if (!slab->ptr) { + device->ws->buffer_destroy(slab->bo); + free(slab); + return NULL; + } + list_inithead(&slab->shaders); mtx_lock(&device->shader_slab_mutex); @@ -980,7 +1013,8 @@ radv_shader_variant_create(struct radv_device *device, return NULL; } - if (!ac_rtld_read_config(&rtld_binary, &config)) { + if (!ac_rtld_read_config(&device->physical_device->rad_info, + &rtld_binary, &config)) { ac_rtld_close(&rtld_binary); free(variant); return NULL; @@ -1004,15 +1038,14 @@ radv_shader_variant_create(struct radv_device *device, radv_postprocess_config(device->physical_device, &config, &binary->info, binary->stage, &variant->config); - if (radv_device_use_secure_compile(device->instance)) { + void *dest_ptr = radv_alloc_shader_memory(device, variant); + if (!dest_ptr) { if (binary->type == RADV_BINARY_TYPE_RTLD) ac_rtld_close(&rtld_binary); - - return variant; + free(variant); + return NULL; } - void *dest_ptr = radv_alloc_shader_memory(device, variant); - if (binary->type == RADV_BINARY_TYPE_RTLD) { struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary; struct ac_rtld_upload_info info = { @@ -1115,6 +1148,7 @@ shader_variant_compile(struct radv_device *device, options->address32_hi = device->physical_device->rad_info.address32_hi; options->has_ls_vgpr_init_bug = device->physical_device->rad_info.has_ls_vgpr_init_bug; options->use_ngg_streamout = device->physical_device->use_ngg_streamout; + options->enable_mrt_output_nan_fixup = device->instance->enable_mrt_output_nan_fixup; struct radv_shader_args args = {}; args.options = options; @@ -1127,14 +1161,14 @@ shader_variant_compile(struct radv_device *device, shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX); - if (!device->physical_device->use_aco || + if (device->physical_device->use_llvm || options->dump_shader || options->record_ir) ac_init_llvm_once(); - if (device->physical_device->use_aco) { - aco_compile_shader(shader_count, shaders, &binary, &args); - } else { + if (device->physical_device->use_llvm) { llvm_compile_shader(device, shader_count, shaders, &binary, &args); + } else { + aco_compile_shader(shader_count, shaders, &binary, &args); } binary->info = *info; @@ -1195,7 +1229,7 @@ radv_shader_variant_compile(struct radv_device *device, if (key) options.key = *key; - options.explicit_scratch_args = device->physical_device->use_aco; + options.explicit_scratch_args = !device->physical_device->use_llvm; options.robust_buffer_access = device->robust_buffer_access; return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, info, @@ -1212,7 +1246,7 @@ radv_create_gs_copy_shader(struct radv_device *device, { struct radv_nir_compiler_options options = {0}; - options.explicit_scratch_args = device->physical_device->use_aco; + options.explicit_scratch_args = !device->physical_device->use_llvm; options.key.has_multiview_view_index = multiview; return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,