X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_shader.c;h=3b00bf800b96c3d366ede82f462730a741c12f57;hb=921c1d24d5ea17e5448c1f464416397e6fa9e418;hp=7ad9abe8df8a2a946d74e7fa2c608fc9f693f85e;hpb=96063100812d1de46f4146fde92975c98e78c3ce;p=mesa.git

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 7ad9abe8df8..3b00bf800b9 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -40,10 +40,10 @@
 #include <llvm-c/Support.h>
 
 #include "sid.h"
-#include "gfx9d.h"
 #include "ac_binary.h"
 #include "ac_llvm_util.h"
 #include "ac_nir_to_llvm.h"
+#include "ac_rtld.h"
 #include "vk_format.h"
 #include "util/debug.h"
 #include "ac_exp_param.h"
@@ -53,11 +53,14 @@
 static const struct nir_shader_compiler_options nir_options = {
 	.vertex_id_zero_based = true,
 	.lower_scmp = true,
+	.lower_flrp16 = true,
 	.lower_flrp32 = true,
 	.lower_flrp64 = true,
 	.lower_device_index_to_zero = true,
 	.lower_fsat = true,
 	.lower_fdiv = true,
+	.lower_bitfield_insert_to_bitfield_select = true,
+	.lower_bitfield_extract = true,
 	.lower_sub = true,
 	.lower_pack_snorm_2x16 = true,
 	.lower_pack_snorm_4x8 = true,
@@ -71,7 +74,10 @@ static const struct nir_shader_compiler_options nir_options = {
 	.lower_extract_word = true,
 	.lower_ffma = true,
 	.lower_fpow = true,
-	.max_unroll_iterations = 32
+	.lower_mul_2x32_64 = true,
+	.lower_rotate = true,
+	.max_unroll_iterations = 32,
+	.use_interpolated_input_intrinsics = true,
 };
 
 VkResult radv_CreateShaderModule(
@@ -122,12 +128,16 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
                   bool allow_copies)
 {
         bool progress;
+        unsigned lower_flrp =
+                (shader->options->lower_flrp16 ? 16 : 0) |
+                (shader->options->lower_flrp32 ? 32 : 0) |
+                (shader->options->lower_flrp64 ? 64 : 0);
 
         do {
                 progress = false;
 
-		NIR_PASS(progress, shader, nir_split_array_vars, nir_var_local);
-		NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_local);
+		NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp);
+		NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp);
 
                 NIR_PASS_V(shader, nir_lower_vars_to_ssa);
 		NIR_PASS_V(shader, nir_lower_pack);
@@ -144,7 +154,7 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 		NIR_PASS(progress, shader, nir_opt_copy_prop_vars);
 		NIR_PASS(progress, shader, nir_opt_dead_write_vars);
 
-                NIR_PASS_V(shader, nir_lower_alu_to_scalar);
+                NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL);
                 NIR_PASS_V(shader, nir_lower_phis_to_scalar);
 
                 NIR_PASS(progress, shader, nir_copy_prop);
@@ -156,12 +166,33 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 			NIR_PASS(progress, shader, nir_opt_remove_phis);
                         NIR_PASS(progress, shader, nir_opt_dce);
                 }
-                NIR_PASS(progress, shader, nir_opt_if);
+                NIR_PASS(progress, shader, nir_opt_if, true);
                 NIR_PASS(progress, shader, nir_opt_dead_cf);
                 NIR_PASS(progress, shader, nir_opt_cse);
                 NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true);
-                NIR_PASS(progress, shader, nir_opt_algebraic);
                 NIR_PASS(progress, shader, nir_opt_constant_folding);
+                NIR_PASS(progress, shader, nir_opt_algebraic);
+
+                if (lower_flrp != 0) {
+                        bool lower_flrp_progress = false;
+                        NIR_PASS(lower_flrp_progress,
+                                 shader,
+                                 nir_lower_flrp,
+                                 lower_flrp,
+                                 false /* always_precise */,
+                                 shader->options->lower_ffma);
+                        if (lower_flrp_progress) {
+                                NIR_PASS(progress, shader,
+                                         nir_opt_constant_folding);
+                                progress = true;
+                        }
+
+                        /* Nothing should rematerialize any flrps, so we only
+                         * need to do this lowering once.
+                         */
+                        lower_flrp = 0;
+                }
+
                 NIR_PASS(progress, shader, nir_opt_undef);
                 NIR_PASS(progress, shader, nir_opt_conditional_discard);
                 if (shader->options->max_unroll_iterations) {
@@ -179,10 +210,10 @@ radv_shader_compile_to_nir(struct radv_device *device,
 			   const char *entrypoint_name,
 			   gl_shader_stage stage,
 			   const VkSpecializationInfo *spec_info,
-			   const VkPipelineCreateFlags flags)
+			   const VkPipelineCreateFlags flags,
+			   const struct radv_pipeline_layout *layout)
 {
 	nir_shader *nir;
-	nir_function *entry_point;
 	if (module->nir) {
 		/* Some things such as our meta clear/blit code will give us a NIR
 		 * shader directly.  In that case, we just ignore the SPIR-V entirely
@@ -192,8 +223,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
 		nir_validate_shader(nir, "in internal shader");
 
 		assert(exec_list_length(&nir->functions) == 1);
-		struct exec_node *node = exec_list_get_head(&nir->functions);
-		entry_point = exec_node_data(nir_function, node, node);
 	} else {
 		uint32_t *spirv = (uint32_t *) module->data;
 		assert(module->size % 4 == 0);
@@ -219,40 +248,56 @@ radv_shader_compile_to_nir(struct radv_device *device,
 			}
 		}
 		const struct spirv_to_nir_options spirv_options = {
+			.lower_ubo_ssbo_access_to_offsets = true,
 			.caps = {
+				.amd_gcn_shader = true,
+				.amd_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT,
+				.amd_trinary_minmax = true,
+				.derivative_group = true,
+				.descriptor_array_dynamic_indexing = true,
+				.descriptor_array_non_uniform_indexing = true,
+				.descriptor_indexing = true,
 				.device_group = true,
 				.draw_parameters = true,
+				.float16 = true,
 				.float64 = true,
+				.geometry_streams = true,
 				.image_read_without_format = true,
 				.image_write_without_format = true,
-				.tessellation = true,
-				.int64 = true,
+				.int8 = true,
 				.int16 = true,
+				.int64 = true,
+				.int64_atomics = true,
 				.multiview = true,
+				.physical_storage_buffer_address = true,
+				.post_depth_coverage = true,
+				.runtime_descriptor_array = true,
+				.shader_viewport_index_layer = true,
+				.stencil_export = true,
+				.storage_8bit = true,
+				.storage_16bit = true,
+				.storage_image_ms = true,
 				.subgroup_arithmetic = true,
 				.subgroup_ballot = true,
 				.subgroup_basic = true,
 				.subgroup_quad = true,
 				.subgroup_shuffle = true,
 				.subgroup_vote = true,
-				.variable_pointers = true,
-				.gcn_shader = true,
-				.trinary_minmax = true,
-				.shader_viewport_index_layer = true,
-				.descriptor_array_dynamic_indexing = true,
-				.runtime_descriptor_array = true,
-				.stencil_export = true,
-				.storage_16bit = true,
-				.geometry_streams = true,
+				.tessellation = true,
 				.transform_feedback = true,
-				.storage_image_ms = true,
+				.variable_pointers = true,
 			},
+			.ubo_addr_format = nir_address_format_32bit_index_offset,
+			.ssbo_addr_format = nir_address_format_32bit_index_offset,
+			.phys_ssbo_addr_format = nir_address_format_64bit_global,
+			.push_const_addr_format = nir_address_format_logical,
+			.shared_addr_format = nir_address_format_32bit_offset,
+			.frag_coord_is_sysval = true,
 		};
-		entry_point = spirv_to_nir(spirv, module->size / 4,
-					   spec_entries, num_spec_entries,
-					   stage, entrypoint_name,
-					   &spirv_options, &nir_options);
-		nir = entry_point->shader;
+		nir = spirv_to_nir(spirv, module->size / 4,
+				   spec_entries, num_spec_entries,
+				   stage, entrypoint_name,
+				   &spirv_options, &nir_options);
 		assert(nir->info.stage == stage);
 		nir_validate_shader(nir, "after spirv_to_nir");
 
@@ -262,18 +307,19 @@ radv_shader_compile_to_nir(struct radv_device *device,
 		 * inline functions.  That way they get properly initialized at the top
 		 * of the function and not at the top of its caller.
 		 */
-		NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
+		NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
 		NIR_PASS_V(nir, nir_lower_returns);
 		NIR_PASS_V(nir, nir_inline_functions);
-		NIR_PASS_V(nir, nir_copy_prop);
+		NIR_PASS_V(nir, nir_opt_deref);
 
 		/* Pick off the single entrypoint that we want */
 		foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
-			if (func != entry_point)
+			if (func->is_entrypoint)
+				func->name = ralloc_strdup(func, "main");
+			else
 				exec_node_remove(&func->node);
 		}
 		assert(exec_list_length(&nir->functions) == 1);
-		entry_point->name = ralloc_strdup(entry_point, "main");
 
 		/* Make sure we lower constant initializers on output variables so that
 		 * nir_remove_dead_variables below sees the corresponding stores
@@ -291,20 +337,25 @@ radv_shader_compile_to_nir(struct radv_device *device,
 		NIR_PASS_V(nir, nir_split_var_copies);
 		NIR_PASS_V(nir, nir_split_per_member_structs);
 
+		if (nir->info.stage == MESA_SHADER_FRAGMENT)
+			NIR_PASS_V(nir, nir_lower_input_attachments, true);
+
 		NIR_PASS_V(nir, nir_remove_dead_variables,
 		           nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 
 		NIR_PASS_V(nir, nir_lower_system_values);
 		NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
+		NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
 	}
 
 	/* Vulkan uses the separate-shader linking model */
 	nir->info.separate_shader = true;
 
-	nir_shader_gather_info(nir, entry_point->impl);
+	nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 
 	static const nir_lower_tex_options tex_options = {
 	  .lower_txp = ~0,
+	  .lower_tg4_offsets = true,
 	};
 
 	nir_lower_tex(nir, &tex_options);
@@ -312,11 +363,11 @@ radv_shader_compile_to_nir(struct radv_device *device,
 	nir_lower_vars_to_ssa(nir);
 
 	if (nir->info.stage == MESA_SHADER_VERTEX ||
-	    nir->info.stage == MESA_SHADER_GEOMETRY) {
+	    nir->info.stage == MESA_SHADER_GEOMETRY ||
+	    nir->info.stage == MESA_SHADER_FRAGMENT) {
 		NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 			   nir_shader_get_entrypoint(nir), true, true);
-	} else if (nir->info.stage == MESA_SHADER_TESS_EVAL||
-		   nir->info.stage == MESA_SHADER_FRAGMENT) {
+	} else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
 		NIR_PASS_V(nir, nir_lower_io_to_temporaries,
 			   nir_shader_get_entrypoint(nir), true, false);
 	}
@@ -324,7 +375,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
 	nir_split_var_copies(nir);
 
 	nir_lower_global_vars_to_local(nir);
-	nir_remove_dead_variables(nir, nir_var_local);
+	nir_remove_dead_variables(nir, nir_var_function_temp);
 	nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
 			.subgroup_size = 64,
 			.ballot_bit_size = 64,
@@ -356,6 +407,151 @@ radv_shader_compile_to_nir(struct radv_device *device,
 	return nir;
 }
 
+static void mark_16bit_fs_input(struct radv_shader_variant_info *shader_info,
+                                const struct glsl_type *type,
+                                int location)
+{
+	if (glsl_type_is_scalar(type) || glsl_type_is_vector(type) || glsl_type_is_matrix(type)) {
+		unsigned attrib_count = glsl_count_attribute_slots(type, false);
+		if (glsl_type_is_16bit(type)) {
+			shader_info->fs.float16_shaded_mask |= ((1ull << attrib_count) - 1) << location;
+		}
+	} else if (glsl_type_is_array(type)) {
+		unsigned stride = glsl_count_attribute_slots(glsl_get_array_element(type), false);
+		for (unsigned i = 0; i < glsl_get_length(type); ++i) {
+			mark_16bit_fs_input(shader_info, glsl_get_array_element(type), location + i * stride);
+		}
+	} else {
+		assert(glsl_type_is_struct_or_ifc(type));
+		for (unsigned i = 0; i < glsl_get_length(type); i++) {
+			mark_16bit_fs_input(shader_info, glsl_get_struct_field(type, i), location);
+			location += glsl_count_attribute_slots(glsl_get_struct_field(type, i), false);
+		}
+	}
+}
+
+static void
+handle_fs_input_decl(struct radv_shader_variant_info *shader_info,
+		     struct nir_variable *variable)
+{
+	unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
+
+	if (variable->data.compact) {
+		unsigned component_count = variable->data.location_frac +
+		                           glsl_get_length(variable->type);
+		attrib_count = (component_count + 3) / 4;
+	} else {
+		mark_16bit_fs_input(shader_info, variable->type,
+				    variable->data.driver_location);
+	}
+
+	uint64_t mask = ((1ull << attrib_count) - 1);
+
+	if (variable->data.interpolation == INTERP_MODE_FLAT)
+		shader_info->fs.flat_shaded_mask |= mask << variable->data.driver_location;
+
+	if (variable->data.location >= VARYING_SLOT_VAR0)
+		shader_info->fs.input_mask |= mask << (variable->data.location - VARYING_SLOT_VAR0);
+}
+
+static int
+type_size_vec4(const struct glsl_type *type, bool bindless)
+{
+	return glsl_count_attribute_slots(type, false);
+}
+
+static nir_variable *
+find_layer_in_var(nir_shader *nir)
+{
+	nir_foreach_variable(var, &nir->inputs) {
+		if (var->data.location == VARYING_SLOT_LAYER) {
+			return var;
+		}
+	}
+
+	nir_variable *var =
+		nir_variable_create(nir, nir_var_shader_in, glsl_int_type(), "layer id");
+	var->data.location = VARYING_SLOT_LAYER;
+	var->data.interpolation = INTERP_MODE_FLAT;
+	return var;
+}
+
+/* We use layered rendering to implement multiview, which means we need to map
+ * view_index to gl_Layer. The attachment lowering also uses needs to know the
+ * layer so that it can sample from the correct layer. The code generates a
+ * load from the layer_id sysval, but since we don't have a way to get at this
+ * information from the fragment shader, we also need to lower this to the
+ * gl_Layer varying.  This pass lowers both to a varying load from the LAYER
+ * slot, before lowering io, so that nir_assign_var_locations() will give the
+ * LAYER varying the correct driver_location.
+ */
+
+static bool
+lower_view_index(nir_shader *nir)
+{
+	bool progress = false;
+	nir_function_impl *entry = nir_shader_get_entrypoint(nir);
+	nir_builder b;
+	nir_builder_init(&b, entry);
+	
+	nir_variable *layer = NULL;
+	nir_foreach_block(block, entry) {
+		nir_foreach_instr_safe(instr, block) {
+			if (instr->type != nir_instr_type_intrinsic)
+				continue;
+
+			nir_intrinsic_instr *load = nir_instr_as_intrinsic(instr);
+			if (load->intrinsic != nir_intrinsic_load_view_index &&
+			    load->intrinsic != nir_intrinsic_load_layer_id)
+				continue;
+
+			if (!layer)
+				layer = find_layer_in_var(nir);
+
+			b.cursor = nir_before_instr(instr);
+			nir_ssa_def *def = nir_load_var(&b, layer);
+			nir_ssa_def_rewrite_uses(&load->dest.ssa,
+						 nir_src_for_ssa(def));
+
+			nir_instr_remove(instr);
+			progress = true;
+		}
+	}
+
+	return progress;
+}
+
+/* Gather information needed to setup the vs<->ps linking registers in
+ * radv_pipeline_generate_ps_inputs().
+ */
+
+static void
+handle_fs_inputs(nir_shader *nir, struct radv_shader_variant_info *shader_info)
+{
+	shader_info->fs.num_interp = nir->num_inputs;
+	
+	nir_foreach_variable(variable, &nir->inputs)
+		handle_fs_input_decl(shader_info, variable);
+}
+
+static void
+lower_fs_io(nir_shader *nir, struct radv_shader_variant_info *shader_info)
+{
+	NIR_PASS_V(nir, lower_view_index);
+	nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
+				    MESA_SHADER_FRAGMENT);
+
+	handle_fs_inputs(nir, shader_info);
+
+	NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
+
+	/* This pass needs actual constants */
+	nir_opt_constant_folding(nir);
+
+	NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in);
+}
+
+
 void *
 radv_alloc_shader_memory(struct radv_device *device,
 			 struct radv_shader_variant *shader)
@@ -390,7 +586,8 @@ radv_alloc_shader_memory(struct radv_device *device,
 	                                     RADEON_DOMAIN_VRAM,
 					     RADEON_FLAG_NO_INTERPROCESS_SHARING |
 					     (device->physical_device->cpdma_prefetch_writes_memory ?
-					             0 : RADEON_FLAG_READ_ONLY));
+					             0 : RADEON_FLAG_READ_ONLY),
+					     RADV_BO_PRIORITY_SHADER);
 	slab->ptr = (char*)device->ws->buffer_map(slab->bo);
 	list_inithead(&slab->shaders);
 
@@ -419,78 +616,229 @@ radv_destroy_shader_slabs(struct radv_device *device)
 #define DEBUGGER_NUM_MARKERS           5
 
 static unsigned
-radv_get_shader_binary_size(struct ac_shader_binary *binary)
+radv_get_shader_binary_size(size_t code_size)
 {
-	return binary->code_size + DEBUGGER_NUM_MARKERS * 4;
+	return code_size + DEBUGGER_NUM_MARKERS * 4;
 }
 
-static void
-radv_fill_shader_variant(struct radv_device *device,
-			 struct radv_shader_variant *variant,
-			 struct ac_shader_binary *binary,
-			 gl_shader_stage stage)
+static void radv_postprocess_config(const struct radv_physical_device *pdevice,
+				    const struct ac_shader_config *config_in,
+				    const struct radv_shader_variant_info *info,
+				    gl_shader_stage stage,
+				    struct ac_shader_config *config_out)
 {
-	bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
-	struct radv_shader_info *info = &variant->info.info;
+	bool scratch_enabled = config_in->scratch_bytes_per_wave > 0;
 	unsigned vgpr_comp_cnt = 0;
+	unsigned num_input_vgprs = info->num_input_vgprs;
 
-	variant->code_size = radv_get_shader_binary_size(binary);
-	variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
-			 S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) |
-			 S_00B12C_SCRATCH_EN(scratch_enabled) |
-			 S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) |
-			 S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) |
-			 S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) |
-			 S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) |
-			 S_00B12C_SO_EN(!!info->so.num_outputs);
-
-	variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
-		S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
-		S_00B848_DX10_CLAMP(1) |
-		S_00B848_FLOAT_MODE(variant->config.float_mode);
+	if (stage == MESA_SHADER_FRAGMENT) {
+		num_input_vgprs = 0;
+		if (G_0286CC_PERSP_SAMPLE_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 2;
+		if (G_0286CC_PERSP_CENTER_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 2;
+		if (G_0286CC_PERSP_CENTROID_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 2;
+		if (G_0286CC_PERSP_PULL_MODEL_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 3;
+		if (G_0286CC_LINEAR_SAMPLE_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 2;
+		if (G_0286CC_LINEAR_CENTER_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 2;
+		if (G_0286CC_LINEAR_CENTROID_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 2;
+		if (G_0286CC_LINE_STIPPLE_TEX_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 1;
+		if (G_0286CC_POS_X_FLOAT_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 1;
+		if (G_0286CC_POS_Y_FLOAT_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 1;
+		if (G_0286CC_POS_Z_FLOAT_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 1;
+		if (G_0286CC_POS_W_FLOAT_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 1;
+		if (G_0286CC_FRONT_FACE_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 1;
+		if (G_0286CC_ANCILLARY_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 1;
+		if (G_0286CC_SAMPLE_COVERAGE_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 1;
+		if (G_0286CC_POS_FIXED_PT_ENA(config_in->spi_ps_input_addr))
+			num_input_vgprs += 1;
+	}
+
+	unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs);
+	/* +3 for scratch wave offset and VCC */
+	unsigned num_sgprs = MAX2(config_in->num_sgprs, info->num_input_sgprs + 3);
+
+	*config_out = *config_in;
+	config_out->num_vgprs = num_vgprs;
+	config_out->num_sgprs = num_sgprs;
+
+	/* Enable 64-bit and 16-bit denormals, because there is no performance
+	 * cost.
+	 *
+	 * If denormals are enabled, all floating-point output modifiers are
+	 * ignored.
+	 *
+	 * Don't enable denormals for 32-bit floats, because:
+	 * - Floating-point output modifiers would be ignored by the hw.
+	 * - Some opcodes don't support denormals, such as v_mad_f32. We would
+	 *   have to stop using those.
+	 * - GFX6 & GFX7 would be very slow.
+	 */
+	config_out->float_mode |= V_00B028_FP_64_DENORMS;
+
+	config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
+			    S_00B12C_SCRATCH_EN(scratch_enabled);
+
+	config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / 4) |
+			    S_00B848_DX10_CLAMP(1) |
+			    S_00B848_FLOAT_MODE(config_out->float_mode);
+
+	if (pdevice->rad_info.chip_class >= GFX10) {
+		config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
+	} else {
+		config_out->rsrc1 |= S_00B228_SGPRS((num_sgprs - 1) / 8);
+		config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5)  |
+		                     S_00B12C_SO_BASE0_EN(!!info->info.so.strides[0]) |
+		                     S_00B12C_SO_BASE1_EN(!!info->info.so.strides[1]) |
+		                     S_00B12C_SO_BASE2_EN(!!info->info.so.strides[2]) |
+		                     S_00B12C_SO_BASE3_EN(!!info->info.so.strides[3]) |
+		                     S_00B12C_SO_EN(!!info->info.so.num_outputs);
+	}
 
 	switch (stage) {
 	case MESA_SHADER_TESS_EVAL:
-		vgpr_comp_cnt = 3;
-		variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
+		if (info->is_ngg) {
+			config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
+			config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1);
+		} else if (info->tes.as_es) {
+			assert(pdevice->rad_info.chip_class <= GFX8);
+			vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
+
+			config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
+		} else {
+			bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id;
+			vgpr_comp_cnt = enable_prim_id ? 3 : 2;
+
+			config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
+			config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
+		}
 		break;
 	case MESA_SHADER_TESS_CTRL:
-		if (device->physical_device->rad_info.chip_class >= GFX9) {
-			vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
+		if (pdevice->rad_info.chip_class >= GFX9) {
+			/* We need at least 2 components for LS.
+			 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
+			 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
+			 */
+			if (pdevice->rad_info.chip_class >= GFX10) {
+				vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3 : 1;
+			} else {
+				vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1;
+			}
 		} else {
-			variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
+			config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1);
 		}
+		config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
+				     S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
 		break;
 	case MESA_SHADER_VERTEX:
-	case MESA_SHADER_GEOMETRY:
-		vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
+		if (info->is_ngg) {
+			config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
+		} else if (info->vs.as_ls) {
+			assert(pdevice->rad_info.chip_class <= GFX8);
+			/* We need at least 2 components for LS.
+			 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
+			 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
+			 */
+			vgpr_comp_cnt = info->info.vs.needs_instance_id ? 2 : 1;
+		} else if (info->vs.as_es) {
+			assert(pdevice->rad_info.chip_class <= GFX8);
+			/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
+			vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0;
+		} else {
+			/* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
+			 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
+			 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
+			 */
+			if (info->vs.export_prim_id) {
+				vgpr_comp_cnt = 2;
+			} else if (info->info.vs.needs_instance_id) {
+				vgpr_comp_cnt = 1;
+			} else {
+				vgpr_comp_cnt = 0;
+			}
+
+			config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
+		}
 		break;
 	case MESA_SHADER_FRAGMENT:
+		config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10);
+		break;
+	case MESA_SHADER_GEOMETRY:
+		config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
+				     S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
 		break;
 	case MESA_SHADER_COMPUTE:
-		variant->rsrc2 |=
-			S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
-			S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
-			S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) |
-			S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 :
-						info->cs.uses_thread_id[1] ? 1 : 0) |
-			S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) |
-			S_00B84C_LDS_SIZE(variant->config.lds_size);
+		config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10) |
+				     S_00B848_WGP_MODE(pdevice->rad_info.chip_class >= GFX10);
+		config_out->rsrc2 |=
+			S_00B84C_TGID_X_EN(info->info.cs.uses_block_id[0]) |
+			S_00B84C_TGID_Y_EN(info->info.cs.uses_block_id[1]) |
+			S_00B84C_TGID_Z_EN(info->info.cs.uses_block_id[2]) |
+			S_00B84C_TIDIG_COMP_CNT(info->info.cs.uses_thread_id[2] ? 2 :
+						info->info.cs.uses_thread_id[1] ? 1 : 0) |
+			S_00B84C_TG_SIZE_EN(info->info.cs.uses_local_invocation_idx) |
+			S_00B84C_LDS_SIZE(config_in->lds_size);
 		break;
 	default:
 		unreachable("unsupported shader type");
 		break;
 	}
 
-	if (device->physical_device->rad_info.chip_class >= GFX9 &&
-	    stage == MESA_SHADER_GEOMETRY) {
-		unsigned es_type = variant->info.gs.es_type;
+	if (pdevice->rad_info.chip_class >= GFX10 && info->is_ngg &&
+	    (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_GEOMETRY)) {
+		unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
+		gl_shader_stage es_stage = stage;
+		if (stage == MESA_SHADER_GEOMETRY)
+			es_stage = info->gs.es_type;
+
+		/* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
+		if (es_stage == MESA_SHADER_VERTEX) {
+			es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3 : 0;
+		} else if (es_stage == MESA_SHADER_TESS_EVAL) {
+			bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id;
+			es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
+		}
+
+		bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
+			info->tes.primitive_mode >= 4; /* GL_TRIANGLES */
+		if (info->info.uses_invocation_id || stage == MESA_SHADER_VERTEX) {
+			gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
+		} else if (info->info.uses_prim_id) {
+			gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
+		} else if (info->gs.vertices_in >= 3 || tes_triangles) {
+			gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
+		} else {
+			gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
+		}
+
+		config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt) |
+				     S_00B228_WGP_MODE(1);
+		config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
+				     S_00B22C_LDS_SIZE(config_in->lds_size) |
+				     S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL);
+	} else if (pdevice->rad_info.chip_class >= GFX9 &&
+		   stage == MESA_SHADER_GEOMETRY) {
+		unsigned es_type = info->gs.es_type;
 		unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
 
 		if (es_type == MESA_SHADER_VERTEX) {
-			es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
+			/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
+			es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 1 : 0;
 		} else if (es_type == MESA_SHADER_TESS_EVAL) {
-			es_vgpr_comp_cnt = 3;
+			es_vgpr_comp_cnt = info->info.uses_prim_id ? 3 : 2;
 		} else {
 			unreachable("invalid shader ES type");
 		}
@@ -498,34 +846,25 @@ radv_fill_shader_variant(struct radv_device *device,
 		/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
 		 * VGPR[0:4] are always loaded.
 		 */
-		if (info->uses_invocation_id) {
+		if (info->info.uses_invocation_id) {
 			gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
-		} else if (info->uses_prim_id) {
+		} else if (info->info.uses_prim_id) {
 			gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
-		} else if (variant->info.gs.vertices_in >= 3) {
+		} else if (info->gs.vertices_in >= 3) {
 			gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
 		} else {
 			gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
 		}
 
-		variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
-		variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
-		                  S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
-	} else if (device->physical_device->rad_info.chip_class >= GFX9 &&
+		config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
+		config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
+		                         S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL);
+	} else if (pdevice->rad_info.chip_class >= GFX9 &&
 		   stage == MESA_SHADER_TESS_CTRL) {
-		variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
+		config_out->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
 	} else {
-		variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
+		config_out->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt);
 	}
-
-	void *ptr = radv_alloc_shader_memory(device, variant);
-	memcpy(ptr, binary->code, binary->code_size);
-
-	/* Add end-of-code markers for the UMR disassembler. */
-       uint32_t *ptr32 = (uint32_t *)ptr + binary->code_size / 4;
-       for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
-		ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
-
 }
 
 static void radv_init_llvm_target()
@@ -567,26 +906,162 @@ static void radv_init_llvm_once(void)
 	call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
 }
 
+struct radv_shader_variant *
+radv_shader_variant_create(struct radv_device *device,
+			   const struct radv_shader_binary *binary)
+{
+	struct ac_shader_config config = {0};
+	struct ac_rtld_binary rtld_binary = {0};
+	struct radv_shader_variant *variant = calloc(1, sizeof(struct radv_shader_variant));
+	if (!variant)
+		return NULL;
+
+	variant->ref_count = 1;
+
+	if (binary->type == RADV_BINARY_TYPE_RTLD) {
+		struct ac_rtld_symbol lds_symbols[1];
+		unsigned num_lds_symbols = 0;
+		const char *elf_data = (const char *)((struct radv_shader_binary_rtld *)binary)->data;
+		size_t elf_size = ((struct radv_shader_binary_rtld *)binary)->elf_size;
+		unsigned esgs_ring_size = 0;
+
+		if (device->physical_device->rad_info.chip_class >= GFX9 &&
+		    binary->stage == MESA_SHADER_GEOMETRY && !binary->is_gs_copy_shader) {
+			/* TODO: Do not hardcode this value */
+			esgs_ring_size = 32 * 1024;
+		}
+
+		if (binary->variant_info.is_ngg) {
+			/* GS stores Primitive IDs into LDS at the address
+			 * corresponding to the ES thread of the provoking
+			 * vertex. All ES threads load and export PrimitiveID
+			 * for their thread.
+			 */
+			if (binary->stage == MESA_SHADER_VERTEX &&
+			    binary->variant_info.vs.export_prim_id) {
+				/* TODO: Do not harcode this value */
+				esgs_ring_size = 256 /* max_out_verts */ * 4;
+			}
+		}
+
+		if (esgs_ring_size) {
+			/* We add this symbol even on LLVM <= 8 to ensure that
+			 * shader->config.lds_size is set correctly below.
+			 */
+			struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
+			sym->name = "esgs_ring";
+			sym->size = esgs_ring_size;
+			sym->align = 64 * 1024;
+
+			/* Make sure to have LDS space for NGG scratch. */
+			/* TODO: Compute this correctly somehow? */
+			if (binary->variant_info.is_ngg)
+				sym->size -= 32;
+		}
+		struct ac_rtld_open_info open_info = {
+			.info = &device->physical_device->rad_info,
+			.shader_type = binary->stage,
+			.wave_size = 64,
+			.num_parts = 1,
+			.elf_ptrs = &elf_data,
+			.elf_sizes = &elf_size,
+			.num_shared_lds_symbols = num_lds_symbols,
+			.shared_lds_symbols = lds_symbols,
+		};
+		
+		if (!ac_rtld_open(&rtld_binary, open_info)) {
+			free(variant);
+			return NULL;
+		}
+
+		if (!ac_rtld_read_config(&rtld_binary, &config)) {
+			ac_rtld_close(&rtld_binary);
+			free(variant);
+			return NULL;
+		}
+
+		if (rtld_binary.lds_size > 0) {
+			unsigned alloc_granularity = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
+			config.lds_size = align(rtld_binary.lds_size, alloc_granularity) / alloc_granularity;
+		}
+
+		variant->code_size = rtld_binary.rx_size;
+	} else {
+		assert(binary->type == RADV_BINARY_TYPE_LEGACY);
+		config = ((struct radv_shader_binary_legacy *)binary)->config;
+		variant->code_size  = radv_get_shader_binary_size(((struct radv_shader_binary_legacy *)binary)->code_size);
+	}
+
+	variant->info = binary->variant_info;
+	radv_postprocess_config(device->physical_device, &config, &binary->variant_info,
+				binary->stage, &variant->config);
+	
+	void *dest_ptr = radv_alloc_shader_memory(device, variant);
+
+	if (binary->type == RADV_BINARY_TYPE_RTLD) {
+		struct radv_shader_binary_rtld* bin = (struct radv_shader_binary_rtld *)binary;
+		struct ac_rtld_upload_info info = {
+			.binary = &rtld_binary,
+			.rx_va = radv_buffer_get_va(variant->bo) + variant->bo_offset,
+			.rx_ptr = dest_ptr, 
+		};
+
+		if (!ac_rtld_upload(&info)) {
+			radv_shader_variant_destroy(device, variant);
+			ac_rtld_close(&rtld_binary);
+			return NULL;
+		}
+
+		if (device->keep_shader_info) {
+			const char *disasm_data;
+			size_t disasm_size;
+			if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm_data, &disasm_size)) {
+				radv_shader_variant_destroy(device, variant);
+				ac_rtld_close(&rtld_binary);
+				return NULL;
+			}
+
+			variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->elf_size)) : NULL;
+			variant->disasm_string = malloc(disasm_size + 1);
+			memcpy(variant->disasm_string, disasm_data, disasm_size);
+			variant->disasm_string[disasm_size] = 0;
+		}
+
+		ac_rtld_close(&rtld_binary);
+	} else {
+		struct radv_shader_binary_legacy* bin = (struct radv_shader_binary_legacy *)binary;
+		memcpy(dest_ptr, bin->data, bin->code_size);
+
+		/* Add end-of-code markers for the UMR disassembler. */
+		uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4;
+		for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
+			ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
+
+		variant->llvm_ir_string = bin->llvm_ir_size ? strdup((const char*)(bin->data + bin->code_size)) : NULL;
+		variant->disasm_string = bin->disasm_size ? strdup((const char*)(bin->data + bin->code_size + bin->llvm_ir_size)) : NULL;
+	}
+	return variant;
+}
+
 static struct radv_shader_variant *
-shader_variant_create(struct radv_device *device,
-		      struct radv_shader_module *module,
-		      struct nir_shader * const *shaders,
-		      int shader_count,
-		      gl_shader_stage stage,
-		      struct radv_nir_compiler_options *options,
-		      bool gs_copy_shader,
-		      void **code_out,
-		      unsigned *code_size_out)
+shader_variant_compile(struct radv_device *device,
+		       struct radv_shader_module *module,
+		       struct nir_shader * const *shaders,
+		       int shader_count,
+		       gl_shader_stage stage,
+		       struct radv_nir_compiler_options *options,
+		       bool gs_copy_shader,
+		       struct radv_shader_binary **binary_out)
 {
 	enum radeon_family chip_family = device->physical_device->rad_info.family;
 	enum ac_target_machine_options tm_options = 0;
-	struct radv_shader_variant *variant;
-	struct ac_shader_binary binary;
 	struct ac_llvm_compiler ac_llvm;
+	struct radv_shader_binary *binary = NULL;
+	struct radv_shader_variant_info variant_info = {0};
 	bool thread_compiler;
-	variant = calloc(1, sizeof(struct radv_shader_variant));
-	if (!variant)
-		return NULL;
+
+	if (shaders[0]->info.stage == MESA_SHADER_FRAGMENT)
+		lower_fs_io(shaders[0], &variant_info);
 
 	options->family = chip_family;
 	options->chip_class = device->physical_device->rad_info.chip_class;
@@ -604,6 +1079,8 @@ shader_variant_create(struct radv_device *device,
 		tm_options |= AC_TM_SISCHED;
 	if (options->check_ir)
 		tm_options |= AC_TM_CHECK_IR;
+	if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
+		tm_options |= AC_TM_NO_LOAD_STORE_OPT;
 
 	thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
 	radv_init_llvm_once();
@@ -613,53 +1090,50 @@ shader_variant_create(struct radv_device *device,
 	if (gs_copy_shader) {
 		assert(shader_count == 1);
 		radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary,
-					    &variant->config, &variant->info,
-					    options);
+					    &variant_info, options);
 	} else {
-		radv_compile_nir_shader(&ac_llvm, &binary, &variant->config,
-					&variant->info, shaders, shader_count,
-					options);
+		radv_compile_nir_shader(&ac_llvm, &binary, &variant_info,
+					shaders, shader_count, options);
 	}
+	binary->variant_info = variant_info;
 
 	radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
 
-	radv_fill_shader_variant(device, variant, &binary, stage);
-
-	if (code_out) {
-		*code_out = binary.code;
-		*code_size_out = binary.code_size;
-	} else
-		free(binary.code);
-	free(binary.config);
-	free(binary.rodata);
-	free(binary.global_symbol_offsets);
-	free(binary.relocs);
-	variant->ref_count = 1;
+	struct radv_shader_variant *variant = radv_shader_variant_create(device, binary);
+	if (!variant) {
+		free(binary);
+		return NULL;
+	}
+
+	if (options->dump_shader) {
+		fprintf(stderr, "disasm:\n%s\n", variant->disasm_string);
+	}
+
 
 	if (device->keep_shader_info) {
-		variant->disasm_string = binary.disasm_string;
-		variant->llvm_ir_string = binary.llvm_ir_string;
 		if (!gs_copy_shader && !module->nir) {
 			variant->nir = *shaders;
 			variant->spirv = (uint32_t *)module->data;
 			variant->spirv_size = module->size;
 		}
-	} else {
-		free(binary.disasm_string);
 	}
 
+	if (binary_out)
+		*binary_out = binary;
+	else
+		free(binary);
+
 	return variant;
 }
 
 struct radv_shader_variant *
-radv_shader_variant_create(struct radv_device *device,
+radv_shader_variant_compile(struct radv_device *device,
 			   struct radv_shader_module *module,
 			   struct nir_shader *const *shaders,
 			   int shader_count,
 			   struct radv_pipeline_layout *layout,
 			   const struct radv_shader_variant_key *key,
-			   void **code_out,
-			   unsigned *code_size_out)
+			   struct radv_shader_binary **binary_out)
 {
 	struct radv_nir_compiler_options options = {0};
 
@@ -670,23 +1144,22 @@ radv_shader_variant_create(struct radv_device *device,
 	options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH);
 	options.supports_spill = true;
 
-	return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
-				     &options, false, code_out, code_size_out);
+	return shader_variant_compile(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage,
+				     &options, false, binary_out);
 }
 
 struct radv_shader_variant *
 radv_create_gs_copy_shader(struct radv_device *device,
 			   struct nir_shader *shader,
-			   void **code_out,
-			   unsigned *code_size_out,
+			   struct radv_shader_binary **binary_out,
 			   bool multiview)
 {
 	struct radv_nir_compiler_options options = {0};
 
 	options.key.has_multiview_view_index = multiview;
 
-	return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
-				     &options, true, code_out, code_size_out);
+	return shader_variant_compile(device, NULL, &shader, 1, MESA_SHADER_VERTEX,
+				     &options, true, binary_out);
 }
 
 void
@@ -707,15 +1180,34 @@ radv_shader_variant_destroy(struct radv_device *device,
 }
 
 const char *
-radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage)
+radv_get_shader_name(struct radv_shader_variant_info *info,
+		     gl_shader_stage stage)
 {
 	switch (stage) {
-	case MESA_SHADER_VERTEX: return var->info.vs.as_ls ? "Vertex Shader as LS" : var->info.vs.as_es ? "Vertex Shader as ES" : "Vertex Shader as VS";
-	case MESA_SHADER_GEOMETRY: return "Geometry Shader";
-	case MESA_SHADER_FRAGMENT: return "Pixel Shader";
-	case MESA_SHADER_COMPUTE: return "Compute Shader";
-	case MESA_SHADER_TESS_CTRL: return "Tessellation Control Shader";
-	case MESA_SHADER_TESS_EVAL: return var->info.tes.as_es ? "Tessellation Evaluation Shader as ES" : "Tessellation Evaluation Shader as VS";
+	case MESA_SHADER_VERTEX:
+		if (info->vs.as_ls)
+			return "Vertex Shader as LS";
+		else if (info->vs.as_es)
+			return "Vertex Shader as ES";
+		else if (info->is_ngg)
+			return "Vertex Shader as ESGS";
+		else
+			return "Vertex Shader as VS";
+	case MESA_SHADER_TESS_CTRL:
+		return "Tessellation Control Shader";
+	case MESA_SHADER_TESS_EVAL:
+		if (info->tes.as_es)
+			return "Tessellation Evaluation Shader as ES";
+		else if (info->is_ngg)
+			return "Tessellation Evaluation Shader as ESGS";
+		else
+			return "Tessellation Evaluation Shader as VS";
+	case MESA_SHADER_GEOMETRY:
+		return "Geometry Shader";
+	case MESA_SHADER_FRAGMENT:
+		return "Pixel Shader";
+	case MESA_SHADER_COMPUTE:
+		return "Compute Shader";
 	default:
 		return "Unknown shader";
 	};
@@ -727,7 +1219,8 @@ generate_shader_stats(struct radv_device *device,
 		      gl_shader_stage stage,
 		      struct _mesa_string_buffer *buf)
 {
-	unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
+	enum chip_class chip_class = device->physical_device->rad_info.chip_class;
+	unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
 	struct ac_shader_config *conf;
 	unsigned max_simd_waves;
 	unsigned lds_per_wave = 0;
@@ -740,12 +1233,17 @@ generate_shader_stats(struct radv_device *device,
 		lds_per_wave = conf->lds_size * lds_increment +
 			       align(variant->info.fs.num_interp * 48,
 				     lds_increment);
+	} else if (stage == MESA_SHADER_COMPUTE) {
+		unsigned max_workgroup_size =
+			radv_nir_get_max_workgroup_size(chip_class, stage, variant->nir);
+		lds_per_wave = (conf->lds_size * lds_increment) /
+			       DIV_ROUND_UP(max_workgroup_size, 64);
 	}
 
 	if (conf->num_sgprs)
 		max_simd_waves =
 			MIN2(max_simd_waves,
-			     radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs);
+			     ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs);
 
 	if (conf->num_vgprs)
 		max_simd_waves =
@@ -793,7 +1291,7 @@ radv_shader_dump_stats(struct radv_device *device,
 
 	generate_shader_stats(device, variant, stage, buf);
 
-	fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage));
+	fprintf(file, "\n%s:\n", radv_get_shader_name(&variant->info, stage));
 	fprintf(file, "%s", buf->buf);
 
 	_mesa_string_buffer_destroy(buf);
@@ -824,13 +1322,13 @@ radv_GetShaderInfoAMD(VkDevice _device,
 		if (!pInfo) {
 			*pInfoSize = sizeof(VkShaderStatisticsInfoAMD);
 		} else {
-			unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256;
+			unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256;
 			struct ac_shader_config *conf = &variant->config;
 
 			VkShaderStatisticsInfoAMD statistics = {};
 			statistics.shaderStageMask = shaderStage;
 			statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
-			statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device);
+			statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class);
 			statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 
 			if (stage == MESA_SHADER_COMPUTE) {
@@ -866,7 +1364,7 @@ radv_GetShaderInfoAMD(VkDevice _device,
 	case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD:
 		buf = _mesa_string_buffer_create(NULL, 1024);
 
-		_mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage));
+		_mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(&variant->info, stage));
 		_mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string);
 		_mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string);
 		generate_shader_stats(device, variant, stage, buf);