X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_shader.c;h=3c50471c63b88c902b55d06ab482d323e36896c7;hb=b4477fa4d46345d1e8742c1d57c9dcc432edaf51;hp=ac36cecb67498b9248d3724d0e7f18ebee3d001a;hpb=0e10790558b01f09b9517495f7368860af47ee97;p=mesa.git diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index ac36cecb674..3c50471c63b 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -30,15 +30,16 @@ #include "radv_debug.h" #include "radv_private.h" #include "radv_shader.h" +#include "radv_shader_helper.h" #include "nir/nir.h" #include "nir/nir_builder.h" #include "spirv/nir_spirv.h" #include #include +#include #include "sid.h" -#include "gfx9d.h" #include "ac_binary.h" #include "ac_llvm_util.h" #include "ac_nir_to_llvm.h" @@ -51,11 +52,14 @@ static const struct nir_shader_compiler_options nir_options = { .vertex_id_zero_based = true, .lower_scmp = true, + .lower_flrp16 = true, .lower_flrp32 = true, .lower_flrp64 = true, .lower_device_index_to_zero = true, .lower_fsat = true, .lower_fdiv = true, + .lower_bitfield_insert_to_bitfield_select = true, + .lower_bitfield_extract = true, .lower_sub = true, .lower_pack_snorm_2x16 = true, .lower_pack_snorm_4x8 = true, @@ -69,7 +73,7 @@ static const struct nir_shader_compiler_options nir_options = { .lower_extract_word = true, .lower_ffma = true, .lower_fpow = true, - .vs_inputs_dual_locations = true, + .lower_mul_2x32_64 = true, .max_unroll_iterations = 32 }; @@ -89,7 +93,7 @@ VkResult radv_CreateShaderModule( sizeof(*module) + pCreateInfo->codeSize, 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); if (module == NULL) - return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); + return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); module->nir = NULL; module->size = pCreateInfo->codeSize; @@ -117,16 +121,37 @@ void radv_DestroyShaderModule( } void -radv_optimize_nir(struct nir_shader *shader) +radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively, + bool allow_copies) { bool progress; + unsigned lower_flrp = + (shader->options->lower_flrp16 ? 16 : 0) | + (shader->options->lower_flrp32 ? 32 : 0) | + (shader->options->lower_flrp64 ? 64 : 0); do { progress = false; + NIR_PASS(progress, shader, nir_split_array_vars, nir_var_function_temp); + NIR_PASS(progress, shader, nir_shrink_vec_array_vars, nir_var_function_temp); + NIR_PASS_V(shader, nir_lower_vars_to_ssa); - NIR_PASS_V(shader, nir_lower_64bit_pack); - NIR_PASS_V(shader, nir_lower_alu_to_scalar); + NIR_PASS_V(shader, nir_lower_pack); + + if (allow_copies) { + /* Only run this pass in the first call to + * radv_optimize_nir. Later calls assume that we've + * lowered away any copy_deref instructions and we + * don't want to introduce any more. + */ + NIR_PASS(progress, shader, nir_opt_find_array_copies); + } + + NIR_PASS(progress, shader, nir_opt_copy_prop_vars); + NIR_PASS(progress, shader, nir_opt_dead_write_vars); + + NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL); NIR_PASS_V(shader, nir_lower_phis_to_scalar); NIR_PASS(progress, shader, nir_copy_prop); @@ -138,18 +163,39 @@ radv_optimize_nir(struct nir_shader *shader) NIR_PASS(progress, shader, nir_opt_remove_phis); NIR_PASS(progress, shader, nir_opt_dce); } - NIR_PASS(progress, shader, nir_opt_if); + NIR_PASS(progress, shader, nir_opt_if, true); NIR_PASS(progress, shader, nir_opt_dead_cf); NIR_PASS(progress, shader, nir_opt_cse); - NIR_PASS(progress, shader, nir_opt_peephole_select, 8); - NIR_PASS(progress, shader, nir_opt_algebraic); + NIR_PASS(progress, shader, nir_opt_peephole_select, 8, true, true); NIR_PASS(progress, shader, nir_opt_constant_folding); + NIR_PASS(progress, shader, nir_opt_algebraic); + + if (lower_flrp != 0) { + bool lower_flrp_progress = false; + NIR_PASS(lower_flrp_progress, + shader, + nir_lower_flrp, + lower_flrp, + false /* always_precise */, + shader->options->lower_ffma); + if (lower_flrp_progress) { + NIR_PASS(progress, shader, + nir_opt_constant_folding); + progress = true; + } + + /* Nothing should rematerialize any flrps, so we only + * need to do this lowering once. + */ + lower_flrp = 0; + } + NIR_PASS(progress, shader, nir_opt_undef); NIR_PASS(progress, shader, nir_opt_conditional_discard); if (shader->options->max_unroll_iterations) { NIR_PASS(progress, shader, nir_opt_loop_unroll, 0); } - } while (progress); + } while (progress && !optimize_conservatively); NIR_PASS(progress, shader, nir_opt_shrink_load); NIR_PASS(progress, shader, nir_opt_move_load_ubo); @@ -160,25 +206,20 @@ radv_shader_compile_to_nir(struct radv_device *device, struct radv_shader_module *module, const char *entrypoint_name, gl_shader_stage stage, - const VkSpecializationInfo *spec_info) + const VkSpecializationInfo *spec_info, + const VkPipelineCreateFlags flags, + const struct radv_pipeline_layout *layout) { - if (strcmp(entrypoint_name, "main") != 0) { - radv_finishme("Multiple shaders per module not really supported"); - } - nir_shader *nir; - nir_function *entry_point; if (module->nir) { /* Some things such as our meta clear/blit code will give us a NIR * shader directly. In that case, we just ignore the SPIR-V entirely * and just use the NIR shader */ nir = module->nir; nir->options = &nir_options; - nir_validate_shader(nir); + nir_validate_shader(nir, "in internal shader"); assert(exec_list_length(&nir->functions) == 1); - struct exec_node *node = exec_list_get_head(&nir->functions); - entry_point = exec_node_data(nir_function, node, node); } else { uint32_t *spirv = (uint32_t *) module->data; assert(module->size % 4 == 0); @@ -204,35 +245,56 @@ radv_shader_compile_to_nir(struct radv_device *device, } } const struct spirv_to_nir_options spirv_options = { + .lower_ubo_ssbo_access_to_offsets = true, .caps = { + .amd_gcn_shader = true, + .amd_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT, + .amd_trinary_minmax = true, + .derivative_group = true, + .descriptor_array_dynamic_indexing = true, + .descriptor_array_non_uniform_indexing = true, + .descriptor_indexing = true, .device_group = true, .draw_parameters = true, + .float16 = true, .float64 = true, + .geometry_streams = true, .image_read_without_format = true, .image_write_without_format = true, - .tessellation = true, + .int8 = true, + .int16 = true, .int64 = true, + .int64_atomics = true, .multiview = true, + .physical_storage_buffer_address = true, + .runtime_descriptor_array = true, + .shader_viewport_index_layer = true, + .stencil_export = true, + .storage_8bit = true, + .storage_16bit = true, + .storage_image_ms = true, + .subgroup_arithmetic = true, .subgroup_ballot = true, .subgroup_basic = true, .subgroup_quad = true, .subgroup_shuffle = true, .subgroup_vote = true, + .tessellation = true, + .transform_feedback = true, .variable_pointers = true, - .gcn_shader = true, - .trinary_minmax = true, - .shader_viewport_index_layer = true, - .descriptor_array_dynamic_indexing = true, - .runtime_descriptor_array = true, }, + .ubo_addr_format = nir_address_format_32bit_index_offset, + .ssbo_addr_format = nir_address_format_32bit_index_offset, + .phys_ssbo_addr_format = nir_address_format_64bit_global, + .push_const_addr_format = nir_address_format_logical, + .shared_addr_format = nir_address_format_32bit_offset, }; - entry_point = spirv_to_nir(spirv, module->size / 4, - spec_entries, num_spec_entries, - stage, entrypoint_name, - &spirv_options, &nir_options); - nir = entry_point->shader; + nir = spirv_to_nir(spirv, module->size / 4, + spec_entries, num_spec_entries, + stage, entrypoint_name, + &spirv_options, &nir_options); assert(nir->info.stage == stage); - nir_validate_shader(nir); + nir_validate_shader(nir, "after spirv_to_nir"); free(spec_entries); @@ -240,49 +302,72 @@ radv_shader_compile_to_nir(struct radv_device *device, * inline functions. That way they get properly initialized at the top * of the function and not at the top of its caller. */ - NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local); + NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp); NIR_PASS_V(nir, nir_lower_returns); NIR_PASS_V(nir, nir_inline_functions); + NIR_PASS_V(nir, nir_opt_deref); /* Pick off the single entrypoint that we want */ foreach_list_typed_safe(nir_function, func, node, &nir->functions) { - if (func != entry_point) + if (func->is_entrypoint) + func->name = ralloc_strdup(func, "main"); + else exec_node_remove(&func->node); } assert(exec_list_length(&nir->functions) == 1); - entry_point->name = ralloc_strdup(entry_point, "main"); /* Make sure we lower constant initializers on output variables so that * nir_remove_dead_variables below sees the corresponding stores */ NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out); - NIR_PASS_V(nir, nir_remove_dead_variables, - nir_var_shader_in | nir_var_shader_out | nir_var_system_value); - /* Now that we've deleted all but the main function, we can go ahead and * lower the rest of the constant initializers. */ NIR_PASS_V(nir, nir_lower_constant_initializers, ~0); + + /* Split member structs. We do this before lower_io_to_temporaries so that + * it doesn't lower system values to temporaries by accident. + */ + NIR_PASS_V(nir, nir_split_var_copies); + NIR_PASS_V(nir, nir_split_per_member_structs); + + NIR_PASS_V(nir, nir_remove_dead_variables, + nir_var_shader_in | nir_var_shader_out | nir_var_system_value); + NIR_PASS_V(nir, nir_lower_system_values); NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays); + NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout); } /* Vulkan uses the separate-shader linking model */ nir->info.separate_shader = true; - nir_shader_gather_info(nir, entry_point->impl); + nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); static const nir_lower_tex_options tex_options = { .lower_txp = ~0, + .lower_tg4_offsets = true, }; nir_lower_tex(nir, &tex_options); nir_lower_vars_to_ssa(nir); - nir_lower_var_copies(nir); + + if (nir->info.stage == MESA_SHADER_VERTEX || + nir->info.stage == MESA_SHADER_GEOMETRY) { + NIR_PASS_V(nir, nir_lower_io_to_temporaries, + nir_shader_get_entrypoint(nir), true, true); + } else if (nir->info.stage == MESA_SHADER_TESS_EVAL|| + nir->info.stage == MESA_SHADER_FRAGMENT) { + NIR_PASS_V(nir, nir_lower_io_to_temporaries, + nir_shader_get_entrypoint(nir), true, false); + } + + nir_split_var_copies(nir); + nir_lower_global_vars_to_local(nir); - nir_remove_dead_variables(nir, nir_var_local); + nir_remove_dead_variables(nir, nir_var_function_temp); nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) { .subgroup_size = 64, .ballot_bit_size = 64, @@ -293,7 +378,15 @@ radv_shader_compile_to_nir(struct radv_device *device, .lower_vote_eq_to_ballot = 1, }); - radv_optimize_nir(nir); + nir_lower_load_const_to_scalar(nir); + + if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) + radv_optimize_nir(nir, false, true); + + /* We call nir_lower_var_copies() after the first radv_optimize_nir() + * to remove any copies introduced by nir_opt_find_array_copies(). + */ + nir_lower_var_copies(nir); /* Indirect lowering must be called after the radv_optimize_nir() loop * has been called at least once. Otherwise indirect lowering can @@ -301,7 +394,7 @@ radv_shader_compile_to_nir(struct radv_device *device, * considered too large for unrolling. */ ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class); - radv_optimize_nir(nir); + radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT, false); return nir; } @@ -339,8 +432,9 @@ radv_alloc_shader_memory(struct radv_device *device, slab->bo = device->ws->buffer_create(device->ws, slab->size, 256, RADEON_DOMAIN_VRAM, RADEON_FLAG_NO_INTERPROCESS_SHARING | - device->physical_device->cpdma_prefetch_writes_memory ? - 0 : RADEON_FLAG_READ_ONLY); + (device->physical_device->cpdma_prefetch_writes_memory ? + 0 : RADEON_FLAG_READ_ONLY), + RADV_BO_PRIORITY_SHADER); slab->ptr = (char*)device->ws->buffer_map(slab->bo); list_inithead(&slab->shaders); @@ -364,37 +458,59 @@ radv_destroy_shader_slabs(struct radv_device *device) mtx_destroy(&device->shader_slab_mutex); } +/* For the UMR disassembler. */ +#define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */ +#define DEBUGGER_NUM_MARKERS 5 + +static unsigned +radv_get_shader_binary_size(struct ac_shader_binary *binary) +{ + return binary->code_size + DEBUGGER_NUM_MARKERS * 4; +} + static void radv_fill_shader_variant(struct radv_device *device, struct radv_shader_variant *variant, + struct radv_nir_compiler_options *options, struct ac_shader_binary *binary, gl_shader_stage stage) { bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0; + struct radv_shader_info *info = &variant->info.info; unsigned vgpr_comp_cnt = 0; - if (scratch_enabled && !device->llvm_supports_spill) - radv_finishme("shader scratch support only available with LLVM 4.0"); - - variant->code_size = binary->code_size; + variant->code_size = radv_get_shader_binary_size(binary); variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | - S_00B12C_SCRATCH_EN(scratch_enabled); - - variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | + S_00B12C_USER_SGPR_MSB(variant->info.num_user_sgprs >> 5) | + S_00B12C_SCRATCH_EN(scratch_enabled) | + S_00B12C_SO_BASE0_EN(!!info->so.strides[0]) | + S_00B12C_SO_BASE1_EN(!!info->so.strides[1]) | + S_00B12C_SO_BASE2_EN(!!info->so.strides[2]) | + S_00B12C_SO_BASE3_EN(!!info->so.strides[3]) | + S_00B12C_SO_EN(!!info->so.num_outputs); + + variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) | S_00B848_DX10_CLAMP(1) | S_00B848_FLOAT_MODE(variant->config.float_mode); switch (stage) { case MESA_SHADER_TESS_EVAL: - vgpr_comp_cnt = 3; + if (options->key.tes.as_es) { + assert(device->physical_device->rad_info.chip_class <= GFX8); + vgpr_comp_cnt = info->uses_prim_id ? 3 : 2; + } else { + bool enable_prim_id = options->key.tes.export_prim_id || info->uses_prim_id; + vgpr_comp_cnt = enable_prim_id ? 3 : 2; + } variant->rsrc2 |= S_00B12C_OC_LDS_EN(1); break; case MESA_SHADER_TESS_CTRL: - if (device->physical_device->rad_info.chip_class >= GFX9) + if (device->physical_device->rad_info.chip_class >= GFX9) { vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt; - else + } else { variant->rsrc2 |= S_00B12C_OC_LDS_EN(1); + } break; case MESA_SHADER_VERTEX: case MESA_SHADER_GEOMETRY: @@ -402,8 +518,7 @@ radv_fill_shader_variant(struct radv_device *device, break; case MESA_SHADER_FRAGMENT: break; - case MESA_SHADER_COMPUTE: { - struct radv_shader_info *info = &variant->info.info; + case MESA_SHADER_COMPUTE: variant->rsrc2 |= S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) | S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) | @@ -413,7 +528,6 @@ radv_fill_shader_variant(struct radv_device *device, S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) | S_00B84C_LDS_SIZE(variant->config.lds_size); break; - } default: unreachable("unsupported shader type"); break; @@ -421,14 +535,13 @@ radv_fill_shader_variant(struct radv_device *device, if (device->physical_device->rad_info.chip_class >= GFX9 && stage == MESA_SHADER_GEOMETRY) { - struct radv_shader_info *info = &variant->info.info; unsigned es_type = variant->info.gs.es_type; unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt; if (es_type == MESA_SHADER_VERTEX) { es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt; } else if (es_type == MESA_SHADER_TESS_EVAL) { - es_vgpr_comp_cnt = 3; + es_vgpr_comp_cnt = info->uses_prim_id ? 3 : 2; } else { unreachable("invalid shader ES type"); } @@ -436,26 +549,73 @@ radv_fill_shader_variant(struct radv_device *device, /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and * VGPR[0:4] are always loaded. */ - if (info->uses_invocation_id) + if (info->uses_invocation_id) { gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */ - else if (info->uses_prim_id) + } else if (info->uses_prim_id) { gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */ - else if (variant->info.gs.vertices_in >= 3) + } else if (variant->info.gs.vertices_in >= 3) { gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */ - else + } else { gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */ + } variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL); } else if (device->physical_device->rad_info.chip_class >= GFX9 && - stage == MESA_SHADER_TESS_CTRL) + stage == MESA_SHADER_TESS_CTRL) { variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt); - else + } else { variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt); + } void *ptr = radv_alloc_shader_memory(device, variant); memcpy(ptr, binary->code, binary->code_size); + + /* Add end-of-code markers for the UMR disassembler. */ + uint32_t *ptr32 = (uint32_t *)ptr + binary->code_size / 4; + for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++) + ptr32[i] = DEBUGGER_END_OF_CODE_MARKER; + +} + +static void radv_init_llvm_target() +{ + LLVMInitializeAMDGPUTargetInfo(); + LLVMInitializeAMDGPUTarget(); + LLVMInitializeAMDGPUTargetMC(); + LLVMInitializeAMDGPUAsmPrinter(); + + /* For inline assembly. */ + LLVMInitializeAMDGPUAsmParser(); + + /* Workaround for bug in llvm 4.0 that causes image intrinsics + * to disappear. + * https://reviews.llvm.org/D26348 + * + * Workaround for bug in llvm that causes the GPU to hang in presence + * of nested loops because there is an exec mask issue. The proper + * solution is to fix LLVM but this might require a bunch of work. + * https://bugs.llvm.org/show_bug.cgi?id=37744 + * + * "mesa" is the prefix for error messages. + */ + if (HAVE_LLVM >= 0x0800) { + const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" }; + LLVMParseCommandLineOptions(2, argv, NULL); + + } else { + const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false", + "-amdgpu-skip-threshold=1" }; + LLVMParseCommandLineOptions(3, argv, NULL); + } +} + +static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT; + +static void radv_init_llvm_once(void) +{ + call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target); } static struct radv_shader_variant * @@ -473,40 +633,50 @@ shader_variant_create(struct radv_device *device, enum ac_target_machine_options tm_options = 0; struct radv_shader_variant *variant; struct ac_shader_binary binary; - LLVMTargetMachineRef tm; - + struct ac_llvm_compiler ac_llvm; + bool thread_compiler; variant = calloc(1, sizeof(struct radv_shader_variant)); if (!variant) return NULL; options->family = chip_family; options->chip_class = device->physical_device->rad_info.chip_class; - options->dump_shader = radv_can_dump_shader(device, module); + options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader); options->dump_preoptir = options->dump_shader && device->instance->debug_flags & RADV_DEBUG_PREOPTIR; options->record_llvm_ir = device->keep_shader_info; + options->check_ir = device->instance->debug_flags & RADV_DEBUG_CHECKIR; options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size; + options->address32_hi = device->physical_device->rad_info.address32_hi; if (options->supports_spill) tm_options |= AC_TM_SUPPORTS_SPILL; if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED) tm_options |= AC_TM_SISCHED; - tm = ac_create_target_machine(chip_family, tm_options); - + if (options->check_ir) + tm_options |= AC_TM_CHECK_IR; + if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT) + tm_options |= AC_TM_NO_LOAD_STORE_OPT; + + thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM); + radv_init_llvm_once(); + radv_init_llvm_compiler(&ac_llvm, + thread_compiler, + chip_family, tm_options); if (gs_copy_shader) { assert(shader_count == 1); - radv_compile_gs_copy_shader(tm, *shaders, &binary, + radv_compile_gs_copy_shader(&ac_llvm, *shaders, &binary, &variant->config, &variant->info, options); } else { - radv_compile_nir_shader(tm, &binary, &variant->config, + radv_compile_nir_shader(&ac_llvm, &binary, &variant->config, &variant->info, shaders, shader_count, options); } - LLVMDisposeTargetMachine(tm); + radv_destroy_llvm_compiler(&ac_llvm, thread_compiler); - radv_fill_shader_variant(device, variant, &binary, stage); + radv_fill_shader_variant(device, variant, options, &binary, stage); if (code_out) { *code_out = binary.code; @@ -551,7 +721,7 @@ radv_shader_variant_create(struct radv_device *device, options.key = *key; options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH); - options.supports_spill = device->llvm_supports_spill; + options.supports_spill = true; return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, &options, false, code_out, code_size_out); @@ -610,21 +780,13 @@ generate_shader_stats(struct radv_device *device, gl_shader_stage stage, struct _mesa_string_buffer *buf) { - unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256; + enum chip_class chip_class = device->physical_device->rad_info.chip_class; + unsigned lds_increment = chip_class >= GFX7 ? 512 : 256; struct ac_shader_config *conf; unsigned max_simd_waves; unsigned lds_per_wave = 0; - switch (device->physical_device->rad_info.family) { - /* These always have 8 waves: */ - case CHIP_POLARIS10: - case CHIP_POLARIS11: - case CHIP_POLARIS12: - max_simd_waves = 8; - break; - default: - max_simd_waves = 10; - } + max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family); conf = &variant->config; @@ -632,12 +794,17 @@ generate_shader_stats(struct radv_device *device, lds_per_wave = conf->lds_size * lds_increment + align(variant->info.fs.num_interp * 48, lds_increment); + } else if (stage == MESA_SHADER_COMPUTE) { + unsigned max_workgroup_size = + radv_nir_get_max_workgroup_size(chip_class, variant->nir); + lds_per_wave = (conf->lds_size * lds_increment) / + DIV_ROUND_UP(max_workgroup_size, 64); } if (conf->num_sgprs) max_simd_waves = MIN2(max_simd_waves, - radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs); + ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs); if (conf->num_vgprs) max_simd_waves = @@ -709,20 +876,20 @@ radv_GetShaderInfoAMD(VkDevice _device, /* Spec doesn't indicate what to do if the stage is invalid, so just * return no info for this. */ if (!variant) - return vk_error(VK_ERROR_FEATURE_NOT_PRESENT); + return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT); switch (infoType) { case VK_SHADER_INFO_TYPE_STATISTICS_AMD: if (!pInfo) { *pInfoSize = sizeof(VkShaderStatisticsInfoAMD); } else { - unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256; + unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= GFX7 ? 512 : 256; struct ac_shader_config *conf = &variant->config; VkShaderStatisticsInfoAMD statistics = {}; statistics.shaderStageMask = shaderStage; statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS; - statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device); + statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class); statistics.numAvailableSgprs = statistics.numPhysicalSgprs; if (stage == MESA_SHADER_COMPUTE) { @@ -730,7 +897,7 @@ radv_GetShaderInfoAMD(VkDevice _device, unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2]; statistics.numAvailableVgprs = statistics.numPhysicalVgprs / - ceil(workgroup_size / statistics.numPhysicalVgprs); + ceil((double)workgroup_size / statistics.numPhysicalVgprs); statistics.computeWorkGroupSize[0] = local_size[0]; statistics.computeWorkGroupSize[1] = local_size[1]; @@ -759,6 +926,7 @@ radv_GetShaderInfoAMD(VkDevice _device, buf = _mesa_string_buffer_create(NULL, 1024); _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage)); + _mesa_string_buffer_printf(buf, "%s\n\n", variant->llvm_ir_string); _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string); generate_shader_stats(device, variant, stage, buf);