X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_shader.c;h=76790a19047a86abdad5668690675f0679f1f572;hb=135e4d434f622fa1d7275bdb72f859e1c1b1976e;hp=87deb7c3ab7210312a1693ea687289f86bbcc7d3;hpb=64d9bd149aa7f5a09f73cae07499577933722fb2;p=mesa.git diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 87deb7c3ab7..76790a19047 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -36,10 +36,10 @@ #include #include +#include #include "sid.h" #include "gfx9d.h" -#include "r600d_common.h" #include "ac_binary.h" #include "ac_llvm_util.h" #include "ac_nir_to_llvm.h" @@ -47,10 +47,14 @@ #include "util/debug.h" #include "ac_exp_param.h" +#include "util/string_buffer.h" + static const struct nir_shader_compiler_options nir_options = { .vertex_id_zero_based = true, .lower_scmp = true, .lower_flrp32 = true, + .lower_flrp64 = true, + .lower_device_index_to_zero = true, .lower_fsat = true, .lower_fdiv = true, .lower_sub = true, @@ -64,6 +68,9 @@ static const struct nir_shader_compiler_options nir_options = { .lower_unpack_unorm_4x8 = true, .lower_extract_byte = true, .lower_extract_word = true, + .lower_ffma = true, + .lower_fpow = true, + .vs_inputs_dual_locations = true, .max_unroll_iterations = 32 }; @@ -83,7 +90,7 @@ VkResult radv_CreateShaderModule( sizeof(*module) + pCreateInfo->codeSize, 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); if (module == NULL) - return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); + return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); module->nir = NULL; module->size = pCreateInfo->codeSize; @@ -110,8 +117,8 @@ void radv_DestroyShaderModule( vk_free2(&device->alloc, pAllocator, module); } -static void -radv_optimize_nir(struct nir_shader *shader) +void +radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively) { bool progress; @@ -119,7 +126,7 @@ radv_optimize_nir(struct nir_shader *shader) progress = false; NIR_PASS_V(shader, nir_lower_vars_to_ssa); - NIR_PASS_V(shader, nir_lower_64bit_pack); + NIR_PASS_V(shader, nir_lower_pack); NIR_PASS_V(shader, nir_lower_alu_to_scalar); NIR_PASS_V(shader, nir_lower_phis_to_scalar); @@ -143,7 +150,10 @@ radv_optimize_nir(struct nir_shader *shader) if (shader->options->max_unroll_iterations) { NIR_PASS(progress, shader, nir_opt_loop_unroll, 0); } - } while (progress); + } while (progress && !optimize_conservatively); + + NIR_PASS(progress, shader, nir_opt_shrink_load); + NIR_PASS(progress, shader, nir_opt_move_load_ubo); } nir_shader * @@ -151,12 +161,9 @@ radv_shader_compile_to_nir(struct radv_device *device, struct radv_shader_module *module, const char *entrypoint_name, gl_shader_stage stage, - const VkSpecializationInfo *spec_info) + const VkSpecializationInfo *spec_info, + const VkPipelineCreateFlags flags) { - if (strcmp(entrypoint_name, "main") != 0) { - radv_finishme("Multiple shaders per module not really supported"); - } - nir_shader *nir; nir_function *entry_point; if (module->nir) { @@ -174,8 +181,8 @@ radv_shader_compile_to_nir(struct radv_device *device, uint32_t *spirv = (uint32_t *) module->data; assert(module->size % 4 == 0); - if (device->debug_flags & RADV_DEBUG_DUMP_SPIRV) - radv_print_spirv(module, stderr); + if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV) + radv_print_spirv(spirv, module->size, stderr); uint32_t num_spec_entries = 0; struct nir_spirv_specialization *spec_entries = NULL; @@ -194,21 +201,35 @@ radv_shader_compile_to_nir(struct radv_device *device, spec_entries[i].data32 = *(const uint32_t *)data; } } - const struct nir_spirv_supported_extensions supported_ext = { - .draw_parameters = true, - .float64 = true, - .image_read_without_format = true, - .image_write_without_format = true, - .tessellation = true, - .int64 = true, - .multiview = true, - .variable_pointers = true, + const struct spirv_to_nir_options spirv_options = { + .caps = { + .device_group = true, + .draw_parameters = true, + .float64 = true, + .image_read_without_format = true, + .image_write_without_format = true, + .tessellation = true, + .int64 = true, + .multiview = true, + .subgroup_ballot = true, + .subgroup_basic = true, + .subgroup_quad = true, + .subgroup_shuffle = true, + .subgroup_vote = true, + .variable_pointers = true, + .gcn_shader = true, + .trinary_minmax = true, + .shader_viewport_index_layer = true, + .descriptor_array_dynamic_indexing = true, + .runtime_descriptor_array = true, + }, }; entry_point = spirv_to_nir(spirv, module->size / 4, spec_entries, num_spec_entries, - stage, entrypoint_name, &supported_ext, &nir_options); + stage, entrypoint_name, + &spirv_options, &nir_options); nir = entry_point->shader; - assert(nir->stage == stage); + assert(nir->info.stage == stage); nir_validate_shader(nir); free(spec_entries); @@ -229,6 +250,11 @@ radv_shader_compile_to_nir(struct radv_device *device, assert(exec_list_length(&nir->functions) == 1); entry_point->name = ralloc_strdup(entry_point, "main"); + /* Make sure we lower constant initializers on output variables so that + * nir_remove_dead_variables below sees the corresponding stores + */ + NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_shader_out); + NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_shader_in | nir_var_shader_out | nir_var_system_value); @@ -245,12 +271,6 @@ radv_shader_compile_to_nir(struct radv_device *device, nir_shader_gather_info(nir, entry_point->impl); - nir_variable_mode indirect_mask = 0; - indirect_mask |= nir_var_shader_in; - indirect_mask |= nir_var_local; - - nir_lower_indirect_derefs(nir, indirect_mask); - static const nir_lower_tex_options tex_options = { .lower_txp = ~0, }; @@ -258,13 +278,42 @@ radv_shader_compile_to_nir(struct radv_device *device, nir_lower_tex(nir, &tex_options); nir_lower_vars_to_ssa(nir); + + if (nir->info.stage == MESA_SHADER_VERTEX || + nir->info.stage == MESA_SHADER_GEOMETRY) { + NIR_PASS_V(nir, nir_lower_io_to_temporaries, + nir_shader_get_entrypoint(nir), true, true); + } else if (nir->info.stage == MESA_SHADER_TESS_EVAL|| + nir->info.stage == MESA_SHADER_FRAGMENT) { + NIR_PASS_V(nir, nir_lower_io_to_temporaries, + nir_shader_get_entrypoint(nir), true, false); + } + + nir_split_var_copies(nir); nir_lower_var_copies(nir); + nir_lower_global_vars_to_local(nir); nir_remove_dead_variables(nir, nir_var_local); - radv_optimize_nir(nir); - - if (device->debug_flags & RADV_DEBUG_DUMP_SHADERS) - nir_print_shader(nir, stderr); + nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) { + .subgroup_size = 64, + .ballot_bit_size = 64, + .lower_to_scalar = 1, + .lower_subgroup_masks = 1, + .lower_shuffle = 1, + .lower_shuffle_to_32bit = 1, + .lower_vote_eq_to_ballot = 1, + }); + + if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) + radv_optimize_nir(nir, false); + + /* Indirect lowering must be called after the radv_optimize_nir() loop + * has been called at least once. Otherwise indirect lowering can + * bloat the instruction count of the loop and cause it to be + * considered too large for unrolling. + */ + ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class); + radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT); return nir; } @@ -300,7 +349,10 @@ radv_alloc_shader_memory(struct radv_device *device, slab->size = 256 * 1024; slab->bo = device->ws->buffer_create(device->ws, slab->size, 256, - RADEON_DOMAIN_VRAM, 0); + RADEON_DOMAIN_VRAM, + RADEON_FLAG_NO_INTERPROCESS_SHARING | + device->physical_device->cpdma_prefetch_writes_memory ? + 0 : RADEON_FLAG_READ_ONLY); slab->ptr = (char*)device->ws->buffer_map(slab->bo); list_inithead(&slab->shaders); @@ -331,21 +383,29 @@ radv_fill_shader_variant(struct radv_device *device, gl_shader_stage stage) { bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0; + struct radv_shader_info *info = &variant->info.info; unsigned vgpr_comp_cnt = 0; - if (scratch_enabled && !device->llvm_supports_spill) - radv_finishme("shader scratch support only available with LLVM 4.0"); - variant->code_size = binary->code_size; variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | - S_00B12C_SCRATCH_EN(scratch_enabled); + S_00B12C_SCRATCH_EN(scratch_enabled); + + variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | + S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) | + S_00B848_DX10_CLAMP(1) | + S_00B848_FLOAT_MODE(variant->config.float_mode); switch (stage) { case MESA_SHADER_TESS_EVAL: vgpr_comp_cnt = 3; - /* fallthrough */ + variant->rsrc2 |= S_00B12C_OC_LDS_EN(1); + break; case MESA_SHADER_TESS_CTRL: - variant->rsrc2 |= S_00B42C_OC_LDS_EN(1); + if (device->physical_device->rad_info.chip_class >= GFX9) { + vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt; + } else { + variant->rsrc2 |= S_00B12C_OC_LDS_EN(1); + } break; case MESA_SHADER_VERTEX: case MESA_SHADER_GEOMETRY: @@ -355,9 +415,12 @@ radv_fill_shader_variant(struct radv_device *device, break; case MESA_SHADER_COMPUTE: variant->rsrc2 |= - S_00B84C_TGID_X_EN(1) | S_00B84C_TGID_Y_EN(1) | - S_00B84C_TGID_Z_EN(1) | S_00B84C_TIDIG_COMP_CNT(2) | - S_00B84C_TG_SIZE_EN(1) | + S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) | + S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) | + S_00B84C_TGID_Z_EN(info->cs.uses_block_id[2]) | + S_00B84C_TIDIG_COMP_CNT(info->cs.uses_thread_id[2] ? 2 : + info->cs.uses_thread_id[1] ? 1 : 0) | + S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) | S_00B84C_LDS_SIZE(variant->config.lds_size); break; default: @@ -365,27 +428,134 @@ radv_fill_shader_variant(struct radv_device *device, break; } - variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | - S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) | - S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) | - S_00B848_DX10_CLAMP(1) | - S_00B848_FLOAT_MODE(variant->config.float_mode); + if (device->physical_device->rad_info.chip_class >= GFX9 && + stage == MESA_SHADER_GEOMETRY) { + unsigned es_type = variant->info.gs.es_type; + unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt; + + if (es_type == MESA_SHADER_VERTEX) { + es_vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt; + } else if (es_type == MESA_SHADER_TESS_EVAL) { + es_vgpr_comp_cnt = 3; + } else { + unreachable("invalid shader ES type"); + } + + /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and + * VGPR[0:4] are always loaded. + */ + if (info->uses_invocation_id) { + gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */ + } else if (info->uses_prim_id) { + gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */ + } else if (variant->info.gs.vertices_in >= 3) { + gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */ + } else { + gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */ + } + + variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); + variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | + S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL); + } else if (device->physical_device->rad_info.chip_class >= GFX9 && + stage == MESA_SHADER_TESS_CTRL) { + variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt); + } else { + variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt); + } void *ptr = radv_alloc_shader_memory(device, variant); memcpy(ptr, binary->code, binary->code_size); } +static void radv_init_llvm_target() +{ + LLVMInitializeAMDGPUTargetInfo(); + LLVMInitializeAMDGPUTarget(); + LLVMInitializeAMDGPUTargetMC(); + LLVMInitializeAMDGPUAsmPrinter(); + + /* For inline assembly. */ + LLVMInitializeAMDGPUAsmParser(); + + /* Workaround for bug in llvm 4.0 that causes image intrinsics + * to disappear. + * https://reviews.llvm.org/D26348 + * + * Workaround for bug in llvm that causes the GPU to hang in presence + * of nested loops because there is an exec mask issue. The proper + * solution is to fix LLVM but this might require a bunch of work. + * https://bugs.llvm.org/show_bug.cgi?id=37744 + * + * "mesa" is the prefix for error messages. + */ + const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false", + "-amdgpu-skip-threshold=1" }; + LLVMParseCommandLineOptions(3, argv, NULL); +} + +static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT; + +static LLVMTargetRef radv_get_llvm_target(const char *triple) +{ + LLVMTargetRef target = NULL; + char *err_message = NULL; + + call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target); + + if (LLVMGetTargetFromTriple(triple, &target, &err_message)) { + fprintf(stderr, "Cannot find target for triple %s ", triple); + if (err_message) { + fprintf(stderr, "%s\n", err_message); + } + LLVMDisposeMessage(err_message); + return NULL; + } + return target; +} + +static LLVMTargetMachineRef radv_create_target_machine(enum radeon_family family, + enum ac_target_machine_options tm_options, + const char **out_triple) +{ + assert(family >= CHIP_TAHITI); + char features[256]; + const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" : "amdgcn--"; + LLVMTargetRef target = radv_get_llvm_target(triple); + + snprintf(features, sizeof(features), + "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s", + tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "", + tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "", + tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "", + tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : ""); + + LLVMTargetMachineRef tm = LLVMCreateTargetMachine( + target, + triple, + ac_get_llvm_processor_name(family), + features, + LLVMCodeGenLevelDefault, + LLVMRelocDefault, + LLVMCodeModelDefault); + + if (out_triple) + *out_triple = triple; + return tm; +} + static struct radv_shader_variant * shader_variant_create(struct radv_device *device, - struct nir_shader *shader, + struct radv_shader_module *module, + struct nir_shader * const *shaders, + int shader_count, gl_shader_stage stage, - struct ac_nir_compiler_options *options, + struct radv_nir_compiler_options *options, bool gs_copy_shader, void **code_out, unsigned *code_size_out) { enum radeon_family chip_family = device->physical_device->rad_info.family; - bool dump_shaders = device->debug_flags & RADV_DEBUG_DUMP_SHADERS; enum ac_target_machine_options tm_options = 0; struct radv_shader_variant *variant; struct ac_shader_binary binary; @@ -397,20 +567,28 @@ shader_variant_create(struct radv_device *device, options->family = chip_family; options->chip_class = device->physical_device->rad_info.chip_class; + options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader); + options->dump_preoptir = options->dump_shader && + device->instance->debug_flags & RADV_DEBUG_PREOPTIR; + options->record_llvm_ir = device->keep_shader_info; + options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size; + options->address32_hi = device->physical_device->rad_info.address32_hi; if (options->supports_spill) tm_options |= AC_TM_SUPPORTS_SPILL; if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED) tm_options |= AC_TM_SISCHED; - tm = ac_create_target_machine(chip_family, tm_options); + tm = radv_create_target_machine(chip_family, tm_options, NULL); if (gs_copy_shader) { - ac_create_gs_copy_shader(tm, shader, &binary, &variant->config, - &variant->info, options, dump_shaders); + assert(shader_count == 1); + radv_compile_gs_copy_shader(tm, *shaders, &binary, + &variant->config, &variant->info, + options); } else { - ac_compile_nir_shader(tm, &binary, &variant->config, - &variant->info, shader, options, - dump_shaders); + radv_compile_nir_shader(tm, &binary, &variant->config, + &variant->info, shaders, shader_count, + options); } LLVMDisposeTargetMachine(tm); @@ -428,8 +606,14 @@ shader_variant_create(struct radv_device *device, free(binary.relocs); variant->ref_count = 1; - if (device->trace_bo) { + if (device->keep_shader_info) { variant->disasm_string = binary.disasm_string; + variant->llvm_ir_string = binary.llvm_ir_string; + if (!gs_copy_shader && !module->nir) { + variant->nir = *shaders; + variant->spirv = (uint32_t *)module->data; + variant->spirv_size = module->size; + } } else { free(binary.disasm_string); } @@ -439,22 +623,24 @@ shader_variant_create(struct radv_device *device, struct radv_shader_variant * radv_shader_variant_create(struct radv_device *device, - struct nir_shader *shader, + struct radv_shader_module *module, + struct nir_shader *const *shaders, + int shader_count, struct radv_pipeline_layout *layout, - const struct ac_shader_variant_key *key, + const struct radv_shader_variant_key *key, void **code_out, unsigned *code_size_out) { - struct ac_nir_compiler_options options = {0}; + struct radv_nir_compiler_options options = {0}; options.layout = layout; if (key) options.key = *key; - options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH); - options.supports_spill = device->llvm_supports_spill; + options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH); + options.supports_spill = true; - return shader_variant_create(device, shader, shader->stage, + return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, &options, false, code_out, code_size_out); } @@ -465,11 +651,11 @@ radv_create_gs_copy_shader(struct radv_device *device, unsigned *code_size_out, bool multiview) { - struct ac_nir_compiler_options options = {0}; + struct radv_nir_compiler_options options = {0}; options.key.has_multiview_view_index = multiview; - return shader_variant_create(device, shader, MESA_SHADER_VERTEX, + return shader_variant_create(device, NULL, &shader, 1, MESA_SHADER_VERTEX, &options, true, code_out, code_size_out); } @@ -484,38 +670,12 @@ radv_shader_variant_destroy(struct radv_device *device, list_del(&variant->slab_list); mtx_unlock(&device->shader_slab_mutex); + ralloc_free(variant->nir); free(variant->disasm_string); + free(variant->llvm_ir_string); free(variant); } -uint32_t -radv_shader_stage_to_user_data_0(gl_shader_stage stage, bool has_gs, - bool has_tess) -{ - switch (stage) { - case MESA_SHADER_FRAGMENT: - return R_00B030_SPI_SHADER_USER_DATA_PS_0; - case MESA_SHADER_VERTEX: - if (has_tess) - return R_00B530_SPI_SHADER_USER_DATA_LS_0; - else - return has_gs ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : R_00B130_SPI_SHADER_USER_DATA_VS_0; - case MESA_SHADER_GEOMETRY: - return R_00B230_SPI_SHADER_USER_DATA_GS_0; - case MESA_SHADER_COMPUTE: - return R_00B900_COMPUTE_USER_DATA_0; - case MESA_SHADER_TESS_CTRL: - return R_00B430_SPI_SHADER_USER_DATA_HS_0; - case MESA_SHADER_TESS_EVAL: - if (has_gs) - return R_00B330_SPI_SHADER_USER_DATA_ES_0; - else - return R_00B130_SPI_SHADER_USER_DATA_VS_0; - default: - unreachable("unknown shader"); - } -} - const char * radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage) { @@ -531,3 +691,177 @@ radv_get_shader_name(struct radv_shader_variant *var, gl_shader_stage stage) }; } +static void +generate_shader_stats(struct radv_device *device, + struct radv_shader_variant *variant, + gl_shader_stage stage, + struct _mesa_string_buffer *buf) +{ + unsigned lds_increment = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256; + struct ac_shader_config *conf; + unsigned max_simd_waves; + unsigned lds_per_wave = 0; + + max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family); + + conf = &variant->config; + + if (stage == MESA_SHADER_FRAGMENT) { + lds_per_wave = conf->lds_size * lds_increment + + align(variant->info.fs.num_interp * 48, + lds_increment); + } + + if (conf->num_sgprs) + max_simd_waves = + MIN2(max_simd_waves, + radv_get_num_physical_sgprs(device->physical_device) / conf->num_sgprs); + + if (conf->num_vgprs) + max_simd_waves = + MIN2(max_simd_waves, + RADV_NUM_PHYSICAL_VGPRS / conf->num_vgprs); + + /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD + * that PS can use. + */ + if (lds_per_wave) + max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave); + + if (stage == MESA_SHADER_FRAGMENT) { + _mesa_string_buffer_printf(buf, "*** SHADER CONFIG ***\n" + "SPI_PS_INPUT_ADDR = 0x%04x\n" + "SPI_PS_INPUT_ENA = 0x%04x\n", + conf->spi_ps_input_addr, conf->spi_ps_input_ena); + } + + _mesa_string_buffer_printf(buf, "*** SHADER STATS ***\n" + "SGPRS: %d\n" + "VGPRS: %d\n" + "Spilled SGPRs: %d\n" + "Spilled VGPRs: %d\n" + "PrivMem VGPRS: %d\n" + "Code Size: %d bytes\n" + "LDS: %d blocks\n" + "Scratch: %d bytes per wave\n" + "Max Waves: %d\n" + "********************\n\n\n", + conf->num_sgprs, conf->num_vgprs, + conf->spilled_sgprs, conf->spilled_vgprs, + variant->info.private_mem_vgprs, variant->code_size, + conf->lds_size, conf->scratch_bytes_per_wave, + max_simd_waves); +} + +void +radv_shader_dump_stats(struct radv_device *device, + struct radv_shader_variant *variant, + gl_shader_stage stage, + FILE *file) +{ + struct _mesa_string_buffer *buf = _mesa_string_buffer_create(NULL, 256); + + generate_shader_stats(device, variant, stage, buf); + + fprintf(file, "\n%s:\n", radv_get_shader_name(variant, stage)); + fprintf(file, "%s", buf->buf); + + _mesa_string_buffer_destroy(buf); +} + +VkResult +radv_GetShaderInfoAMD(VkDevice _device, + VkPipeline _pipeline, + VkShaderStageFlagBits shaderStage, + VkShaderInfoTypeAMD infoType, + size_t* pInfoSize, + void* pInfo) +{ + RADV_FROM_HANDLE(radv_device, device, _device); + RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline); + gl_shader_stage stage = vk_to_mesa_shader_stage(shaderStage); + struct radv_shader_variant *variant = pipeline->shaders[stage]; + struct _mesa_string_buffer *buf; + VkResult result = VK_SUCCESS; + + /* Spec doesn't indicate what to do if the stage is invalid, so just + * return no info for this. */ + if (!variant) + return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT); + + switch (infoType) { + case VK_SHADER_INFO_TYPE_STATISTICS_AMD: + if (!pInfo) { + *pInfoSize = sizeof(VkShaderStatisticsInfoAMD); + } else { + unsigned lds_multiplier = device->physical_device->rad_info.chip_class >= CIK ? 512 : 256; + struct ac_shader_config *conf = &variant->config; + + VkShaderStatisticsInfoAMD statistics = {}; + statistics.shaderStageMask = shaderStage; + statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS; + statistics.numPhysicalSgprs = radv_get_num_physical_sgprs(device->physical_device); + statistics.numAvailableSgprs = statistics.numPhysicalSgprs; + + if (stage == MESA_SHADER_COMPUTE) { + unsigned *local_size = variant->nir->info.cs.local_size; + unsigned workgroup_size = local_size[0] * local_size[1] * local_size[2]; + + statistics.numAvailableVgprs = statistics.numPhysicalVgprs / + ceil(workgroup_size / statistics.numPhysicalVgprs); + + statistics.computeWorkGroupSize[0] = local_size[0]; + statistics.computeWorkGroupSize[1] = local_size[1]; + statistics.computeWorkGroupSize[2] = local_size[2]; + } else { + statistics.numAvailableVgprs = statistics.numPhysicalVgprs; + } + + statistics.resourceUsage.numUsedVgprs = conf->num_vgprs; + statistics.resourceUsage.numUsedSgprs = conf->num_sgprs; + statistics.resourceUsage.ldsSizePerLocalWorkGroup = 32768; + statistics.resourceUsage.ldsUsageSizeInBytes = conf->lds_size * lds_multiplier; + statistics.resourceUsage.scratchMemUsageInBytes = conf->scratch_bytes_per_wave; + + size_t size = *pInfoSize; + *pInfoSize = sizeof(statistics); + + memcpy(pInfo, &statistics, MIN2(size, *pInfoSize)); + + if (size < *pInfoSize) + result = VK_INCOMPLETE; + } + + break; + case VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD: + buf = _mesa_string_buffer_create(NULL, 1024); + + _mesa_string_buffer_printf(buf, "%s:\n", radv_get_shader_name(variant, stage)); + _mesa_string_buffer_printf(buf, "%s\n\n", variant->disasm_string); + generate_shader_stats(device, variant, stage, buf); + + /* Need to include the null terminator. */ + size_t length = buf->length + 1; + + if (!pInfo) { + *pInfoSize = length; + } else { + size_t size = *pInfoSize; + *pInfoSize = length; + + memcpy(pInfo, buf->buf, MIN2(size, length)); + + if (size < length) + result = VK_INCOMPLETE; + } + + _mesa_string_buffer_destroy(buf); + break; + default: + /* VK_SHADER_INFO_TYPE_BINARY_AMD unimplemented for now. */ + result = VK_ERROR_FEATURE_NOT_PRESENT; + break; + } + + return result; +}