X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_shader.c;h=76790a19047a86abdad5668690675f0679f1f572;hb=135e4d434f622fa1d7275bdb72f859e1c1b1976e;hp=ac36cecb67498b9248d3724d0e7f18ebee3d001a;hpb=0e10790558b01f09b9517495f7368860af47ee97;p=mesa.git diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index ac36cecb674..76790a19047 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -36,6 +36,7 @@ #include #include +#include #include "sid.h" #include "gfx9d.h" @@ -89,7 +90,7 @@ VkResult radv_CreateShaderModule( sizeof(*module) + pCreateInfo->codeSize, 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); if (module == NULL) - return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY); + return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY); module->nir = NULL; module->size = pCreateInfo->codeSize; @@ -117,7 +118,7 @@ void radv_DestroyShaderModule( } void -radv_optimize_nir(struct nir_shader *shader) +radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively) { bool progress; @@ -125,7 +126,7 @@ radv_optimize_nir(struct nir_shader *shader) progress = false; NIR_PASS_V(shader, nir_lower_vars_to_ssa); - NIR_PASS_V(shader, nir_lower_64bit_pack); + NIR_PASS_V(shader, nir_lower_pack); NIR_PASS_V(shader, nir_lower_alu_to_scalar); NIR_PASS_V(shader, nir_lower_phis_to_scalar); @@ -149,7 +150,7 @@ radv_optimize_nir(struct nir_shader *shader) if (shader->options->max_unroll_iterations) { NIR_PASS(progress, shader, nir_opt_loop_unroll, 0); } - } while (progress); + } while (progress && !optimize_conservatively); NIR_PASS(progress, shader, nir_opt_shrink_load); NIR_PASS(progress, shader, nir_opt_move_load_ubo); @@ -160,12 +161,9 @@ radv_shader_compile_to_nir(struct radv_device *device, struct radv_shader_module *module, const char *entrypoint_name, gl_shader_stage stage, - const VkSpecializationInfo *spec_info) + const VkSpecializationInfo *spec_info, + const VkPipelineCreateFlags flags) { - if (strcmp(entrypoint_name, "main") != 0) { - radv_finishme("Multiple shaders per module not really supported"); - } - nir_shader *nir; nir_function *entry_point; if (module->nir) { @@ -280,7 +278,20 @@ radv_shader_compile_to_nir(struct radv_device *device, nir_lower_tex(nir, &tex_options); nir_lower_vars_to_ssa(nir); + + if (nir->info.stage == MESA_SHADER_VERTEX || + nir->info.stage == MESA_SHADER_GEOMETRY) { + NIR_PASS_V(nir, nir_lower_io_to_temporaries, + nir_shader_get_entrypoint(nir), true, true); + } else if (nir->info.stage == MESA_SHADER_TESS_EVAL|| + nir->info.stage == MESA_SHADER_FRAGMENT) { + NIR_PASS_V(nir, nir_lower_io_to_temporaries, + nir_shader_get_entrypoint(nir), true, false); + } + + nir_split_var_copies(nir); nir_lower_var_copies(nir); + nir_lower_global_vars_to_local(nir); nir_remove_dead_variables(nir, nir_var_local); nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) { @@ -293,7 +304,8 @@ radv_shader_compile_to_nir(struct radv_device *device, .lower_vote_eq_to_ballot = 1, }); - radv_optimize_nir(nir); + if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) + radv_optimize_nir(nir, false); /* Indirect lowering must be called after the radv_optimize_nir() loop * has been called at least once. Otherwise indirect lowering can @@ -301,7 +313,7 @@ radv_shader_compile_to_nir(struct radv_device *device, * considered too large for unrolling. */ ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class); - radv_optimize_nir(nir); + radv_optimize_nir(nir, flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT); return nir; } @@ -371,16 +383,14 @@ radv_fill_shader_variant(struct radv_device *device, gl_shader_stage stage) { bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0; + struct radv_shader_info *info = &variant->info.info; unsigned vgpr_comp_cnt = 0; - if (scratch_enabled && !device->llvm_supports_spill) - radv_finishme("shader scratch support only available with LLVM 4.0"); - variant->code_size = binary->code_size; variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) | - S_00B12C_SCRATCH_EN(scratch_enabled); + S_00B12C_SCRATCH_EN(scratch_enabled); - variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | + variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) | S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) | S_00B848_DX10_CLAMP(1) | S_00B848_FLOAT_MODE(variant->config.float_mode); @@ -391,10 +401,11 @@ radv_fill_shader_variant(struct radv_device *device, variant->rsrc2 |= S_00B12C_OC_LDS_EN(1); break; case MESA_SHADER_TESS_CTRL: - if (device->physical_device->rad_info.chip_class >= GFX9) + if (device->physical_device->rad_info.chip_class >= GFX9) { vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt; - else + } else { variant->rsrc2 |= S_00B12C_OC_LDS_EN(1); + } break; case MESA_SHADER_VERTEX: case MESA_SHADER_GEOMETRY: @@ -402,8 +413,7 @@ radv_fill_shader_variant(struct radv_device *device, break; case MESA_SHADER_FRAGMENT: break; - case MESA_SHADER_COMPUTE: { - struct radv_shader_info *info = &variant->info.info; + case MESA_SHADER_COMPUTE: variant->rsrc2 |= S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) | S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) | @@ -413,7 +423,6 @@ radv_fill_shader_variant(struct radv_device *device, S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx) | S_00B84C_LDS_SIZE(variant->config.lds_size); break; - } default: unreachable("unsupported shader type"); break; @@ -421,7 +430,6 @@ radv_fill_shader_variant(struct radv_device *device, if (device->physical_device->rad_info.chip_class >= GFX9 && stage == MESA_SHADER_GEOMETRY) { - struct radv_shader_info *info = &variant->info.info; unsigned es_type = variant->info.gs.es_type; unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt; @@ -436,28 +444,106 @@ radv_fill_shader_variant(struct radv_device *device, /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and * VGPR[0:4] are always loaded. */ - if (info->uses_invocation_id) + if (info->uses_invocation_id) { gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */ - else if (info->uses_prim_id) + } else if (info->uses_prim_id) { gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */ - else if (variant->info.gs.vertices_in >= 3) + } else if (variant->info.gs.vertices_in >= 3) { gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */ - else + } else { gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */ + } variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | S_00B22C_OC_LDS_EN(es_type == MESA_SHADER_TESS_EVAL); } else if (device->physical_device->rad_info.chip_class >= GFX9 && - stage == MESA_SHADER_TESS_CTRL) + stage == MESA_SHADER_TESS_CTRL) { variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt); - else + } else { variant->rsrc1 |= S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt); + } void *ptr = radv_alloc_shader_memory(device, variant); memcpy(ptr, binary->code, binary->code_size); } +static void radv_init_llvm_target() +{ + LLVMInitializeAMDGPUTargetInfo(); + LLVMInitializeAMDGPUTarget(); + LLVMInitializeAMDGPUTargetMC(); + LLVMInitializeAMDGPUAsmPrinter(); + + /* For inline assembly. */ + LLVMInitializeAMDGPUAsmParser(); + + /* Workaround for bug in llvm 4.0 that causes image intrinsics + * to disappear. + * https://reviews.llvm.org/D26348 + * + * Workaround for bug in llvm that causes the GPU to hang in presence + * of nested loops because there is an exec mask issue. The proper + * solution is to fix LLVM but this might require a bunch of work. + * https://bugs.llvm.org/show_bug.cgi?id=37744 + * + * "mesa" is the prefix for error messages. + */ + const char *argv[3] = { "mesa", "-simplifycfg-sink-common=false", + "-amdgpu-skip-threshold=1" }; + LLVMParseCommandLineOptions(3, argv, NULL); +} + +static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT; + +static LLVMTargetRef radv_get_llvm_target(const char *triple) +{ + LLVMTargetRef target = NULL; + char *err_message = NULL; + + call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target); + + if (LLVMGetTargetFromTriple(triple, &target, &err_message)) { + fprintf(stderr, "Cannot find target for triple %s ", triple); + if (err_message) { + fprintf(stderr, "%s\n", err_message); + } + LLVMDisposeMessage(err_message); + return NULL; + } + return target; +} + +static LLVMTargetMachineRef radv_create_target_machine(enum radeon_family family, + enum ac_target_machine_options tm_options, + const char **out_triple) +{ + assert(family >= CHIP_TAHITI); + char features[256]; + const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" : "amdgcn--"; + LLVMTargetRef target = radv_get_llvm_target(triple); + + snprintf(features, sizeof(features), + "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s", + tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "", + tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "", + tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "", + tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : ""); + + LLVMTargetMachineRef tm = LLVMCreateTargetMachine( + target, + triple, + ac_get_llvm_processor_name(family), + features, + LLVMCodeGenLevelDefault, + LLVMRelocDefault, + LLVMCodeModelDefault); + + if (out_triple) + *out_triple = triple; + return tm; +} + static struct radv_shader_variant * shader_variant_create(struct radv_device *device, struct radv_shader_module *module, @@ -481,17 +567,18 @@ shader_variant_create(struct radv_device *device, options->family = chip_family; options->chip_class = device->physical_device->rad_info.chip_class; - options->dump_shader = radv_can_dump_shader(device, module); + options->dump_shader = radv_can_dump_shader(device, module, gs_copy_shader); options->dump_preoptir = options->dump_shader && device->instance->debug_flags & RADV_DEBUG_PREOPTIR; options->record_llvm_ir = device->keep_shader_info; options->tess_offchip_block_dw_size = device->tess_offchip_block_dw_size; + options->address32_hi = device->physical_device->rad_info.address32_hi; if (options->supports_spill) tm_options |= AC_TM_SUPPORTS_SPILL; if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED) tm_options |= AC_TM_SISCHED; - tm = ac_create_target_machine(chip_family, tm_options); + tm = radv_create_target_machine(chip_family, tm_options, NULL); if (gs_copy_shader) { assert(shader_count == 1); @@ -551,7 +638,7 @@ radv_shader_variant_create(struct radv_device *device, options.key = *key; options.unsafe_math = !!(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH); - options.supports_spill = device->llvm_supports_spill; + options.supports_spill = true; return shader_variant_create(device, module, shaders, shader_count, shaders[shader_count - 1]->info.stage, &options, false, code_out, code_size_out); @@ -615,16 +702,7 @@ generate_shader_stats(struct radv_device *device, unsigned max_simd_waves; unsigned lds_per_wave = 0; - switch (device->physical_device->rad_info.family) { - /* These always have 8 waves: */ - case CHIP_POLARIS10: - case CHIP_POLARIS11: - case CHIP_POLARIS12: - max_simd_waves = 8; - break; - default: - max_simd_waves = 10; - } + max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family); conf = &variant->config; @@ -709,7 +787,7 @@ radv_GetShaderInfoAMD(VkDevice _device, /* Spec doesn't indicate what to do if the stage is invalid, so just * return no info for this. */ if (!variant) - return vk_error(VK_ERROR_FEATURE_NOT_PRESENT); + return vk_error(device->instance, VK_ERROR_FEATURE_NOT_PRESENT); switch (infoType) { case VK_SHADER_INFO_TYPE_STATISTICS_AMD: