X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_shader.h;h=bfd2787a1234f26e2292df0e1340b2f12bb9229e;hb=2dd8dfd9137ac561aac3c453c1c7ad6683bd17b4;hp=d9fc64aeb9a819dc7041552a9594139ad7410528;hpb=a1fdd4a4a73604469b6204a56457b08f8ae4a948;p=mesa.git

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index d9fc64aeb9a..bfd2787a123 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -66,11 +66,17 @@ struct radv_vs_variant_key {
 	uint32_t instance_rate_inputs;
 	uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
 	uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
+	uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
+	uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
+	uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
 
 	/* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
 	 * so we may need to fix it up. */
 	uint64_t alpha_adjust;
 
+	/* For some formats the channels have to be shuffled. */
+	uint32_t post_shuffle;
+
 	uint32_t as_es:1;
 	uint32_t as_ls:1;
 	uint32_t export_prim_id:1;
@@ -331,6 +337,9 @@ struct radv_shader_slab {
 void
 radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively,
 		  bool allow_copies);
+bool
+radv_nir_lower_ycbcr_textures(nir_shader *shader,
+                             const struct radv_pipeline_layout *layout);
 
 nir_shader *
 radv_shader_compile_to_nir(struct radv_device *device,
@@ -338,7 +347,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
 			   const char *entrypoint_name,
 			   gl_shader_stage stage,
 			   const VkSpecializationInfo *spec_info,
-			   const VkPipelineCreateFlags flags);
+			   const VkPipelineCreateFlags flags,
+			   const struct radv_pipeline_layout *layout);
 
 void *
 radv_alloc_shader_memory(struct radv_device *device,