X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_shader.h;h=cb76e635dc5f7f75cff70bfdcc3e4259aa1d17e9;hb=2133e6420377f29052a60efd9471f4a946040515;hp=eb414829d96f95751ab37d10c3895241893814d1;hpb=ad2703653f306f0fa751ddfd546d1d93ce348630;p=mesa.git diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index eb414829d96..cb76e635dc5 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -34,10 +34,14 @@ #include "nir/nir.h" #include "vulkan/vulkan.h" +#include "vulkan/util/vk_object.h" + +#define RADV_VERT_ATTRIB_MAX MAX2(VERT_ATTRIB_MAX, VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS) struct radv_device; struct radv_shader_module { + struct vk_object_base base; struct nir_shader *nir; unsigned char sha1[20]; uint32_t size; @@ -59,6 +63,7 @@ struct radv_vs_out_key { uint32_t export_prim_id:1; uint32_t export_layer_id:1; uint32_t export_clip_dists:1; + uint32_t export_viewport_index:1; }; struct radv_vs_variant_key { @@ -103,6 +108,7 @@ struct radv_fs_variant_key { uint8_t num_samples; uint32_t is_int8; uint32_t is_int10; + bool is_dual_src; }; struct radv_cs_variant_key { @@ -123,6 +129,11 @@ struct radv_shader_variant_key { bool has_multiview_view_index; }; +enum radv_compiler_debug_level { + RADV_COMPILER_DEBUG_LEVEL_PERFWARN, + RADV_COMPILER_DEBUG_LEVEL_ERROR, +}; + struct radv_nir_compiler_options { struct radv_pipeline_layout *layout; struct radv_shader_variant_key key; @@ -132,13 +143,22 @@ struct radv_nir_compiler_options { bool dump_shader; bool dump_preoptir; bool record_ir; + bool record_stats; bool check_ir; bool has_ls_vgpr_init_bug; bool use_ngg_streamout; + bool enable_mrt_output_nan_fixup; enum radeon_family family; enum chip_class chip_class; uint32_t tess_offchip_block_dw_size; uint32_t address32_hi; + + struct { + void (*func)(void *private_data, + enum radv_compiler_debug_level level, + const char *message); + void *private_data; + } debug; }; enum radv_ud_index { @@ -247,7 +267,7 @@ struct radv_shader_info { bool is_ngg_passthrough; struct { uint64_t ls_outputs_written; - uint8_t input_usage_mask[VERT_ATTRIB_MAX]; + uint8_t input_usage_mask[RADV_VERT_ATTRIB_MAX]; uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1]; bool has_vertex_buffers; /* needs vertex buffers and base/start */ bool needs_draw_id; @@ -257,6 +277,7 @@ struct radv_shader_info { bool as_es; bool as_ls; bool export_prim_id; + uint8_t num_linked_outputs; } vs; struct { uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1]; @@ -271,6 +292,7 @@ struct radv_shader_info { unsigned output_prim; unsigned invocations; unsigned es_type; /* GFX9: VS or TES */ + uint8_t num_linked_inputs; } gs; struct { uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1]; @@ -282,6 +304,9 @@ struct radv_shader_info { bool ccw; bool point_mode; bool export_prim_id; + uint8_t num_linked_inputs; + uint8_t num_linked_patch_inputs; + uint8_t num_linked_outputs; } tes; struct { bool force_persample; @@ -293,15 +318,18 @@ struct radv_shader_info { bool has_pcoord; bool prim_id_input; bool layer_input; + bool viewport_index_input; uint8_t num_input_clips_culls; uint32_t input_mask; uint32_t flat_shaded_mask; uint32_t explicit_shaded_mask; uint32_t float16_shaded_mask; uint32_t num_interp; + uint32_t cb_shader_mask; bool can_discard; bool early_fragment_test; bool post_depth_coverage; + uint8_t depth_layout; } ps; struct { bool uses_grid_size; @@ -313,9 +341,14 @@ struct radv_shader_info { struct { uint64_t outputs_written; uint64_t patch_outputs_written; + uint64_t tes_inputs_read; + uint64_t tes_patch_inputs_read; unsigned tcs_vertices_out; uint32_t num_patches; - uint32_t lds_size; + uint32_t num_lds_blocks; + uint8_t num_linked_inputs; + uint8_t num_linked_outputs; + uint8_t num_linked_patch_outputs; } tcs; struct radv_streamout_info so; @@ -420,14 +453,10 @@ radv_shader_compile_to_nir(struct radv_device *device, const struct radv_pipeline_layout *layout, unsigned subgroup_size, unsigned ballot_bit_size); -void * -radv_alloc_shader_memory(struct radv_device *device, - struct radv_shader_variant *shader); - void radv_destroy_shader_slabs(struct radv_device *device); -void +VkResult radv_create_shaders(struct radv_pipeline *pipeline, struct radv_device *device, struct radv_pipeline_cache *cache, @@ -449,14 +478,15 @@ radv_shader_variant_compile(struct radv_device *device, struct radv_pipeline_layout *layout, const struct radv_shader_variant_key *key, struct radv_shader_info *info, - bool keep_shader_info, + bool keep_shader_info, bool keep_statistic_info, struct radv_shader_binary **binary_out); struct radv_shader_variant * radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir, struct radv_shader_info *info, struct radv_shader_binary **binary_out, - bool multiview, bool keep_shader_info); + bool multiview, bool keep_shader_info, + bool keep_statistic_info); void radv_shader_variant_destroy(struct radv_device *device, @@ -517,46 +547,52 @@ shader_io_get_unique_index(gl_varying_slot slot) } static inline unsigned -calculate_tess_lds_size(unsigned tcs_num_input_vertices, +calculate_tess_lds_size(enum chip_class chip_class, + unsigned tcs_num_input_vertices, unsigned tcs_num_output_vertices, unsigned tcs_num_inputs, unsigned tcs_num_patches, - unsigned tcs_outputs_written, - unsigned tcs_per_patch_outputs_written) + unsigned tcs_num_outputs, + unsigned tcs_num_patch_outputs) { - unsigned num_tcs_outputs = util_last_bit64(tcs_outputs_written); - unsigned num_tcs_patch_outputs = util_last_bit64(tcs_per_patch_outputs_written); - unsigned input_vertex_size = tcs_num_inputs * 16; - unsigned output_vertex_size = num_tcs_outputs * 16; + unsigned output_vertex_size = tcs_num_outputs * 16; unsigned input_patch_size = tcs_num_input_vertices * input_vertex_size; unsigned pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size; - unsigned output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16; + unsigned output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16; unsigned output_patch0_offset = input_patch_size * tcs_num_patches; - return output_patch0_offset + output_patch_size * tcs_num_patches; + unsigned lds_size = output_patch0_offset + output_patch_size * tcs_num_patches; + + if (chip_class >= GFX7) { + assert(lds_size <= 65536); + lds_size = align(lds_size, 512) / 512; + } else { + assert(lds_size <= 32768); + lds_size = align(lds_size, 256) / 256; + } + + return lds_size; } static inline unsigned get_tcs_num_patches(unsigned tcs_num_input_vertices, unsigned tcs_num_output_vertices, unsigned tcs_num_inputs, - unsigned tcs_outputs_written, - unsigned tcs_per_patch_outputs_written, + unsigned tcs_num_outputs, + unsigned tcs_num_patch_outputs, unsigned tess_offchip_block_dw_size, enum chip_class chip_class, enum radeon_family family) { uint32_t input_vertex_size = tcs_num_inputs * 16; uint32_t input_patch_size = tcs_num_input_vertices * input_vertex_size; - uint32_t num_tcs_outputs = util_last_bit64(tcs_outputs_written); - uint32_t num_tcs_patch_outputs = util_last_bit64(tcs_per_patch_outputs_written); - uint32_t output_vertex_size = num_tcs_outputs * 16; + uint32_t output_vertex_size = tcs_num_outputs * 16; uint32_t pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size; - uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16; + uint32_t output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16; /* Ensure that we only need one wave per SIMD so we don't need to check * resource usage. Also ensures that the number of tcs in and out