X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fradv_shader_info.c;h=2c8d4e0511fc57f2f1a608c1c0a7c41e29820fea;hb=f038b3a136175c0afcc6545b886238a7b5dcf515;hp=dc4aea1d2198bb141007128b9123a1164773aad2;hpb=70cc80805ce5b027bece7334349ae8b028bf2862;p=mesa.git

diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index dc4aea1d219..2c8d4e0511f 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -403,7 +403,7 @@ gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var,
 	unsigned attrib_count = glsl_count_attribute_slots(var->type, true);
 	int idx = var->data.location;
 
-	if (idx >= VERT_ATTRIB_GENERIC0 && idx <= VERT_ATTRIB_GENERIC15)
+	if (idx >= VERT_ATTRIB_GENERIC0 && idx < VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS)
 		info->vs.has_vertex_buffers = true;
 
 	for (unsigned i = 0; i < attrib_count; ++i) {
@@ -668,7 +668,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
 			  const struct radv_pipeline_layout *layout,
 			  const struct radv_shader_variant_key *key,
 			  struct radv_shader_info *info,
-			  bool use_aco)
+			  bool use_llvm)
 {
 	struct nir_function *func =
 		(struct nir_function *)exec_list_get_head_const(&nir->functions);
@@ -679,14 +679,14 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
 		info->loads_dynamic_offsets = true;
 	}
 
-	nir_foreach_variable(variable, &nir->inputs)
+	nir_foreach_shader_in_variable(variable, nir)
 		gather_info_input_decl(nir, variable, info, key);
 
 	nir_foreach_block(block, func->impl) {
 		gather_info_block(nir, block, info);
 	}
 
-	nir_foreach_variable(variable, &nir->outputs)
+	nir_foreach_shader_out_variable(variable, nir)
 		gather_info_output_decl(nir, variable, info, key);
 
 	if (nir->info.stage == MESA_SHADER_VERTEX ||
@@ -822,13 +822,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
 		struct radv_es_output_info *es_info =
 			nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info;
 
-		if (use_aco) {
-			/* The outputs don't contain gaps, se we can use the number of outputs */
-			uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
-				? info->vs.num_linked_outputs
-				: info->tes.num_linked_outputs;
-			es_info->esgs_itemsize = num_outputs_written * 16;
-		} else {
+		if (use_llvm) {
 			/* The outputs may contain gaps, use the highest output index + 1 */
 			uint32_t max_output_written = 0;
 			uint64_t output_mask = nir->info.outputs_written;
@@ -839,8 +833,13 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
 
 				max_output_written = MAX2(param_index, max_output_written);
 			}
-
 			es_info->esgs_itemsize = (max_output_written + 1) * 16;
+		} else {
+			/* The outputs don't contain gaps, se we can use the number of outputs */
+			uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX
+				? info->vs.num_linked_outputs
+				: info->tes.num_linked_outputs;
+			es_info->esgs_itemsize = num_outputs_written * 16;
 		}
 	}
 
@@ -858,5 +857,9 @@ radv_nir_shader_info_pass(const struct nir_shader *nir,
 				info->ps.cb_shader_mask |= 0xf << (i * 4);
 			}
 		}
+
+		if (key->fs.is_dual_src) {
+			info->ps.cb_shader_mask |= (info->ps.cb_shader_mask & 0xf) << 4;
+		}
 	}
 }