X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fsi_cmd_buffer.c;h=0692124bf51653ff3a38dea8c350676144673a5f;hb=f89d3874fb9744dff2e699ca9414ed9dea4febe7;hp=15edaa4b2b51caf1b3936d118e5194ac834ac1ce;hpb=893e19efb74edd6133a607e09338bf5d449632f1;p=mesa.git diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 15edaa4b2b5..0692124bf51 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -37,114 +37,20 @@ static void si_write_harvested_raster_configs(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, unsigned raster_config, unsigned raster_config_1) { - unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1); unsigned num_se = MAX2(physical_device->rad_info.max_se, 1); - unsigned rb_mask = physical_device->rad_info.enabled_rb_mask; - unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16); - unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2); - unsigned rb_per_se = num_rb / num_se; - unsigned se_mask[4]; + unsigned raster_config_se[4]; unsigned se; - se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; - se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; - se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; - se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; - - assert(num_se == 1 || num_se == 2 || num_se == 4); - assert(sh_per_se == 1 || sh_per_se == 2); - assert(rb_per_pkr == 1 || rb_per_pkr == 2); - - /* XXX: I can't figure out what the *_XSEL and *_YSEL - * fields are for, so I'm leaving them as their default - * values. */ - - if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || - (!se_mask[2] && !se_mask[3]))) { - raster_config_1 &= C_028354_SE_PAIR_MAP; - - if (!se_mask[0] && !se_mask[1]) { - raster_config_1 |= - S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3); - } else { - raster_config_1 |= - S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0); - } - } + ac_get_harvested_configs(&physical_device->rad_info, + raster_config, + &raster_config_1, + raster_config_se); for (se = 0; se < num_se; se++) { - unsigned raster_config_se = raster_config; - unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); - unsigned pkr1_mask = pkr0_mask << rb_per_pkr; - int idx = (se / 2) * 2; - - if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { - raster_config_se &= C_028350_SE_MAP; - - if (!se_mask[idx]) { - raster_config_se |= - S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3); - } else { - raster_config_se |= - S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0); - } - } - - pkr0_mask &= rb_mask; - pkr1_mask &= rb_mask; - if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { - raster_config_se &= C_028350_PKR_MAP; - - if (!pkr0_mask) { - raster_config_se |= - S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3); - } else { - raster_config_se |= - S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0); - } - } - - if (rb_per_se >= 2) { - unsigned rb0_mask = 1 << (se * rb_per_se); - unsigned rb1_mask = rb0_mask << 1; - - rb0_mask &= rb_mask; - rb1_mask &= rb_mask; - if (!rb0_mask || !rb1_mask) { - raster_config_se &= C_028350_RB_MAP_PKR0; - - if (!rb0_mask) { - raster_config_se |= - S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3); - } else { - raster_config_se |= - S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0); - } - } - - if (rb_per_se > 2) { - rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); - rb1_mask = rb0_mask << 1; - rb0_mask &= rb_mask; - rb1_mask &= rb_mask; - if (!rb0_mask || !rb1_mask) { - raster_config_se &= C_028350_RB_MAP_PKR1; - - if (!rb0_mask) { - raster_config_se |= - S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3); - } else { - raster_config_se |= - S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0); - } - } - } - } - /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ if (physical_device->rad_info.chip_class < CIK) radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, @@ -155,9 +61,7 @@ si_write_harvested_raster_configs(struct radv_physical_device *physical_device, radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1)); - radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se); - if (physical_device->rad_info.chip_class >= CIK) - radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); + radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]); } /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ @@ -170,11 +74,14 @@ si_write_harvested_raster_configs(struct radv_physical_device *physical_device, radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1)); + + if (physical_device->rad_info.chip_class >= CIK) + radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); } static void si_emit_compute(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs) + struct radeon_cmdbuf *cs) { radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); radeon_emit(cs, 0); @@ -228,90 +135,15 @@ static unsigned radv_pack_float_12p4(float x) static void si_set_raster_config(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs) + struct radeon_cmdbuf *cs) { unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16); unsigned rb_mask = physical_device->rad_info.enabled_rb_mask; unsigned raster_config, raster_config_1; - switch (physical_device->rad_info.family) { - case CHIP_TAHITI: - case CHIP_PITCAIRN: - raster_config = 0x2a00126a; - raster_config_1 = 0x00000000; - break; - case CHIP_VERDE: - raster_config = 0x0000124a; - raster_config_1 = 0x00000000; - break; - case CHIP_OLAND: - raster_config = 0x00000082; - raster_config_1 = 0x00000000; - break; - case CHIP_HAINAN: - raster_config = 0x00000000; - raster_config_1 = 0x00000000; - break; - case CHIP_BONAIRE: - raster_config = 0x16000012; - raster_config_1 = 0x00000000; - break; - case CHIP_HAWAII: - raster_config = 0x3a00161a; - raster_config_1 = 0x0000002e; - break; - case CHIP_FIJI: - if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) { - /* old kernels with old tiling config */ - raster_config = 0x16000012; - raster_config_1 = 0x0000002a; - } else { - raster_config = 0x3a00161a; - raster_config_1 = 0x0000002e; - } - break; - case CHIP_POLARIS10: - raster_config = 0x16000012; - raster_config_1 = 0x0000002a; - break; - case CHIP_POLARIS11: - case CHIP_POLARIS12: - raster_config = 0x16000012; - raster_config_1 = 0x00000000; - break; - case CHIP_TONGA: - raster_config = 0x16000012; - raster_config_1 = 0x0000002a; - break; - case CHIP_ICELAND: - if (num_rb == 1) - raster_config = 0x00000000; - else - raster_config = 0x00000002; - raster_config_1 = 0x00000000; - break; - case CHIP_CARRIZO: - raster_config = 0x00000002; - raster_config_1 = 0x00000000; - break; - case CHIP_KAVERI: - /* KV should be 0x00000002, but that causes problems with radeon */ - raster_config = 0x00000000; /* 0x00000002 */ - raster_config_1 = 0x00000000; - break; - case CHIP_KABINI: - case CHIP_MULLINS: - case CHIP_STONEY: - raster_config = 0x00000000; - raster_config_1 = 0x00000000; - break; - default: - fprintf(stderr, - "radv: Unknown GPU, using 0 for raster_config\n"); - raster_config = 0x00000000; - raster_config_1 = 0x00000000; - break; - } + ac_get_raster_config(&physical_device->rad_info, + &raster_config, + &raster_config_1); /* Always use the default config when all backends are enabled * (or when we failed to determine the enabled backends). @@ -331,7 +163,7 @@ si_set_raster_config(struct radv_physical_device *physical_device, static void si_emit_config(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs) + struct radeon_cmdbuf *cs) { int i; @@ -567,7 +399,7 @@ void si_init_config(struct radv_cmd_buffer *cmd_buffer) void cik_create_gfx_config(struct radv_device *device) { - struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX); + struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX); if (!cs) return; @@ -624,7 +456,7 @@ get_viewport_xform(const VkViewport *viewport, } void -si_write_viewport(struct radeon_winsys_cs *cs, int first_vp, +si_write_viewport(struct radeon_cmdbuf *cs, int first_vp, int count, const VkViewport *viewports) { int i; @@ -683,7 +515,7 @@ static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) { } void -si_write_scissors(struct radeon_winsys_cs *cs, int first, +si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors, const VkViewport *viewports, bool can_use_guardband) { @@ -840,7 +672,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, } -void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, +void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, bool predicated, enum chip_class chip_class, bool is_mec, @@ -890,7 +722,7 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, } void -si_emit_wait_fence(struct radeon_winsys_cs *cs, +si_emit_wait_fence(struct radeon_cmdbuf *cs, bool predicated, uint64_t va, uint32_t ref, uint32_t mask) @@ -905,7 +737,7 @@ si_emit_wait_fence(struct radeon_winsys_cs *cs, } static void -si_emit_acquire_mem(struct radeon_winsys_cs *cs, +si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool predicated, bool is_gfx9, @@ -932,7 +764,7 @@ si_emit_acquire_mem(struct radeon_winsys_cs *cs, } void -si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, +si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uint32_t *flush_cnt, uint64_t flush_va, @@ -1207,7 +1039,7 @@ static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t src_va, unsigned size, unsigned flags) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint32_t header = 0, command = 0; assert(size); @@ -1485,7 +1317,7 @@ unsigned radv_cayman_get_maxdist(int log_samples) return max_dist[log_samples]; } -void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples) +void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples) { switch (nr_samples) { default: