X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Famd%2Fvulkan%2Fsi_cmd_buffer.c;h=0692124bf51653ff3a38dea8c350676144673a5f;hb=f89d3874fb9744dff2e699ca9414ed9dea4febe7;hp=e61f5b8fa476a0df35178f37404d17116f0fb264;hpb=305745457c12fd54ff98d2f090dcebee27d5d33e;p=mesa.git diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index e61f5b8fa47..0692124bf51 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -37,142 +37,51 @@ static void si_write_harvested_raster_configs(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, unsigned raster_config, unsigned raster_config_1) { - unsigned sh_per_se = MAX2(physical_device->rad_info.max_sh_per_se, 1); unsigned num_se = MAX2(physical_device->rad_info.max_se, 1); - unsigned rb_mask = physical_device->rad_info.enabled_rb_mask; - unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16); - unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2); - unsigned rb_per_se = num_rb / num_se; - unsigned se_mask[4]; + unsigned raster_config_se[4]; unsigned se; - se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; - se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; - se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; - se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; - - assert(num_se == 1 || num_se == 2 || num_se == 4); - assert(sh_per_se == 1 || sh_per_se == 2); - assert(rb_per_pkr == 1 || rb_per_pkr == 2); - - /* XXX: I can't figure out what the *_XSEL and *_YSEL - * fields are for, so I'm leaving them as their default - * values. */ - - if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || - (!se_mask[2] && !se_mask[3]))) { - raster_config_1 &= C_028354_SE_PAIR_MAP; - - if (!se_mask[0] && !se_mask[1]) { - raster_config_1 |= - S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3); - } else { - raster_config_1 |= - S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0); - } - } + ac_get_harvested_configs(&physical_device->rad_info, + raster_config, + &raster_config_1, + raster_config_se); for (se = 0; se < num_se; se++) { - unsigned raster_config_se = raster_config; - unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); - unsigned pkr1_mask = pkr0_mask << rb_per_pkr; - int idx = (se / 2) * 2; - - if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { - raster_config_se &= C_028350_SE_MAP; - - if (!se_mask[idx]) { - raster_config_se |= - S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3); - } else { - raster_config_se |= - S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0); - } - } - - pkr0_mask &= rb_mask; - pkr1_mask &= rb_mask; - if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { - raster_config_se &= C_028350_PKR_MAP; - - if (!pkr0_mask) { - raster_config_se |= - S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3); - } else { - raster_config_se |= - S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0); - } - } - - if (rb_per_se >= 2) { - unsigned rb0_mask = 1 << (se * rb_per_se); - unsigned rb1_mask = rb0_mask << 1; - - rb0_mask &= rb_mask; - rb1_mask &= rb_mask; - if (!rb0_mask || !rb1_mask) { - raster_config_se &= C_028350_RB_MAP_PKR0; - - if (!rb0_mask) { - raster_config_se |= - S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3); - } else { - raster_config_se |= - S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0); - } - } - - if (rb_per_se > 2) { - rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); - rb1_mask = rb0_mask << 1; - rb0_mask &= rb_mask; - rb1_mask &= rb_mask; - if (!rb0_mask || !rb1_mask) { - raster_config_se &= C_028350_RB_MAP_PKR1; - - if (!rb0_mask) { - raster_config_se |= - S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3); - } else { - raster_config_se |= - S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0); - } - } - } - } - /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ if (physical_device->rad_info.chip_class < CIK) - radeon_set_config_reg(cs, GRBM_GFX_INDEX, - SE_INDEX(se) | SH_BROADCAST_WRITES | - INSTANCE_BROADCAST_WRITES); + radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, + S_00802C_SE_INDEX(se) | + S_00802C_SH_BROADCAST_WRITES(1) | + S_00802C_INSTANCE_BROADCAST_WRITES(1)); else radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1)); - radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se); - if (physical_device->rad_info.chip_class >= CIK) - radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); + radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]); } /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ if (physical_device->rad_info.chip_class < CIK) - radeon_set_config_reg(cs, GRBM_GFX_INDEX, - SE_BROADCAST_WRITES | SH_BROADCAST_WRITES | - INSTANCE_BROADCAST_WRITES); + radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, + S_00802C_SE_BROADCAST_WRITES(1) | + S_00802C_SH_BROADCAST_WRITES(1) | + S_00802C_INSTANCE_BROADCAST_WRITES(1)); else radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1)); + + if (physical_device->rad_info.chip_class >= CIK) + radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); } static void si_emit_compute(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs) + struct radeon_cmdbuf *cs) { radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); radeon_emit(cs, 0); @@ -226,90 +135,15 @@ static unsigned radv_pack_float_12p4(float x) static void si_set_raster_config(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs) + struct radeon_cmdbuf *cs) { unsigned num_rb = MIN2(physical_device->rad_info.num_render_backends, 16); unsigned rb_mask = physical_device->rad_info.enabled_rb_mask; unsigned raster_config, raster_config_1; - switch (physical_device->rad_info.family) { - case CHIP_TAHITI: - case CHIP_PITCAIRN: - raster_config = 0x2a00126a; - raster_config_1 = 0x00000000; - break; - case CHIP_VERDE: - raster_config = 0x0000124a; - raster_config_1 = 0x00000000; - break; - case CHIP_OLAND: - raster_config = 0x00000082; - raster_config_1 = 0x00000000; - break; - case CHIP_HAINAN: - raster_config = 0x00000000; - raster_config_1 = 0x00000000; - break; - case CHIP_BONAIRE: - raster_config = 0x16000012; - raster_config_1 = 0x00000000; - break; - case CHIP_HAWAII: - raster_config = 0x3a00161a; - raster_config_1 = 0x0000002e; - break; - case CHIP_FIJI: - if (physical_device->rad_info.cik_macrotile_mode_array[0] == 0x000000e8) { - /* old kernels with old tiling config */ - raster_config = 0x16000012; - raster_config_1 = 0x0000002a; - } else { - raster_config = 0x3a00161a; - raster_config_1 = 0x0000002e; - } - break; - case CHIP_POLARIS10: - raster_config = 0x16000012; - raster_config_1 = 0x0000002a; - break; - case CHIP_POLARIS11: - case CHIP_POLARIS12: - raster_config = 0x16000012; - raster_config_1 = 0x00000000; - break; - case CHIP_TONGA: - raster_config = 0x16000012; - raster_config_1 = 0x0000002a; - break; - case CHIP_ICELAND: - if (num_rb == 1) - raster_config = 0x00000000; - else - raster_config = 0x00000002; - raster_config_1 = 0x00000000; - break; - case CHIP_CARRIZO: - raster_config = 0x00000002; - raster_config_1 = 0x00000000; - break; - case CHIP_KAVERI: - /* KV should be 0x00000002, but that causes problems with radeon */ - raster_config = 0x00000000; /* 0x00000002 */ - raster_config_1 = 0x00000000; - break; - case CHIP_KABINI: - case CHIP_MULLINS: - case CHIP_STONEY: - raster_config = 0x00000000; - raster_config_1 = 0x00000000; - break; - default: - fprintf(stderr, - "radv: Unknown GPU, using 0 for raster_config\n"); - raster_config = 0x00000000; - raster_config_1 = 0x00000000; - break; - } + ac_get_raster_config(&physical_device->rad_info, + &raster_config, + &raster_config_1); /* Always use the default config when all backends are enabled * (or when we failed to determine the enabled backends). @@ -329,7 +163,7 @@ si_set_raster_config(struct radv_physical_device *physical_device, static void si_emit_config(struct radv_physical_device *physical_device, - struct radeon_winsys_cs *cs) + struct radeon_cmdbuf *cs) { int i; @@ -507,6 +341,7 @@ si_emit_config(struct radv_physical_device *physical_device, switch (physical_device->rad_info.family) { case CHIP_VEGA10: + case CHIP_VEGA12: pc_lines = 4096; break; case CHIP_RAVEN: @@ -516,12 +351,6 @@ si_emit_config(struct radv_physical_device *physical_device, assert(0); } - radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL, - S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF)); - /* TODO: Enable the binner: */ - radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0, - S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) | - S_028C44_DISABLE_START_OF_PRIM(1)); radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1, S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) | S_028C48_MAX_PRIM_PER_BATCH(1023)); @@ -542,6 +371,21 @@ si_emit_config(struct radv_physical_device *physical_device, S_028004_ZPASS_INCREMENT_DISABLE(1)); } + /* Enable the Polaris small primitive filter control. + * XXX: There is possibly an issue when MSAA is off (see RadeonSI + * has_msaa_sample_loc_bug). But this doesn't seem to regress anything, + * and AMDVLK doesn't have a workaround as well. + */ + if (physical_device->rad_info.family >= CHIP_POLARIS10) { + unsigned small_prim_filter_cntl = + S_028830_SMALL_PRIM_FILTER_ENABLE(1) | + /* Workaround for a hw line bug. */ + S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12); + + radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL, + small_prim_filter_cntl); + } + si_emit_compute(physical_device, cs); } @@ -555,7 +399,7 @@ void si_init_config(struct radv_cmd_buffer *cmd_buffer) void cik_create_gfx_config(struct radv_device *device) { - struct radeon_winsys_cs *cs = device->ws->cs_create(device->ws, RING_GFX); + struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX); if (!cs) return; @@ -572,7 +416,8 @@ cik_create_gfx_config(struct radv_device *device) cs->cdw * 4, 4096, RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS| - RADEON_FLAG_NO_INTERPROCESS_SHARING); + RADEON_FLAG_NO_INTERPROCESS_SHARING | + RADEON_FLAG_READ_ONLY); if (!device->gfx_init) goto fail; @@ -611,7 +456,7 @@ get_viewport_xform(const VkViewport *viewport, } void -si_write_viewport(struct radeon_winsys_cs *cs, int first_vp, +si_write_viewport(struct radeon_cmdbuf *cs, int first_vp, int count, const VkViewport *viewports) { int i; @@ -650,10 +495,10 @@ static VkRect2D si_scissor_from_viewport(const VkViewport *viewport) get_viewport_xform(viewport, scale, translate); - rect.offset.x = translate[0] - abs(scale[0]); - rect.offset.y = translate[1] - abs(scale[1]); - rect.extent.width = ceilf(translate[0] + abs(scale[0])) - rect.offset.x; - rect.extent.height = ceilf(translate[1] + abs(scale[1])) - rect.offset.y; + rect.offset.x = translate[0] - fabs(scale[0]); + rect.offset.y = translate[1] - fabs(scale[1]); + rect.extent.width = ceilf(translate[0] + fabs(scale[0])) - rect.offset.x; + rect.extent.height = ceilf(translate[1] + fabs(scale[1])) - rect.offset.y; return rect; } @@ -670,14 +515,15 @@ static VkRect2D si_intersect_scissor(const VkRect2D *a, const VkRect2D *b) { } void -si_write_scissors(struct radeon_winsys_cs *cs, int first, +si_write_scissors(struct radeon_cmdbuf *cs, int first, int count, const VkRect2D *scissors, const VkViewport *viewports, bool can_use_guardband) { int i; float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY; const float max_range = 32767.0f; - assert(count); + if (!count) + return; radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + first * 4 * 2, count * 2); for (i = 0; i < count; i++) { @@ -743,21 +589,21 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool ia_switch_on_eop = false; bool ia_switch_on_eoi = false; bool partial_vs_wave = false; - bool partial_es_wave = cmd_buffer->state.pipeline->graphics.partial_es_wave; + bool partial_es_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_es_wave; bool multi_instances_smaller_than_primgroup; multi_instances_smaller_than_primgroup = indirect_draw; if (!multi_instances_smaller_than_primgroup && instanced_draw) { uint32_t num_prims = radv_prims_for_vertices(&cmd_buffer->state.pipeline->graphics.prim_vertex_count, draw_vertex_count); - if (num_prims < cmd_buffer->state.pipeline->graphics.primgroup_size) + if (num_prims < cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.primgroup_size) multi_instances_smaller_than_primgroup = true; } - ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_switch_on_eoi; - partial_vs_wave = cmd_buffer->state.pipeline->graphics.partial_vs_wave; + ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi; + partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave; if (chip_class >= CIK) { - wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.wd_switch_on_eop; + wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop; /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0. * We don't know that for indirect drawing, so treat it as @@ -817,7 +663,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, } } - return cmd_buffer->state.pipeline->graphics.base_ia_multi_vgt_param | + return cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.base | S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) | S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) | @@ -826,7 +672,7 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, } -void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, +void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, bool predicated, enum chip_class chip_class, bool is_mec, @@ -876,7 +722,7 @@ void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs, } void -si_emit_wait_fence(struct radeon_winsys_cs *cs, +si_emit_wait_fence(struct radeon_cmdbuf *cs, bool predicated, uint64_t va, uint32_t ref, uint32_t mask) @@ -891,7 +737,7 @@ si_emit_wait_fence(struct radeon_winsys_cs *cs, } static void -si_emit_acquire_mem(struct radeon_winsys_cs *cs, +si_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool predicated, bool is_gfx9, @@ -918,8 +764,7 @@ si_emit_acquire_mem(struct radeon_winsys_cs *cs, } void -si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, - bool predicated, +si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum chip_class chip_class, uint32_t *flush_cnt, uint64_t flush_va, @@ -950,7 +795,7 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, /* Necessary for DCC */ if (chip_class >= VI) { si_cs_emit_write_event_eop(cs, - predicated, + false, chip_class, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, @@ -964,12 +809,12 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, } if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); } if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); } @@ -982,13 +827,18 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, } if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); } if (chip_class >= GFX9 && flush_cb_db) { unsigned cb_db_event, tc_flags; +#if 0 + /* This breaks a bunch of: + dEQP-VK.renderpass.dedicated_allocation.formats.d32_sfloat_s8_uint.input*. + use the big hammer always. + */ /* Set the CB/DB flush event. */ switch (flush_cb_db) { case RADV_CMD_FLAG_FLUSH_AND_INV_CB: @@ -1001,25 +851,30 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, /* both CB & DB */ cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT; } - - /* TC | TC_WB = invalidate L2 data - * TC_MD | TC_WB = invalidate L2 metadata - * TC | TC_WB | TC_MD = invalidate L2 data & metadata +#else + cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT; +#endif + /* These are the only allowed combinations. If you need to + * do multiple operations at once, do them separately. + * All operations that invalidate L2 also seem to invalidate + * metadata. Volatile (VOL) and WC flushes are not listed here. * - * The metadata cache must always be invalidated for coherency - * between CB/DB and shaders. (metadata = HTILE, CMASK, DCC) - * - * TC must be invalidated on GFX9 only if the CB/DB surface is - * not pipe-aligned. If the surface is RB-aligned, it might not - * strictly be pipe-aligned since RB alignment takes precendence. + * TC | TC_WB = writeback & invalidate L2 & L1 + * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC + * TC_WB | TC_NC = writeback L2 for MTYPE == NC + * TC | TC_NC = invalidate L2 for MTYPE == NC + * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.) + * TCL1 = invalidate L1 */ - tc_flags = EVENT_TC_WB_ACTION_ENA | - EVENT_TC_MD_ACTION_ENA; + tc_flags = EVENT_TC_ACTION_ENA | + EVENT_TC_MD_ACTION_ENA; /* Ideally flush TC together with CB/DB. */ if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) { - tc_flags |= EVENT_TC_ACTION_ENA | - EVENT_TCL1_ACTION_ENA; + /* Writeback and invalidate everything in L2 & L1. */ + tc_flags = EVENT_TC_ACTION_ENA | + EVENT_TC_WB_ACTION_ENA; + /* Clear the flags. */ flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 | @@ -1029,14 +884,14 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, assert(flush_cnt); uint32_t old_fence = (*flush_cnt)++; - si_cs_emit_write_event_eop(cs, predicated, chip_class, false, cb_db_event, tc_flags, 1, + si_cs_emit_write_event_eop(cs, false, chip_class, false, cb_db_event, tc_flags, 1, flush_va, old_fence, *flush_cnt); - si_emit_wait_fence(cs, predicated, flush_va, *flush_cnt, 0xffffffff); + si_emit_wait_fence(cs, false, flush_va, *flush_cnt, 0xffffffff); } /* VGT state sync */ if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, predicated)); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); } @@ -1049,13 +904,13 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, RADV_CMD_FLAG_INV_GLOBAL_L2 | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) && !is_mec) { - radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, predicated)); + radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); radeon_emit(cs, 0); } if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) || (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) { - si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9, + si_emit_acquire_mem(cs, is_mec, false, chip_class >= GFX9, cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | S_0085F0_TCL1_ACTION_ENA(1) | @@ -1069,7 +924,7 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, * * WB doesn't work without NC. */ - si_emit_acquire_mem(cs, is_mec, predicated, + si_emit_acquire_mem(cs, is_mec, false, chip_class >= GFX9, cp_coher_cntl | S_0301F0_TC_WB_ACTION_ENA(1) | @@ -1078,7 +933,7 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, } if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) { si_emit_acquire_mem(cs, is_mec, - predicated, chip_class >= GFX9, + false, chip_class >= GFX9, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1)); cp_coher_cntl = 0; @@ -1089,7 +944,7 @@ si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, * Therefore, it should be last. Done in PFP. */ if (cp_coher_cntl) - si_emit_acquire_mem(cs, is_mec, predicated, chip_class >= GFX9, cp_coher_cntl); + si_emit_acquire_mem(cs, is_mec, false, chip_class >= GFX9, cp_coher_cntl); } void @@ -1119,7 +974,6 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) ptr = &cmd_buffer->gfx9_fence_idx; } si_cs_emit_cache_flush(cmd_buffer->cs, - cmd_buffer->state.predicating, cmd_buffer->device->physical_device->rad_info.chip_class, ptr, va, radv_cmd_buffer_uses_mec(cmd_buffer), @@ -1185,7 +1039,7 @@ static void si_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t src_va, unsigned size, unsigned flags) { - struct radeon_winsys_cs *cs = cmd_buffer->cs; + struct radeon_cmdbuf *cs = cmd_buffer->cs; uint32_t header = 0, command = 0; assert(size); @@ -1463,7 +1317,7 @@ unsigned radv_cayman_get_maxdist(int log_samples) return max_dist[log_samples]; } -void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples) +void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples) { switch (nr_samples) { default: